Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
  • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
  • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
  • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
  • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
  • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
  • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
  • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
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  • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
  • H01L24/27—Manufacturing methods
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  • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
  • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
  • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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  • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
  • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
  • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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  • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
  • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
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  • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
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  • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
  • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
  • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
  • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
  • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
• • H—ELECTRICITY
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  • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
  • H01L2223/544—Marks applied to semiconductor devices or parts
  • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
  • H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
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  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
  • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
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  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
  • H01L2224/27—Manufacturing methods
  • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
• • H—ELECTRICITY
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  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
  • H01L2224/8319—Arrangement of the layer connectors prior to mounting
  • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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  • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
  • H01L2224/838—Bonding techniques
  • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• • H—ELECTRICITY
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  • H01L2924/01—Chemical elements
  • H01L2924/01029—Copper [Cu]
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  • H01L2924/01047—Silver [Ag]
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  • H01L2924/078—Adhesive characteristics other than chemical
  • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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  • H01L2924/06—Polymers
  • H01L2924/078—Adhesive characteristics other than chemical
  • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
  • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
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  • H01L2924/10—Details of semiconductor or other solid state devices to be connected
  • H01L2924/11—Device type
  • H01L2924/14—Integrated circuits
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  • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
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  • H01L2924/30—Technical effects
  • H01L2924/301—Electrical effects
  • H01L2924/3011—Impedance

Definitions

• the present invention relates to a method for handling thinned chips for insertion into chip cards.
• Thinned chips have been used for some time to produce vertically integrated circuit structures (VIC).
• VIP vertically integrated circuit structures
• DE 4433 846 AI describes how a wafer, in this case a so-called top substrate, with its front side, i. with the active or functional IC surface on which the component layers are located, glued onto a so-called handling substrate by means of an adhesive layer and then thinned from the back. This thinning takes place e.g. by wet chemical etching or by mechanical or chemomechanical grinding.
• a top substrate is then provided with an adhesive layer, precisely adjusted and placed on a so-called bottom substrate and connected to it. The handling substrate is then removed again.
• a similar method is known from EP 0531 723 B, in which a first circuit component with its active surface is attached to a carrier and then thinned from the rear. A further circuit component is then placed on the back of the thinned chip and connected to it by means of contact points that were previously generated on the back of the thinned chip. Then the attached circuit component is also thinned from the back, provided with contact points and another circuit component is attached. This step is repeated several times until the desired multi-element pack of components lying one above the other is finally built up. All of these processes only describe the handling of the chips at a process stage in which they have either not yet been thinned or have already been built into a stable package.
• the invention is therefore based on the object of specifying a method with which thinned chips can also be handled individually and introduced into chip cards.
• the starting point in each case is that a front of the wafer, on which the components are located, is first glued onto a carrier substrate by means of an adhesive layer. This wafer is then thinned from the back. After thinning, the wafer is divided into individual chips by sawing into the wafer from the rear. The sawing can take place up to or into the adhesive layer or even into the carrier substrate.
• the adhesive layer is dissolved and the individual chips are lifted off the carrier substrate with a suction head. They are then preferably stored in a special storage container for further processing. With this method, the chips lie with their backs up in the special containers. Alternatively, the chips can of course also be processed immediately, for example immediately placed on a chip card or chip card film.
• a further method step is provided in which, after sawing, the individual chips still on the carrier substrate are covered on the back with a continuous carrier film by means of a second adhesive layer.
• the first adhesive layer is then dissolved using a method in which the second adhesive layer is retained.
• the chips can then be lifted together from the carrier substrate in a coherent manner.
• the individual chips can then be removed from the carrier film by dissolving the second adhesive layer.
• removal can be carried out with the aid of a suction head or the like. With this method, the active front side of the chip is on top.
• the carrier film glues this carrier film directly after thinning the wafer, and only then to saw the wafer into individual chips.
• the film remains on the individual chip; the chip is thus reinforced by the carrier film and can also be handled using conventional methods and tools.
• suitable, for example tough, elastic materials for the carrier film this can be kept relatively thin with sufficient stability of the chip-film composite.
• the chips can be temporarily stored in a storage container in the course of further processing.
• Adhesive layer between the wafer and carrier substrate, or instead of this adhesive layer, the carrier substrate itself is dissolved. It goes without saying that a method is selected for this in the method according to claim 2 or 3, in which the second adhesive layer is not attacked.
• the thinner chips which are safe and easy to handle with the method according to the invention, are more flexible and require less space than the conventional chips. This opens up new possibilities for accommodating the chips in the chip cards.
• chip is applied to a chip card film which is provided on the rear side opposite the chip with contact areas which are in turn connected to the chip via conductor tracks through the film.
• This chip module constructed in this way can then be inserted with the contact surfaces outside into a cavity of a chip card, as is also the case with the previous conventional chip card structures.
• the chip is simply applied to the surface of a chip card.
• the chip is preferably placed with its front facing outward and then the chip card is provided with conductor tracks together with the chip.
• the conductor tracks can be applied using an embossing or printing process, preferably using a screen printing process. Due to the small size of the thinned chip, it is hardly applied to the surface of the chip card. Of course, it is also possible to place the chip in a flat cavity in the surface of the chip card bring in.
• the chips which are open on the surface are advantageously coated with a protective lacquer.
• FIG. 1 shows a wafer which is connected on its active surface by means of an adhesive layer to a carrier substrate
• FIG. 2a shows a wafer according to FIG. 1 after thinning and dividing into individual chips
• FIG. 4b shows a chip produced according to FIG. 4a on a chip card
• FIG. 6 is a perspective view of a thinned chip with position markings
• a wafer 1 with its front side, which has the components 2 is first glued onto a carrier substrate 4.
• a carrier substrate e.g. another wafer, a metal foil or magnetizable foil or another foil that is common in chip card production, such as PVC, ABS, PC or the like.
• an adhesive layer 3 is applied either to the wafer 1 or to the carrier substrate 4, and the two parts are then joined together.
• the wafer usually contains a plurality of circuits arranged side by side, each of which can form a standard chip card chip or a memory chip.
• the wafer 1 fastened on the carrier substrate 4 is then thinned from the rear side to a predetermined thickness, as shown by the broken line 9 in FIG. 1.
• the thinning can be done with the conventional methods, for example by etching or mechanical grinding. In this way, it is possible to thin the wafer 1 or the chips 10 made therefrom to a thickness of less than 100 ⁇ m, preferably approximately 20 ⁇ m.
• saw cuts 7 are then inserted into the wafer 1 from the rear up to the adhesive layer 3, and thus the wafer 1 is divided into individual chips 10.
• the adhesive layer 3 is then dissolved or loosened, the chips 10 being lifted off the carrier substrate 4 with a suction head 30 and placed in special containers 40, where they are available for further processing.
• the suction head 30 for the removal of the thin chips 10 is relatively flat and has a plurality of small holes 31 on the suction surface, which can be acted upon by suction or compressed air for sucking or depositing the chips 10 via a line as required.
• the chips 10 can be removed from the special containers 40 in the same way and placed with a robot during card production.
• the adhesive layer 3 of the carrier substrate 4 can be detached by the action of heat.
• a heatable suction head 30 or a separate heat radiation source 34, as in FIG. 4a, is used.
• 3a and 3b show an alternative method in which the active surface with the components 2 of the chips 10 is ultimately on top.
• a carrier film 5 is applied to the thinned and sawn wafer 1 by means of a second adhesive layer 6.
• this carrier film 5 can also be a self-adhesive film which is already provided with an adhesive layer.
• the first adhesive layer 3 is released using a method which does not attack the second adhesive layer 6.
• the first adhesive layer 3 consists of an adhesive which is decomposed under the influence of light of a certain wavelength range, for example UV light, the second adhesive layer 6 being cured during this irradiation.
• the first adhesive layer 3 consists of an adhesive that decomposes under the action of heat, the second adhesive layer 6 curing precisely under the action of heat.
• the first adhesive layer 3 consists of a water-soluble adhesive, while the second adhesive layer 6 is not water-soluble, or the second adhesive layer 6 is solvent-resistant and the first adhesive layer 3 dissolves with the corresponding solvent.
• the first adhesive layer 3 consists of an adhesive which is placed under an oxygen plasma or in a certain gas environment, e.g. Ozone is decomposed, the second adhesive layer 6 being resistant to these conditions.
• the carrier substrate 4 can do this consist of styrofoam or another material which decomposes in a plasma or under the action of etching gas or at elevated temperature. Or a carrier substrate 4 made of cardboard or a similar material is used, which is water-soluble.
• the entire association of chips 10 connected via the carrier film 5 can then be removed together, the active surface of the chips 10 pointing outwards.
• the individual chips 10 can then be removed from the carrier film 5 by loosening the second adhesive layer 6.
• a carrier film 5 made of a preferably tough-elastic material such as polycarbonate, polyamide, copper, aluminum, steel or the like is first glued onto the back of the wafer 1 by means of an adhesive layer 6.
• the wafer 1 is then only subdivided into the individual chips 10 by inserting the saw cuts 7. Finally, the individual chips 10 are removed again by dissolving the first adhesive layer 3 or the carrier substrate 4, a method also being used for this purpose
• FIG. 4 a shows schematically how a single chip 10 with a suction head 30 is removed from the carrier substrate 4, the adhesive layer 3 being dissolved by a heat radiator 34, the second adhesive layer 6 curing at the same time. In this method, the carrier film 5 remains on the back of the individual thin chip 10.
• FIGS. 5 to 10 show different variants of how the thinned chips 10 can be accommodated in or on the chip card 20.
• the chips 10 With their front side or with their rear side on a chip card 20 or a chip card film 21. If the front side of the chip 10 is placed on the chip card 20 or chip card film 21, it is expedient to first attach the conductor tracks 11 for contacting the chip 10 to the card 20 or film 21 and then to position the chip 10 thereon.
• the chip 10 has, on its rear side, as shown in FIG. 6, position markings 8 which are, for example, printed or etched onto the chip 10 or onto the carrier film 5.
• FIG. 5 describes an installation example which is similar to the known installation methods of conventional chip modules.
• the chip 10 is first placed on a first chip card film 21.
• On the opposite back of the chip card film 21 are located
• a subdivision 15 can be located between the chip 10 and the first chip card film 21. This chip module constructed in this way is inserted into a corresponding cavity 24 of the chip card 20 and glued all around with a suitable adhesive 25.
• FIGS. 10 and 11 show different lamination methods in which the chip 10 is arranged between two chip card foils 21 and 22 in the chip card 20.
• the chip card foils 21, 22 typically have one
• the chip 10 is applied to one chip card film 21 and the conductor tracks 11 are located on the other chip card film 22. The back of the chip 10 is applied to the chip card film 21. Then the two chip card foils are positioned one above the other and laminated together so that the chip 10 is contacted by the conductor tracks 11 (Fig. 10b).
• conductor tracks 11 are first applied to the one chip card film 21.
• the chip 10 is then placed with its front facing downward on these conductor tracks 11, so that contact is made at the same time.
• the second chip card film 22 is then laminated over it (FIG. 11b).
• the conductor tracks each lead to an external contact surface or to an interface component with which contactless data transmission is possible, or they themselves form such a component.
• the surface of the first chip card film 21 can be covered with an oxygen or
• Chlorine plasma are pretreated so that the chip 10 adheres to the cover and laminated thereon.
• the surface can also be printed with a silver conductive paste, which simultaneously forms the conductor tracks 11, so that the chip 10 adheres to the cover and for lamination on the chip card film 21 and is simultaneously contacted electrically.
• an adhesive to the thinned chip 10 or to use an adhesive-coated film as the chip card film 21.
• 7, 8 and 9 a completely new method is shown, in which the thinned chip is simply placed on the surface of a chip card and then printed with conductor tracks 11.
• the chip 10 is also coated with a protective lacquer 12.
• a screen printing method is preferably used to print the conductor tracks 11. It is of course also possible to apply the conductor tracks 11 in the form of a metal foil.
• FIG. 12 a to 12 c show embodiments in which the conductor tracks are first applied to the surface and then the chip is placed face down on the pads 11.
• an additional lacquer and / or adhesive layer 13 is arranged between the integrated circuit 10 and the surface of the chip card 20, while in FIG. 12c the chip / conductor track arrangement 10, 11 is pressed into the card surface with a heating stamp 14.
• the thin chip 10 is also located directly on the surface of the chip card 20, but here in a small cavity 27.
• This cavity 27 is either embossed into the chip card 20, milled or molded on when the chip card 20 is manufactured been (Fig. 8).
• the cavity 27 is produced by appropriate printing with protective lacquer 26 or by pulling on a protective film with a window (FIG. 9).
• FIGS. 13a to 13c Corresponding arrangements in which the contact surfaces 11 are first arranged in the cutouts in the surface of the chip card 20, on which the chip 10 is then placed, are shown in FIGS. 13a to 13c.
• the chip is pressed flush under the action of heat into the surface of the chip card 20.
• the film with the chip flush with the surface can be printed, coated with silver paste, for example, and possibly contacted at the same time.

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• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Manufacturing & Machinery (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Credit Cards Or The Like (AREA)

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• 1999
  • 1999-05-07 DE DE19921230A patent/DE19921230B4/de not_active Expired - Fee Related
• 2000
  • 2000-05-04 JP JP2000617491A patent/JP2002544669A/ja active Pending
  • 2000-05-04 EP EP00927133A patent/EP1183726A1/de not_active Withdrawn
  • 2000-05-04 CN CNB008072833A patent/CN1157779C/zh not_active Expired - Fee Related
  • 2000-05-04 AU AU45612/00A patent/AU4561200A/en not_active Abandoned
  • 2000-05-04 WO PCT/EP2000/003988 patent/WO2000068990A1/de active Application Filing

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