EP1139426A2 - Mémoire semi-conductrice non-volatile et son procédé de fabrication - Google Patents

Mémoire semi-conductrice non-volatile et son procédé de fabrication Download PDF

Info

Publication number
EP1139426A2
EP1139426A2 EP01301827A EP01301827A EP1139426A2 EP 1139426 A2 EP1139426 A2 EP 1139426A2 EP 01301827 A EP01301827 A EP 01301827A EP 01301827 A EP01301827 A EP 01301827A EP 1139426 A2 EP1139426 A2 EP 1139426A2
Authority
EP
European Patent Office
Prior art keywords
cell
gate
floating
impurity diffusion
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01301827A
Other languages
German (de)
English (en)
Other versions
EP1139426A3 (fr
Inventor
Yoshimitsu Yamauchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of EP1139426A2 publication Critical patent/EP1139426A2/fr
Publication of EP1139426A3 publication Critical patent/EP1139426A3/fr
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0491—Virtual ground arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the present invention relates to a nonvolatile semiconductor memory, a method of reading from and writing to the same, and a method of manufacturing the same. More particularly, it relates to a nonvolatile semiconductor memory having cells of split gate (SPG) structure and being capable of high integration, a method of reading from and writing to the same, and a method of manufacturing the same.
  • SPG split gate
  • Virtual grounding structure has been proposed with a view to reducing the size of memory cells in a nonvolatile semiconductor memory,.
  • one bit line can be omitted, because a bit line does not need to contact an impurity diffusion layer which functions as a drain, and a source of a cell can serve as a drain of another cell adjacent to the cell so that one bit line can be omitted. Therefore, scaling of the cells is easily performed and an area of the cells can be minimized in NOR structures.
  • the virtual grounding structure is suited to realize large capacity.
  • An example of a conventional virtual grounding structure is described in Japanese Unexamined Patent Publication No. HEI 6 (1994)-196711. Now referring to Fig. 22, the conventional technique is explained.
  • a buried bit line 51 in a semiconductor substrate 50 of the first conductivity type is asymmetrically constituted of a low concentration impurity diffusion layer 52 of the second conductivity type and a high concentration impurity diffusion layer 53 of the second conductivity type.
  • the impurity diffusion layer 52 overlaps with a floating gate 54a of an adjacent memory cell and the impurity diffusion layer 53 overlaps with a floating gate 54b of another adjacent memory cell. That is, the buried bit line 51 serves as a source of a cell and a drain of a cell adjacent to the cell.
  • a virtual grounding structure with SPG cells has been known (Japanese Unexamined Patent Publication No. HEI 5 (1993)-152579).
  • floating gates 62a and 62b are provided as sidewall spacers on the sidewalls of a SPG 61 in the channel direction, respectively and a control gate 63 is provided along the channel direction.
  • an impurity diffusion layer 65a which is capacitively coupled with the floating gate 62a and an impurity diffusion layer 65b which is capacitively coupled with the floating gate 62b and the SPG 61 are formed in a surface layer of a semiconductor substrate 64.
  • the impurity diffusion layer 65b is also coupled capacitively with the floating gate 62a of an adjacent cell.
  • Various methods of rewriting the memory cells have been known, for example, a method of injecting electrons from the substrate to the floating gate or from the floating gate to the drain with use of Fowler-Nordheim (FN) tunnel current, and a method of injecting electrons from the source to the floating gate or from the drain to the floating gate with use of channel hot electrons (CHE).
  • FN Fowler-Nordheim
  • CHE channel hot electrons
  • the memory is more miniaturized and the gate is formed shorter, dielectric strength between the source and the drain is reduced and writing errors are resulted. Accordingly the reduction of the cell area is difficult.
  • Fig. 24(a) is a plan view for illustrating the difficulty in reducing the cell area by the conventional technique described above.
  • Figs. 24(b) and 24(c) are cross-sections cut along the lines A-A' and B-B' shown in Fig. 24(a), respectively.
  • reference numeral 71 signifies a diffused bit line
  • 72 a low concentration impurity diffusion layer
  • 73 a high concentration impurity diffusion layer
  • 74 a floating gate
  • 75 a control gate.
  • Fig. 24(b) is a cross section in the direction parallel to the control gate
  • Fig. 24(c) is a cross section in the direction vertical to the control gate.
  • the size of the memory cell in the direction parallel to the control gate will be Lg (channel length between the source and the drain) + F (bit line width).
  • the size of the memory cell in the X direction (horizontal to the control gate) will be 3F.
  • the size in the Y direction (vertical to the control gate) will be 2F, which is the sum of the size F of a portion where the floating gate and the control gate overlaps with each other and the size F of a portion between the memory cells.
  • the memory cell area in the virtual grounding structure according to the prior art is 6F 2 .
  • the actual minimum area 4F 2 is difficult to realize by the prior art technique.
  • an additional transistor (a SPG transistor) is required between the source and the drain, so that the area occupied by the transistor has been an obstacle to the scaling.
  • nonvolatile semiconductor memory including at least two cells each comprising:
  • the present invention further provides a method of reading data from the above-described nonvolatile semiconductor memory, wherein the data reading from one cell is performed by grounding the impurity diffusion layer of said one cell and applying a voltage to an impurity diffusion layer of another adjacent cell, or by applying a voltage to the impurity diffusion layer of said one cell and grounding the impurity diffusion layer of said another adjacent cell.
  • a method of reading data from the above-described nonvolatile semiconductor memory wherein the data reading from one cell is performed by applying a voltage to the SPG of said one cell and avoiding voltage application to a SPG of another adjacent cell to isolate said one cell from said another adjacent cell.
  • a method of writing/erasing data to/from the above-described nonvolatile semiconductor memory wherein the data writing/erasing is performed by utilizing FN tunnel current flowing between the floating gate and the semiconductor substrate or the floating gate and the impurity diffusion layer of one cell.
  • a method of writing data to the above-described nonvolatile semiconductor memory wherein the data writing to one cell is performed by applying a predetermined voltage to the impurity diffusion layer of said one cell and grounding an impurity diffusion layer of another cell to flow electric current, and applying a first voltage to the SPG to weakly invert a channel region facing the SPG to inject hot electrons from an edge of the SPG.
  • a method of data writing to the above-described nonvolatile semiconductor memory wherein the data writing to one cell is performed by applying a predetermined voltage to the impurity diffusion layer of said one cell and grounding an impurity diffusion layer of another cell to flow electric current, and applying a second voltage to the SPG to strongly invert a channel region facing the SPG to inject hot electrons from the impurity diffusion layer of said one cell.
  • a method of manufacturing a nonvolatile semiconductor memory comprising the steps of:
  • a method of manufacturing a nonvolatile semiconductor memory comprising the steps of:
  • a method of manufacturing a nonvolatile semiconductor memory comprising the steps of:
  • a method of manufacturing a nonvolatile semiconductor memory comprising the steps of:
  • a method of manufacturing a nonvolatile semiconductor memory comprising the steps of:
  • the SPG transistor comprising the SPG and the impurity diffusion layer is buried in the trench, the memory cell area of 4F 2 , which is the actual minimum value, is achieved without any influence from the structure of the SPG, and thus a nonvolatile semiconductor memory of large capacity is provided.
  • Fig. 1(a) is a schematic plan view illustrating an example of a memory cell of the nonvolatile semiconductor memory according to the present invention.
  • Figs. 1(b) to 1(d) are sectional views, among which Fig. 1(b) is cut along a plane X1-X1' (parallel to the channel direction), Fig. 1(c) is cut along a plane Y1-Y1' (vertical to the channel direction) and Fig. 1(d) is cut along a plane Y2-Y2' (vertical to the channel direction).
  • Fig. 2 is an equivalent circuit diagram of the memory cell of Fig. 1(a).
  • the memory cell of the nonvolatile semiconductor memory comprises N + -type impurity diffusion layers 2 and 3 formed in a surface layer of a semiconductor substrate 1 of P-type silicon.
  • a floating gate 5 of polysilicon is formed with the intervention of a tunnel oxide film (a first insulating film) 4 and a SPG 7 of polysilicon is formed with the intervention of a gate oxide film of SiO 2 (a second insulating film) 6.
  • a control gate 9 is provided on the floating gate with the intervention of an ONO film 8 (a third insulating film).
  • the first, second and third insulating films may be an oxide film, a nitride film or a layered structure of these films.
  • the above-mentioned conductivity types of the semiconductor substrate and the impurity diffusion layer may be replaced.
  • the memory cell itself may be formed in a well.
  • the impurity diffusion layer 2 functions as a source in a cell and a drain in another cell adjacent to the cell.
  • the tunnel oxide film may be 3 to 10 nm thick (e.g., 9 nm) and the gate oxide film may be 5 to 30 nm thick (e.g., 20 nm).
  • a tunnel oxide film 4 is formed by thermal oxidization on a semiconductor substrate 1 of a first conductivity type. Then, a polysilicon layer 5a of 10-200 nm thick (e.g., 50 nm), an oxide film 10 of 5-50 nm thick (e.g., 20 nm) and a nitride film 11 of 10-500 nm thick (e.g., 200 nm) are formed in this order over the tunnel oxide film 4.
  • a resist mask 12 is provided thereon and desired portions of the nitride film 11, the oxide film 10, the polysilicon layer 5a and the tunnel oxide film 4 are etched away (see Fig. 3(a)).
  • thermal oxidization is performed at 600-1100°C to form sidewall spacers 13 of a silicon oxide film on the sidewalls of the polysilicon layer 5a.
  • a polysilicon layer 7a for forming the SPG is deposited between the sidewall spacers 13 and then planarization is performed by etch back until the nitride film 11 is exposed (see Fig. 3(b)).
  • the nitride film 11 serves as an etch stopper.
  • a resist mask 14 is formed to have an opening over a sidewall spacer 13 between the polysilicon film 7a of a cell and the polysilicon layer 5a of another cell adjacent thereto along the channel direction.
  • the sidewall spacer 13 is removed to expose the semiconductor substrate 1.
  • ion implantation with As, for example, is performed to form impurity diffusion layers 2 and 3 in the surface layer of the semiconductor substrate (see Fig. 3(c)).
  • the ion implantation is carried out under an accelerating voltage of 5-30 kev (e.g., 15 kev) and an implantation amount of 1 ⁇ 10 13 to 1 ⁇ 10 16 cm -2 (e.g., 1 ⁇ 10 14 cm -2 ).
  • a thermal treatment is performed at 600-1100°C (e.g., 800°C) to form a silicon oxide film (an insulating film) 15 on the polysilicon layer 7a and in a portion from which the sidewall spacer 13 was removed in the previous step (see Fig. 4(a)).
  • the thermal treatment revives the crystallinity of the implanted region and activates the implanted impurities.
  • the polysilicon layer 7a turns to be a SPG 7.
  • the nitride film 11 and the oxide film 10 are sequentially etched away (see Fig. 4(b)).
  • the edges of the insulating film 15 is slightly etched and rounded through the etching step, which is favorable for the reduction of level difference.
  • a polysilicon layer 5b is deposited to a thickness of 40-400 nm (e.g., 100 nm) and patterned using a resist mask 16 (see Fig. 4(c)). This step increases an overlapping area between the floating gate and the control gate. As a result, gate capacitance coupling ratio increases and voltage consumption is lowered.
  • This embodiment employs the polysilicon layer 5b for the above reason, but it may be omitted.
  • a third insulating film made of an ONO film 8 and a polysilicon layer 9a are deposited and then patterning is performed for forming word lines. Accordingly, the polysilicon layers 5a, 5b and 9a and the ONO film 8 are sequentially etched to form a floating gate and a control gate in self-alignment (Fig. 4(d)).
  • BPSG Bipolar Phosphorus Silicate Glass
  • CG signifies the control gate and FG signifies the floating gate.
  • Reading Structure CG SPG Drain Source Substrate READ 1 Source 3V 3V 0 1V 0 READ 2 Drain 3V 3V 1V 0 0 Writing/ Erasing Structure CG SPG Drain Source Substrate WRITE 1 FN FG-substrate 20V 0 0 0 0 WRITE 2 FN FG-substrate -20V 0 0 0 0 WRITE 3 FN FG-drain -12V 0 4V 0 0 WRITE 4 CHE Source 12V 2V 4V 0 0 WRITE 5 CHE Drain 12V 12V 6V 0 0 0
  • Tables 1 and 2 indicate writing and rewriting, respectively. These operations can be performed in different modes. The modes are described below.
  • a sidewall spacer 13 located between the polysilicon layer 7a and the polysilicon layer 5a is removed to expose the semiconductor substrate 1. Further, ion implantation is carried out under the same conditions as employed in the step shown in Fig. 3(c) to form impurity diffusion layers 2 and 3 and a floating impurity diffusion layer 17 in the surface layer of the semiconductor substrate (see Fig. 6(c)).
  • Embodiment 3 The same method of writing and reading as employed in Embodiment 1 is also applicable to the nonvolatile semiconductor memory according to Embodiment 2.
  • Embodiment 3 is also applicable to the nonvolatile semiconductor memory according to Embodiment 2.
  • Fig. 8(a) is a schematic plan view illustrating an example of the nonvolatile semiconductor memory according to the present invention.
  • Figs. 8(b) to 8(d) are sectional views, among which Fig. 1(b) is cut along a plane X1-X1' (parallel to the channel direction (X direction)), Fig. 8(c) is cut along a plane Y1-Y1' (vertical to the channel direction (Y direction)) and Fig. 8(d) is cut along a plane Y2-Y2' (vertical to the channel direction).
  • the memory cell of the nonvolatile semiconductor memory comprises a semiconductor substrate 1 of P-type silicon in which trenches 18 are formed and N + -type impurity diffusion layers 2 and 3 formed on a sidewall of each of the trenches 18.
  • SPGs 7 of polysilicon are buried in the trenches 18 with the intervention of a gate oxide film 6 of SiO 2 .
  • Floating gates 5 of polysilicon are formed on a flat surface of the semiconductor substrate 1 sandwiched between the trenches 18 with the intervention of a tunnel oxide film 4 and control gates 9 are formed on the floating gates with the intervention of a third insulating film of an ONO film 8.
  • the first, second and third insulating films may be an oxide film, a nitride film, or a layered structure of these films.
  • the conductivity types of the semiconductor substrate and the impurity diffusion layer may be replaced. Further, the memory cell itself may be formed in a well.
  • the impurity diffusion layer 2 functions as a source in a cell and a drain in another cell adjacent to the cell.
  • the tunnel oxide film may be 3-10 nm thick (e.g., 9 nm) and the gate oxide film may be 5-30 nm thick (e.g., 20 nm).
  • the size of the memory cell in the X direction is the sum of the length F of a portion where the floating gate is located and the length F of a portion where the buried SPG is located. That is, the size in the X direction is 2F.
  • the size of the memory cell in the Y direction is the sum of the length F of a portion where the floating gate and the control gate overlap with each other and the length F of a clearance isolating the memory cells. That is, the size of the memory cell in the Y direction is 2F.
  • the memory cell structure of the present invention realizes the actual minimum memory cell area of 4F 2 .
  • a tunnel oxide film 4 is formed by thermal oxidization at 600-1100°C on a semiconductor substrate 1 of a first conductivity type. Then, a polysilicon layer 5a of 10-200 nm thick (e.g., 50 nm), an oxide film 10 of 5-50 nm (e.g., 20 nm) and a nitride film 11 of 10-500 nm thick (e.g., 200 nm) are sequentially formed over the tunnel oxide film 4. Then, a resist mask 12 is formed to remove the nitride film 11, the polysilicon layer 5a and the oxide film 10 by etching (see Fig. 10(a)).
  • the tunnel oxide film 4 is etched away and the resist mask 12 is removed. Thereafter, oblique ion implantation of As, for example, is performed to form impurity diffusion layers 2a and 3a each overlapping with the polysilicon layer 5a at least at one side in the X direction (see Fig. 10(b)).
  • the oblique ion implantation is carried out with an accelerating voltage of 5-30 kev (e.g., 15 kev) and an implantation amount of 1 ⁇ 10 13 to 1 ⁇ 10 16 cm -2 (e.g., 1 ⁇ 10 14 cm -2 ).
  • a thermal treatment is performed at 600-1100°C (e.g., 800°C) for re-crystallization of the implanted region.
  • 600-1100°C e.g. 800°C
  • a layered film of the oxide film and the nitride film is used as the insulating film on the floating gate, but the nitride film may solely be used.
  • the semiconductor substrate is etched to form a trench 18.
  • the impurity diffusion layers 2a and 3a remain only in regions overlapping with the gate (see Fig. 11(a)) and serve as the impurity diffusion layers 2 and 3, respectively.
  • the surface of the trench 18 is thermally oxidized to form a gate oxide film 6, and then a polysilicon layer 7a is deposited to bury the trench 18 (e.g., to a thickness of 100 nm). Thereafter, the surface is planarized by CMP (see Fig. 11(b)).
  • the sidewalls of the polysilicon layer 5a are also oxidized and formed into insulating portions 6a. The insulating portions 6a prevent leak current between the floating gate and the SPG.
  • the polysilicon layer 7a buried in the trench 18 is etched back so that the level of the remaining polysilicon layer 7a will preferably be equal to or higher than that of the semiconductor substrate 1 (see Fig. 12(a)).
  • the surface of the SPG is thermally oxidized at 600-1100°C (e.g., 800°C) and a HDP oxide film (insulating film) 15 is deposited. Then the oxide film on the floating gate is removed by CMP or etch back (see Fig. 12(b)). In this step, the nitride film 11 serves as an etch stopper. Wet etching is also applicable in place of CMP and etch back.
  • the nitride film 11 is removed with hot phosphoric acid or by chemical dry etching and then the oxide film 10 on the floating gate 5 is removed by light dipping into a HF solution.
  • the etching rate of the insulating film 15 is greater than that of the thermally oxidized film and the like, the edges of the remaining insulating film 15 are tapered (see Fig. 13(a)). The thus tapered shape facilitates the fabrication of the control gate and the floating gate in a later step.
  • a polysilicon layer 5b of 10-200 nm thick (e.g., 50 nm) is deposited and patterned using a resist mask 16 (see Fig. 13(b)). This step is performed to increase an overlapping area between the floating gate and the control gate. As a result, the gate capacitance coupling ratio increases and voltage consumption is lowered.
  • This embodiment employs the polysilicon layer 5b for the above reason, but it may be omitted.
  • a third insulating film of an ONO film 8 and a polysilicon layer 9a are deposited.
  • patterning for forming word lines is performed to sequentially etch the polysilicon layers 5a and 5b and 9a and the ONO layer 8, thereby forming a floating gate and a control gate in self-alignment (see Fig. 14).
  • a protective film such as BPSG is deposited (not shown).
  • Embodiment 4 The method of writing and reading as employed in Embodiment 1 is also applicable to the nonvolatile semiconductor memory according to Embodiment 3.
  • Embodiment 4 is also applicable to the nonvolatile semiconductor memory according to Embodiment 3.
  • the polysilicon layer 5b is layered on the polysilicon layer 5a as shown in Fig. 14.
  • the polysilicon layer 5b may possibly cause misalignment with the polysilicon layer 5a. Therefore, photolithography under a sub rule (with a resist mask having openings smaller than F) is employed to achieve the memory cell area of 4F 2 .
  • Embodiment 4 of the present invention provides a manufacture method which realizes the memory cell area of 4F 2 without utilizing the sub rule.
  • a polysilicon layer 5b is deposited and a nitride film 18a is deposited thereon.
  • the nitride film 18a is patterned using a resist mask 19 which is formed without depending on the sub rule (see Fig. 15(a)).
  • the resist mask 19 is removed, a nitride film is further deposited and etched back to form spacers 18b on the sidewalls of the nitride film 18a.
  • the spacers 18b prevent the misalignment.
  • the polysilicon layer 5b is patterned using the nitride film 18a and the spacers 18b as a mask (see Fig. 15(b)).
  • a polysilicon layer 9a is deposited and patterning for forming the word lines is performed to sequentially etch the polysilicon layers 5a, 5b and 9a, the nitride film 18a and the spacer 18b.
  • a floating gate and a control gate are formed in self-alignment.
  • a protective film such as BPSG is deposited (not shown).
  • Embodiment 5 The method of writing and reading employed in Embodiment 1 is also applicable to the nonvolatile semiconductor memory according to Embodiment 4. Embodiment 5
  • Embodiment 5 provides a manufacturing method which achieves the memory cell area of 4F 2 without utilizing the sub rule.
  • a polysilicon layer 5b is deposited and planarization is performed by CMP until the insulating film 15 is exposed.
  • a layered floating gate structure is formed in self-alignment (see Fig. 16(b)).
  • an ONO film 8 and a polysilicon layer 9a are deposited and patterning for forming the word lines is performed to sequentially etch the polysilicon layers 5a, 5b and 9a and the ONO film 8.
  • a floating gate and a control gate are formed in self-alignment.
  • a protective film such as BPSG is deposited (not shown).
  • Embodiment 6 The method of writing and reading employed in Embodiment 1 is also applicable to the nonvolatile semiconductor memory according to Embodiment 5.
  • Embodiment 6 is also applicable to the nonvolatile semiconductor memory according to Embodiment 5.
  • the impurity diffusion layer is provided to overlap with the floating gate only. Increase in resistance of the impurity diffusion layer causes increase in array noise due to CR (return) delay and substrate bias effect during data reading. Therefore, the reduction of the resistance of the impurity diffusion layer has been demanded.
  • a silicon oxide film is deposited by CVD and etched back to form sidewall spacers 20 on the sidewalls of the layered structure along the channel direction.
  • a trench is formed in self-alignment (see Fig. 17). Since the sidewall spacers 20 are provided, the widths of the impurity diffusion layers 2 and 3 become greater than those of Embodiment 3. As a result, the resistance of the impurity diffusion layer is reduced.
  • Embodiment 3 Thereafter, the manufacturing steps of Embodiment 3 are repeated to provide a nonvolatile semiconductor memory of the present invention in which the memory cell area of 4F 2 is realized.
  • Embodiment 7 The method of writing and reading employed in Embodiment 1 is also applicable to the nonvolatile semiconductor memory according to Embodiment 6.
  • Embodiment 7 is also applicable to the nonvolatile semiconductor memory according to Embodiment 6.
  • Embodiment 7 is a variety of Embodiment 6 described above.
  • ion implantation of As is performed to form an impurity diffusion layer between the floating gates.
  • the ion implantation is performed with an accelerating voltage of 5-30 kev (e.g., 15 kev) and an implantation amount of 1 ⁇ 10 13 to 1 ⁇ 10 16 cm -2 (e.g., 1 ⁇ 10 14 cm -2 ).
  • annealing is performed at 600-1100°C (e.g., 800°C).
  • a thermal oxidization at 600-1100°C (e.g., 800°C) is then carried out to form sidewall spacers on the sidewalls of the layered structure on the substrate in the channel direction.
  • 600-1100°C e.g. 800°C
  • the trench is formed in self-alignment.
  • the impurity diffusion layers which serve as the source and the drain, respectively, are formed.
  • Embodiment 3 Thereafter, the manufacturing steps of Embodiment 3 are repeated to complete the nonvolatile semiconductor memory of the present invention in which the memory cell area of 4F 2 is realized.
  • Embodiment 8 The method of writing and reading employed in Embodiment 1 is also applicable to the nonvolatile semiconductor memory according to Embodiment 7.
  • Embodiment 8 the method of writing and reading employed in Embodiment 1 is also applicable to the nonvolatile semiconductor memory according to Embodiment 7.
  • Embodiment 8 the method of writing and reading employed in Embodiment 1 is also applicable to the nonvolatile semiconductor memory according to Embodiment 7.
  • Embodiment 8 provides a nonvolatile semiconductor memory provided with a SPG formed in the trench and a floating impurity diffusion layer, realizing the memory cell of 4F 2 .
  • a tunnel oxide film 4 is formed by thermal oxidization on a semiconductor substrate 1 of a first conductivity type. Then, a polysilicon layer 5a of 10-200 nm thick (e.g., 50 nm), an oxide film 10 of 5-50 nm thick (e.g., 20 nm) and a nitride film 11 of 10-500 nm thick (e.g., 200 nm) are sequentially formed over the tunnel oxide film 4. After a resist mask 12 is formed, the nitride film 11, the polysilicon layer 5a and the oxide film 11 are etched away (see Fig. 18(a)).
  • ion implantation of As is performed vertically to the semiconductor substrate 1 to form an impurity diffusion layer 21 in a surface layer of the exposed semiconductor substrate (see Fig. 18(b)).
  • the impurity diffusion layer 21 extends in the surface layer of the semiconductor substrate to contact the edges of the tunnel oxide film 4.
  • the ion implantation is carried out under an accelerating voltage of 5-30 kev (e.g., 15 kev) and an implantation amount of 1 ⁇ 10 13 to 1 ⁇ 10 16 cm -2 (e.g., 1 ⁇ 10 14 cm -2 ).
  • a thermal treatment is performed at 600-1100°C (e.g., 800°C) for re-crystallization of the implanted region.
  • 600-1100°C e.g. 800°C
  • a layered structure of the oxide film and the nitride film is used as an insulating film on the floating gate, the nitride film may solely be used.
  • the semiconductor substrate is etched to form a trench 18.
  • the impurity diffusion layer 21 remains only in portions overlapping with the gate and formed into impurity diffusion layers 2 and 3 and a floating impurity layer 22 (see Fig. 19(a)).
  • the surface of the trench 18 is thermally oxidized to form a gate oxide film 6.
  • a polysilicon layer 7a is deposited to fill the trench 18 (e.g., to a thickness of 100 nm) and then planarization is performed by CMP (see Fig. 19(b)).
  • the polysilicon layer 7a buried in the trench 18 is etched back so that the level of the remaining polysilicon layer 7a will preferably be equal to or higher than that of the semiconductor substrate 1 (see Fig. 20(a)).
  • the surface of the SPG is thermally oxidized at 600-1100°C (e.g., 800°C) and a HDP oxide film (insulating film) 15 is deposited.
  • the oxide film on the polysilicon layer 5a is then removed by CMP or etch back.
  • the nitride film 11 functions as an etch stopper.
  • the removal of the oxide film may be performed by wet etch in place of CMP and etch back (see Fig. 20(b)).
  • the nitride film 11 is removed with hot phosphoric acid or by chemical dry etching and then the oxide film 10 on the polysilicon layer 5a is removed by light dipping into a HF solution.
  • the edges of the remaining insulating film 15 is tapered (see Fig. 21(a)). The thus tapered shape facilitates the fabrication of the control gate and the floating gate in a later step.
  • a polysilicon layer 5b of 10-200 nm thick (e.g., 50 nm) is deposited and patterned using a resist mask 16 (see Fig. 21(b)). This step is performed to increase an overlapping area between the floating gate and the control gate. As a result, the gate capacitance coupling ratio increases and voltage consumption is lowered.
  • This embodiment employs the polysilicon layer 5b for the above reason, but it may be omitted.
  • Embodiment 1 The method of writing and reading as employed in Embodiment 1 is also applicable to the nonvolatile semiconductor memory according to Embodiment 8.
  • data rewriting is performed by making use of the FN tunnel current or the CHE so that a highly reliable nonvolatile semiconductor memory capable of high-speed data writing is provided.
  • the memory cell area of 4F 2 which is the actual minimum value, is realized by burying the SPG transistors in the trenches in a device of virtual grounding structure utilizing the SPG cells.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
EP01301827A 2000-03-30 2001-02-28 Mémoire semi-conductrice non-volatile et son procédé de fabrication Withdrawn EP1139426A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000094339 2000-03-30
JP2000094339A JP4117998B2 (ja) 2000-03-30 2000-03-30 不揮発性半導体記憶装置、その読み出し、書き込み方法及び消去方法、その製造方法

Publications (2)

Publication Number Publication Date
EP1139426A2 true EP1139426A2 (fr) 2001-10-04
EP1139426A3 EP1139426A3 (fr) 2001-12-05

Family

ID=18609403

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01301827A Withdrawn EP1139426A3 (fr) 2000-03-30 2001-02-28 Mémoire semi-conductrice non-volatile et son procédé de fabrication

Country Status (5)

Country Link
US (1) US6493264B2 (fr)
EP (1) EP1139426A3 (fr)
JP (1) JP4117998B2 (fr)
KR (1) KR100399380B1 (fr)
TW (1) TW483126B (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG114617A1 (en) * 2002-06-14 2005-09-28 Infineon Technologies Flash Gm Integrated memory circuit and method of forming an integrated memory circuit

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100364803B1 (ko) * 2000-11-15 2002-12-16 주식회사 하이닉스반도체 비휘발성 메모리 제조 방법
JP4027656B2 (ja) * 2001-12-10 2007-12-26 シャープ株式会社 不揮発性半導体記憶装置及びその動作方法
US7064978B2 (en) * 2002-07-05 2006-06-20 Aplus Flash Technology, Inc. Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
US6862223B1 (en) * 2002-07-05 2005-03-01 Aplus Flash Technology, Inc. Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
JP3851914B2 (ja) 2003-07-09 2006-11-29 株式会社東芝 不揮発性半導体記憶装置
US6972230B1 (en) 2004-06-10 2005-12-06 Macronix International Co., Ltd. Method for fabricating a floating gate memory device
US8138540B2 (en) * 2005-10-24 2012-03-20 Macronix International Co., Ltd. Trench type non-volatile memory having three storage locations in one memory cell
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
JP6718248B2 (ja) * 2016-02-17 2020-07-08 ルネサスエレクトロニクス株式会社 半導体装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5495441A (en) * 1994-05-18 1996-02-27 United Microelectronics Corporation Split-gate flash memory cell
US5880499A (en) * 1994-11-11 1999-03-09 Nec Corporation Memory cell of a nonvolatile semiconductor device
US6037221A (en) * 1996-08-06 2000-03-14 Lg Semicon Co., Ltd. Device and fabricating method of non-volatile memory

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2862434B2 (ja) 1991-06-07 1999-03-03 シャープ株式会社 不揮発性メモリ
US5712180A (en) * 1992-01-14 1998-01-27 Sundisk Corporation EEPROM with split gate source side injection
EP0552531B1 (fr) * 1992-01-22 2000-08-16 Macronix International Co., Ltd. Cellule de mémoire non-volatile et architecture en matrice
US5225362A (en) * 1992-06-01 1993-07-06 National Semiconductor Corporation Method of manufacturing a full feature high density EEPROM cell with poly tunnel spacer
US5422504A (en) 1994-05-02 1995-06-06 Motorola Inc. EEPROM memory device having a sidewall spacer floating gate electrode and process
US5641989A (en) 1994-06-03 1997-06-24 Nippon Steel Corporation Semiconductor device having field-shield isolation structures and a method of making the same
JP4070249B2 (ja) 1994-11-22 2008-04-02 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
KR970013338A (ko) * 1995-08-21 1997-03-29 김광호 불휘발성 메모리 장치 및 그 제조 방법
US5793079A (en) 1996-07-22 1998-08-11 Catalyst Semiconductor, Inc. Single transistor non-volatile electrically alterable semiconductor memory device
KR19980073573A (ko) * 1997-03-17 1998-11-05 윤종용 커플링 비 및 절연특성이 개선된 불휘발성 반도체 메모리 장치의 제조방법
KR100244278B1 (ko) * 1997-07-09 2000-02-01 김영환 비휘발성 메모리 소자의 제조 방법
JP3264241B2 (ja) 1998-02-10 2002-03-11 日本電気株式会社 半導体装置の製造方法
KR100268905B1 (ko) * 1998-06-29 2000-10-16 김영환 비휘발성 메모리 셀 및 그 제조방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5495441A (en) * 1994-05-18 1996-02-27 United Microelectronics Corporation Split-gate flash memory cell
US5880499A (en) * 1994-11-11 1999-03-09 Nec Corporation Memory cell of a nonvolatile semiconductor device
US6037221A (en) * 1996-08-06 2000-03-14 Lg Semicon Co., Ltd. Device and fabricating method of non-volatile memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG114617A1 (en) * 2002-06-14 2005-09-28 Infineon Technologies Flash Gm Integrated memory circuit and method of forming an integrated memory circuit

Also Published As

Publication number Publication date
KR100399380B1 (ko) 2003-09-26
TW483126B (en) 2002-04-11
US20010036107A1 (en) 2001-11-01
KR20010095188A (ko) 2001-11-03
JP4117998B2 (ja) 2008-07-16
JP2001284555A (ja) 2001-10-12
US6493264B2 (en) 2002-12-10
EP1139426A3 (fr) 2001-12-05

Similar Documents

Publication Publication Date Title
KR100506445B1 (ko) 반도체 장치 및 그 제조 방법
US7253055B2 (en) Pillar cell flash memory technology
US5847996A (en) Eeprom with split gate source side injection
US7256448B2 (en) Split gate type nonvolatile semiconductor memory device, and method of fabricating the same
US6903408B2 (en) Flash memory cell with high programming efficiency by coupling from floating gate to sidewall
KR100354800B1 (ko) 불휘발성 반도체 기억 장치 및 그 제조 방법
US6838343B2 (en) Flash memory with self-aligned split gate and methods for fabricating and for operating the same
JP2008130676A (ja) 不揮発性半導体記憶装置
US6765261B2 (en) Semiconductor device comprising a non-volatile memory
EP4222744B1 (fr) Cellules de mémoire non volatile à grille divisée avec grilles d'effacement disposées sur des grilles de ligne de mots, et leur procédé de fabrication
US20050190605A1 (en) Semiconductor memory and method of manufacturing the same
US6493264B2 (en) Nonvolatile semiconductor memory, method of reading from and writing to the same and method of manufacturing the same
US7187029B2 (en) Nonvolatile semiconductor memory device with floating gate and two control gates
US7439133B2 (en) Memory structure and method of manufacturing a memory array
US6936883B2 (en) Bi-directional read/program non-volatile floating gate memory cell and array thereof, and method of formation
JP4461042B2 (ja) 不揮発性メモリの製造方法
JP2007142468A (ja) 半導体装置
US6392927B2 (en) Cell array, operating method of the same and manufacturing method of the same
EP1069620A1 (fr) Réseau de cellules de mémoire flash

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

Kind code of ref document: A2

Designated state(s): DE FR GB IT

AX Request for extension of the european patent

Free format text: AL;LT;LV;MK;RO;SI

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

AX Request for extension of the european patent

Free format text: AL;LT;LV;MK;RO;SI

17P Request for examination filed

Effective date: 20020423

AKX Designation fees paid

Free format text: DE FR GB IT

17Q First examination report despatched

Effective date: 20070109

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20090526