Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
  • H01L21/048—Making electrodes
  • H01L21/0485—Ohmic electrodes

Definitions

• the present invention relates to ohmic contacts to semiconductor materials.
• the invention relates to methods of forming ohmic contacts to devices that include a plurality of semiconductor materials.
• circuits are made from the sequential connection of semiconductor devices.
• semiconductor devices are operated by, and are used to control, the flow of electric current within specific circuits to accomplish particular tasks.
• appropriate contacts must be made to the semiconductor devices. Because of their high conductivity and other chemical properties, the most useful and convenient materials for making contacts to such devices are metals.
• Metal contacts between semiconductor devices and circuits should interfere either minimally or preferably not at all with the operation of the device or the circuit. Furthermore, the metal contact must be physically and chemically compatible with the semiconductor material to which it is made or attached. The types of contact that exhibit these desired characteristics are known as "ohmic contacts.”
• An ohmic contact is usually defined as a metal-semiconductor contact that has a negligible contact resistance relative to the bulk or spreading resistance of the semiconductor, Sze, Physics of Semiconductor Devices, Second Edition, 1981, page 304.
• an appropriate ohmic contact will not significantly change the performance of the device to which it is attached, and it can supply any required current with a voltage drop that is appropriately small compared with the drop across the active region of the device.
• Ohmic contacts and methods of producing ohmic contacts are known in the art.
• U.S. Patents 5,409,859 and 5,323,022 to Glass et al. (“Glass patents"), the entire contents of which are incorporated herein by reference, discuss an ohmic contact structure formed of platinum and p-type silicon carbide and a method of making the ohmic structures.
• Glass patents the entire contents of which are incorporated herein by reference
• ohmic contacts and methods of making them are known, the known methods for producing ohmic contacts, and especially those produced using a silicon carbide substrate, are difficult even when properly conducted.
• the problems associated with obtaining ohmic contacts are myriad and cumulative. Limited electrical conductivity of the semiconductor due to low hole or electron concentrations may hinder or even prevent the formation of an ohmic contact.
• an ohmic contact between a semiconductor and a metal requires the correct alloying of the semiconductor and the contact metal at their interface.
• Selectively increasing the hole/electron concentration at the semiconductor surface where the ohmic contact metal is deposited is known as an effective means for enhancing the contact process to achieve an ohmic contact.
• This process is typically achieved through ion implantation, which is well recognized as a selective doping technique in silicon and silicon carbide technologies.
• ion implantation is usually performed at elevated temperatures (typically >600 °C) in order to minimize damage to the silicon carbide crystal lattice. "Activating" the implanted atoms to achieve the desired high carrier concentrations often requires anneal temperatures in excess of 1600 °C, often in a silicon over pressure.
• the equipment required for this ion implantation technique is specialized and expensive.
• the contact metal is deposited on the implanted substrate surface and annealed at temperatures in excess of 900 °C. This method of forming contacts on semiconductor devices that incorporate gallium nitride or indium gallium nitride is not feasible because these compounds disassociate at elevated temperatures.
• MOSFETS metal-oxide-semiconductor field-effect transistors
• MOSFETS metal-oxide-semiconductor field-effect transistors
• oxide layers e.g. silicon dioxide
• ion implantation techniques and implant or contact metal annealing processes place high stress on oxide layers, which can damage oxide layers, the semiconductor-oxide interface and the device itself.
• forming the ohmic contact prior to creating the oxide layer is not practical because the oxidizing environment utilized to form the oxide layers has adverse effects on the ohmic contact.
• It is an object of the invention is to provide a semiconductor device that incorporates an ohmic contact.
• the invention meets these objects with a method for forming a metal- semiconductor ohmic contact for a semiconductor device.
• the method comprises implanting a selected dopant material into a surface of a semiconductor substrate having an initial conductivity type.
• the implanted dopant provides the same conductivity type as the semiconductor substrate.
• the dopant implantation is followed by annealing the implanted semiconductor substrate a first time at a temperature and for a time sufficient to activate the implanted dopant atoms and increase the effective carrier concentrations.
• Depositing a metal on the implanted surface of the semiconductor material follows the first anneal. Thereafter, an annealing of the metal and the implanted semiconductor material occurs.
• This second anneal is at a temperature below which significant degradation of any epitaxial layers placed on the substrate would occur, but high enough to form an ohmic contact between the implanted semiconductor material and the deposited metal.
• the invention also meets these objects with a semiconductor device comprising a semiconductor substrate having a first surface and a second surface and a first conductivity type.
• the device also comprises at least one epitaxial layer that is grown or placed upon the first surface of the semiconductor substrate.
• the semiconductor substrate is further defined as having a zone of increased carrier concentration in the substrate extending from the second surface (the surface opposite the epitaxial layer) toward the first surface.
• the device further comprises a layer of metal deposited on the second surface of the substrate to form an ohmic contact at the interface of the metal and the zone of increased carrier concentration.
• FIG. 1 is a schematic cross-sectional diagram of a semiconductor device according to the present invention.
• FIG. 2 is a schematic cross-sectional diagram of a dopant implantation as utilized in the method according to the invention.
• the present invention is a semiconductor device incorporating an ohmic contact and a method of forming the ohmic contact.
• SiC n-type or p-type silicon carbide
• the following description of the invention and examples will be directed toward an embodiment of the invention utilizing SiC.
• the invention may be easily adapted for use with other semiconductor materials such as silicon, gallium nitride, aluminum gallium nitride, and indium gallium nitride.
• aluminum gallium nitride and indium gallium nitride include compounds where the mole percents of aluminum and gallium or indium and gallium equal 1.
• the invention is a semiconductor device comprising a semiconductor substrate having an initial concentration of dopant imparting an initial conductivity type.
• the semiconductor substrate may be either n-type or p-type.
• the device also comprises at least one epitaxial layer situated adjacent one surface of the semiconductor substrate.
• the claimed semiconductor device is further characterized in that the semiconductor substrate is defined by a zone of increased carrier concentration extending from the surface of the substrate opposite the epitaxial layers toward the surface adjacent the epitaxial layers.
• a layer of metal is deposited on the substrate at the zone of increased carrier concentration to form an ohmic contact at the interface of the metal and the substrate.
• the device 10 comprises a semiconductor substrate 12, which for purposes of explanation is considered to be SiC. It should be understood, however, that other semiconductor materials, such as silicon, may be used as a substrate in the practice of the invention.
• the SiC substrate 12 may be either p-type or n-type.
• the semiconductor device may be a light emitting diode ("LED") having sequential expitaxial layers 14a, 14b, and 14c of p-type and n-type semiconductor materials.
• the invention is a vertical semiconductor device such as a LED, metal-oxide-semiconductor field-effect transistor
• MOSFET metal-oxide-semiconductor
• lasers or Schottky rectifiers that are comprised of several epitaxial layers situated adjacent a semiconductor substrate.
• the device according to the invention is particularly suited for vertical semiconductor devices that comprise materials having low melting or low disassociation temperatures. Such materials would include gallium nitride, indium gallium nitride and aluminum gallium nitride.
• the claimed device is further characterized as having a zone of increased carrier concentration 16 on the backside of the semiconductor substrate.
• the semiconductor substrate in this case SiC, has a carrier concentration near the surface of the substrate opposite the epitaxial layers that is higher than the carrier concentration exhibited in the remainder of the substrate.
• the line that serves as the boundary to the zone of increased carrier concentration 16 is dotted to represent the fact that there is no sharp boundary at which the carrier concentration when the substrate 12 suddenly changes.
• the carrier concentration decreases as the distance from the backside surface of the substrate increases until the carrier concentration equals the initial carrier concentration.
• the zone of increased carrier concentration is formed by a room temperature ion implantation technique using dopants commonly associated with p-type and n-type semiconductor materials.
• a preferred embodiment of the claimed device comprises a n-type SiC substrate doped with nitrogen.
• n-type SiC formed of other n-type dopants along with the various types of p-type SiC also may be used in accordance with the invention.
• the SiC substrate 12 is preferably slightly to highly doped and possess an initial carrier concentration between about 1x1015 and about 1x1019 cm-3.
• the terms "slightly” and “highly” are imprecise and are purposely used to show that the initial carrier concentration may vary considerably. Although the initial carrier concentration may vary considerably, testing has shown that substrates that are initially moderate to highly doped provide the best results.
• a selected dopant material e.g.
• a zone 16 is created that contains a higher carrier concentration than the remainder of the substrate 12.
• the ion implantation is conducted at a level that creates a zone of increased carrier concentration 16 on the backside of the substrate that exhibits a carrier concentration between about lxl 0 18 and about lxl 0 20 cm '3 and that is always higher than the initial carrier concentration.
• the preferred n-type dopants for use in forming the zone of increased carrier concentration 16 are nitrogen, arsenic and phosphorous.
• Preferred p-type dopants for use in forming the zone of increased carrier concentration 16 are aluminum, boron and gallium.
• the zone of increased carrier concentration 16 allows for the creation of a metal contact that exhibits ohmic properties.
• a selected contact metal 18 having a melting point, vapor pressure and physical and chemical properties suitable for use with the overall semiconductor device is deposited at the surface of the SiC substrate at the zone of increased carrier concentration 16 to form an interface 20 between the metal and the substrate.
• Preferred metals include nickel, palladium, platinum, aluminum and titanium with nickel being most preferred.
• the device, including the metal and the substrate is then annealed at a temperature low enough to avoid damage to the device and specifically any epitaxial layer, but high enough to form an ohmic contact at the interface of the metal and substrate.
• the invention comprises the method of forming the ohmic contact utilized in the previously described semiconductor device.
• the invention is a method for forming a metal- semiconductor contact for a semiconductor device.
• the method comprises implanting a selected dopant material into a semiconductor substrate having a first conductivity type and wherein the implanted dopant provides the same conductivity type as the substrate.
• the semiconductor substrate is a SiC substrate and that the dopant material is deposited into a surface of the SiC substrate.
• An annealing step follows the implanting of the selected dopant material.
• the implanted SiC substrate is annealed at a temperature and for a time sufficient to activate the implanted dopant atoms to effectively increase the carrier concentration of the implanted dopant atoms in the SiC substrate.
• a contact metal is then deposited on the implanted surface of the SiC substrate.
• the deposited contact metal and the implanted surface of the SiC substrate are then annealed.
• This second annealing is at a temperature below that at which any expitaxial layer placed on the substrate would experience significant degradation but high enough to form an ohmic contact between the implanted SiC and the deposited metal.
• the semiconductor substrate may comprise a n- type or p-type substrate that may possess a slight, moderate, or high initial dopant concentration.
• the SiC substrate may possess an initial dopant concentration from about lxlO 15 (slightly doped) to lxlO 19 cm “3 (highly doped).
• the terms "slight,” “moderate,” and “high” are imprecise and are used to indicate that the initial concentration of dopant in the substrate material may vary. Testing has shown that moderate to highly doped substrates achieve the best results with the invention.
• the semiconductor substrate is then implanted with a selected dopant material and annealed.
• the dopant implantation occurs at room temperature and the subsequent annealing occurs at a temperature between about 800°C and about 1300°C.
• Dopants usually associated with the conductivity type of the substrate may be used as the dopant for the implantation step.
• nitrogen may serve as the implanted dopant.
• p-type SiC initially doped with aluminum is the substrate, aluminum may serve as the implanted dopant.
• Other possible n-type dopants are arsenic and phosphorous. Boron and gallium may serve as alternative p-type dopants.
• the implanting of the dopant material may be accomplished at high temperatures.
• high temperature implantation is typically preferred in the SiC context in order to reduce damage to the SiC lattice structure.
• high temperature ion implantation places constraints on the commercial use of the invention. Ion implanting equipment with the capability of heating the SiC substrate during implantation are atypical, expensive and intended for research and development rather than low cost, high volume applications.
• SiC substrates are heated to high temperatures, they must be heated and cooled at a rate that will not produce fractures thereby slowing down the production process.
• room temperature implantation is the preferred implantation method for use in the invention. It has been discovered that room temperature implanting of dopant followed by an annealing step in a simple vented furnace capable of reaching 1300°C and holding 100 or more substrate wafers achieves satisfactory results and greatly increases throughput.
• FIG. 2 is a schematic representation of the implantation process according to the invention.
• a n-type SiC substrate 22 having an initial dopant concentration of approximately lxl 0 18 cm “3 is implanted with atomic or diatomic nitrogen 24 at energies of 10 to 60 keN with doses of lxlO 13 cm "2 or more. In some instances more than one implant energy may be used to create a more graduated carrier concentration distribution.
• the implantation process produces a zone 26 near the implanted surface of the SiC substrate approximately 1000 angstroms in depth having a total chemical dopant concentration of approximately lxlO 19 to lxlO 20 cm "3 with the concentration of the implanted dopant decreasing as the distance from the implanted surface increases.
• the dopant concentration outside of the zone of increased dopant concentration 26 remains substantially the same as the initial dopant concentration.
• the boundary of the zone of increased carrier concentration 26 is represented as a dotted line to indicate that the change in carrier concentration between the zone 26 and the remainder of the substrate is not distinct but gradual.
• the implanted substrate As mentioned previously, it is necessary to anneal the implanted substrate. The annealing is required because some of the implanted dopant ions are not "active" immediately after implantation.
• the term "active" is used to describe the availability of the implanted ions to contribute to the overall carrier concentration of the implanted substrate.
• the crystal lattice of the SiC substrate is essentially bombarded by dopant ions. These ions crash into the crystal lattice where they are retained. This bombardment does not result in a perfect insertion of dopant ions into the existing crystal lattice.
• the initial positioning of many of the dopant ions may prevent the ions from being "active" participants in the crystal lattice, which itself may be damaged by the bombardment.
• Annealing (i.e., heating) the implanted SiC substrate provides a mechanism by which the implanted ions and the crystal lattice of the substrate may rearrange in a more orderly fashion and recover from the damage incurred during the dopant implantation.
• the implanting process may be thought of as follows. If 100 nitrogen ions are implanted in an n-type SiC substrate having an initial concentration of x nitrogen atoms, immediately after implantation the substrate may only exhibit the characteristics associated with a substrate having "x+10" nitrogen ions. However, if the substrate is then annealed and the implanted ions are allowed to settle into position in the crystal lattice, the substrate may exhibit the characteristics associated with a substrate having "x+90" nitrogen ions. Thus, the annealing step has "activated” approximately 80 of the implanted nitrogen ions. Testing shows that annealing the room temperature implanted SiC substrate at temperatures between approximately 1000°C and 1300°C for about two hours or less will yield satisfactory results. The temperature and time may be easily adjusted to achieve a more complete activation of the implanted dose.
• the semiconductor device comprising the above-discussed implanted substrate possesses at least one epitaxial layer.
• the epitaxial layer may be grown by any means known to those skilled in the art.
• the epitaxial layer is deposited prior to the dopant implantation of the substrate.
• the desired epitaxial layer or subsequently fabricated device may be made of or comprised of a material (e.g., gallium nitride or a silicon oxide) incapable of withstanding the high temperature anneal of the implanted substrate.
• the epitaxial layer may be formed after the dopant implantation.
• the metal selected to form the ohmic contact is applied to the surface of the substrate at the zone of increased carrier concentration.
• the metal may be just about any metal typically used in forming electrical contacts that possesses an appropriately high melting point and vapor pressure and does not interact adversely with the substrate material.
• Preferred metals include nickel, palladium, platinum, titanium and aluminum with nickel being most preferred.
• the contact metal is deposited on the substrate surface to form a layer 300 angstroms thick or more. The deposition is followed by a second anneal. This anneal, however, is not a high temperature long duration anneal.
• This anneal preferably occurs at a temperature less than about 1000 ° C and most preferably less than about 800°C for 20 minutes or less and most preferably for 5 minutes or less. These temperatures and time periods are sufficiently low to avoid damaging any epitaxial layers that are on the substrate.
• the annealing of the contact metal to the semiconductor substrate results in an ohmic contact at the interface of the metal and substrate.
• a metal semiconductor according to the invention was created using a n-type SiC substrate which was first implanted at an energy of 50 keV with a 3xl0 14 cm "2 dose of atomic nitrogen followed a second implantation at 25 keN at 5xl0 14 cm “2 .
• the implantation was followed by an activation anneal at 1300 °C for 60 to 90 minutes in an argon ambient in a furnace.
• the contact metal, nickel was deposited on the implanted surface at a thickness of 2500 Angstroms.
• the contact anneal was then performed at 800 °C for 2 minutes in argon.
• the resulting ohmic contact exhibited satisfactory ohmic properties.
• the invention offers a substantial advantage for vertical devices such as photodetectors, light emitting diodes (LEDs), lasers, power devices such as metal- oxide-semiconductor field-effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs) , pn junctions and Schottky rectifiers, and microwave devices such as SITs (static induction transistors).
• LEDs and lasers epitaxially grown gallium nitride and indium gallium nitride layers are not to be subjected to anneals at temperatures that would severely damage the layers.
• time at elevated temperatures becomes more critical as the indium composition of the alloy increases.
• Reducing the backside contact anneal temperature also reduces the potential for cracking in or disassociation of indium or gallium components in the strained heteroepitaxial films grown on SiC substrates.
• oxides have an integral role in the device performance and a lower anneal temperature is an advantage.
• the backside metal contact can not be subjected to the oxidizing ambient that is required to grow the SiC-silicon dioxide interface, therefore, the backside ohmic contact must be deposited and annealed after the silicon dioxide is grown (reoxidized or regrown).

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• 1999
  • 1999-09-16 EP EP99951484A patent/EP1125320A1/en not_active Ceased
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