CA2343416A1 - Low temperature formation of backside ohmic contacts for vertical devices - Google Patents

Low temperature formation of backside ohmic contacts for vertical devices Download PDF

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Publication number
CA2343416A1
CA2343416A1 CA002343416A CA2343416A CA2343416A1 CA 2343416 A1 CA2343416 A1 CA 2343416A1 CA 002343416 A CA002343416 A CA 002343416A CA 2343416 A CA2343416 A CA 2343416A CA 2343416 A1 CA2343416 A1 CA 2343416A1
Authority
CA
Canada
Prior art keywords
silicon carbide
substrate
semiconductor device
implanted
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002343416A
Other languages
English (en)
French (fr)
Inventor
David B. Slater, Jr.
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wolfspeed Inc
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2343416A1 publication Critical patent/CA2343416A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/048Making electrodes
    • H01L21/0485Ohmic electrodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Lasers (AREA)
CA002343416A 1998-09-16 1999-09-16 Low temperature formation of backside ohmic contacts for vertical devices Abandoned CA2343416A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10054698P 1998-09-16 1998-09-16
US60/100,546 1998-09-16
PCT/US1999/021475 WO2000016382A1 (en) 1998-09-16 1999-09-16 Low temperature formation of backside ohmic contacts for vertical devices

Publications (1)

Publication Number Publication Date
CA2343416A1 true CA2343416A1 (en) 2000-03-23

Family

ID=22280313

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002343416A Abandoned CA2343416A1 (en) 1998-09-16 1999-09-16 Low temperature formation of backside ohmic contacts for vertical devices

Country Status (9)

Country Link
EP (1) EP1125320A1 (enExample)
JP (2) JP4785249B2 (enExample)
KR (1) KR100694681B1 (enExample)
CN (1) CN1178277C (enExample)
AU (1) AU6391699A (enExample)
CA (1) CA2343416A1 (enExample)
MX (1) MXPA01002751A (enExample)
TW (1) TW449932B (enExample)
WO (1) WO2000016382A1 (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6803243B2 (en) * 2001-03-15 2004-10-12 Cree, Inc. Low temperature formation of backside ohmic contacts for vertical devices
US6884644B1 (en) 1998-09-16 2005-04-26 Cree, Inc. Low temperature formation of backside ohmic contacts for vertical devices
US6909119B2 (en) 2001-03-15 2005-06-21 Cree, Inc. Low temperature formation of backside ohmic contacts for vertical devices
US7138291B2 (en) * 2003-01-30 2006-11-21 Cree, Inc. Methods of treating a silicon carbide substrate for improved epitaxial deposition and resulting structures and devices
US7262434B2 (en) * 2002-03-28 2007-08-28 Rohm Co., Ltd. Semiconductor device with a silicon carbide substrate and ohmic metal layer
US7473929B2 (en) 2003-07-02 2009-01-06 Panasonic Corporation Semiconductor device and method for fabricating the same
JP2006086361A (ja) * 2004-09-16 2006-03-30 Stanley Electric Co Ltd 半導体発光素子及びその製造方法
EP1933386B1 (en) * 2005-09-14 2012-11-07 Central Research Institute of Electric Power Industry Process for producing silicon carbide semiconductor device
WO2009157299A1 (ja) * 2008-06-26 2009-12-30 サンケン電気株式会社 半導体装置及びその製造方法
KR101220407B1 (ko) 2010-12-14 2013-01-21 (재)한국나노기술원 반도체 발광 소자
JP5811829B2 (ja) 2011-12-22 2015-11-11 住友電気工業株式会社 半導体装置の製造方法
JP5742712B2 (ja) 2011-12-29 2015-07-01 住友電気工業株式会社 炭化珪素半導体装置の製造方法
JP6253133B2 (ja) * 2012-04-27 2017-12-27 富士電機株式会社 炭化珪素半導体装置の製造方法
US9496366B2 (en) 2013-10-08 2016-11-15 Shindengen Electric Manufacturing Co., Ltd. Method for manufacturing silicon carbide (SiC) semiconductor device by introducing nitrogen concentration of 5X1019 cm-3 or more at a boundary surface between thermal oxide film and the SiC substrate and then removing the thermal oxide film
JP7135443B2 (ja) * 2018-05-29 2022-09-13 富士電機株式会社 炭化ケイ素半導体装置及びその製造方法
CN115148601A (zh) * 2021-03-30 2022-10-04 无锡华润华晶微电子有限公司 半导体结构及其制备方法
EP4071786B1 (en) * 2021-04-06 2025-11-05 Hitachi Energy Ltd Method for forming an ohmic contact on a wide-bandgap semiconductor device and wide-bandgap semiconductor device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5323022A (en) * 1992-09-10 1994-06-21 North Carolina State University Platinum ohmic contact to p-type silicon carbide
JP3303530B2 (ja) * 1994-06-23 2002-07-22 富士電機株式会社 炭化けい素半導体素子の製造方法
JPH08139053A (ja) * 1994-11-04 1996-05-31 New Japan Radio Co Ltd SiCへの電極の形成方法
JP3333896B2 (ja) * 1995-09-13 2002-10-15 富士電機株式会社 炭化珪素半導体装置の製造方法
WO1998037584A1 (en) * 1997-02-20 1998-08-27 The Board Of Trustees Of The University Of Illinois Solid state power-control device using group iii nitrides

Also Published As

Publication number Publication date
KR20010079759A (ko) 2001-08-22
WO2000016382A1 (en) 2000-03-23
AU6391699A (en) 2000-04-03
CN1178277C (zh) 2004-12-01
JP4785249B2 (ja) 2011-10-05
MXPA01002751A (es) 2002-04-08
EP1125320A1 (en) 2001-08-22
KR100694681B1 (ko) 2007-03-13
TW449932B (en) 2001-08-11
JP2011151428A (ja) 2011-08-04
CN1323446A (zh) 2001-11-21
JP2002525849A (ja) 2002-08-13

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Legal Events

Date Code Title Description
EEER Examination request
FZDE Discontinued