TW449932B - Low temperature formation of backside ohmic contacts for vertical devices - Google Patents

Abstract

The invention comprises a method for forming a metal-semiconductor ohmic contact for use in a semiconductor device having a plurality of epitaxial layers wherein the ohmic contact is preferably formed after deposition of the epitaxial layers. The invention also comprises a semiconductor device comprising a plurality of epitaxial layers and an ohmic contact.

Description

449932 V. Description of the invention (1) Scope of the invention The present invention relates to ohmic contact of semiconductor materials. In particular, the present invention relates to a method of forming an ohmic contact including a plurality of semiconductor material devices. BACKGROUND OF THE INVENTION In the case of microelectronics, a circuit is a continuous connection from a semiconductor device. Generally, a semiconductor device is operated by a current in a specific circuit, and is used to control the current in the specific circuit to achieve a specific task. In order to connect a semiconductor device in a circuit, the semiconductor device must make appropriate contacts. Due to its high electrical conductivity and other chemical properties, the most useful and convenient material for making contact with these devices is metal. Metal contact between a semiconductor device and a circuit should be minimized or preferably not affected by the operation of the device or circuit. Furthermore, the metal contact must be physically or chemically compatible with the semiconductor material it is manufactured or attached to. The type of contact that displays the desired characteristics is called "ohmic contact." In 1981, Sze, Physics of Semiconductor Devices, Second Edition, p. 304, ohmic contact is usually defined as a metal-semiconductor contact, which has negligible contact resistance relative to the bulk or extended resistance of the semiconductor. The document further describes that a proper ohmic contact will not significantly change the performance of the device to which it is connected, and will provide any required current, the voltage drop of which is compared to the voltage drop across the active area of the device, For an appropriate small pressure drop. Ohmic contact and methods of generating ohmic contact are well known to industry experts. For example, U.S. Patent Nos. 5,4 0 9, 8 5 9 and 5, 3 2 3, 0 2 2 are represented by G 1 as s, etc.

5. Explanation of the Invention (2) Author ("G 1 ass Patent"), the entire contents of which are attached for reference, and discuss the ohmic contact structure formed by platinum and p-type silicon carbide , And a method of generating the ohmic structure. Although ohmic and ohmic contact methods are well known, the known methods of generating ohmic contacts, especially those using silicon carbide substrates, are difficult to operate correctly. 〇 There are many types of problems related to ohmic contact, and they gradually build up. Because the hole or electron concentration is too low, the conductivity of the semiconductor is limited, which may affect or even prevent the formation of ohmic contacts. Similarly, poor hole or electron mobility in semiconductors may affect or even prevent the formation of ohmic contacts. As discussed in the G 1 as s patent, differences in the functional functions of the contact metal and semiconductor may raise the barrier, causing a contact to exhibit a rectified (non-ohmic) current relative to the applied voltage. Even between two identical semiconductors that are in close contact and have very different electron-to-hole concentrations, there will be a barrier (internal potential), which results in rectification rather than ohmic contact. In the G 1 as s patent, these problems will occur if an apparent p-type doped S i C layer is inserted between the p-type SiC substrate and the contact metal. More difficult problems are encountered when forming ohmic contacts for next-generation gallium and indium-based semiconductor devices. The formation of an ohmic contact between a semiconductor and a metal requires the correct alloy of the semiconductor and the contact metal. Selectively increasing the hole electron concentration on the semiconductor surface on which the ohmic contact metal is deposited is considered an effective method to enhance contact processing to achieve ohmic contact. This processing method is usually achieved by ion implantation, which is well-known as a selective doping technique in Shixi and post-fossil techniques. However, in the case of silicon carbide, ion implantation is usually performed when the temperature rises (usually> 60 ° C).

449 9 3 2 V. Description of the invention (3) In order to minimize the damage to the silicon carbide lattice. "Activating" the implanted atoms to achieve the desired high carrier density requires an annealing temperature in excess of 1,600 ° C, which is usually within silicon under pressure. The equipment required for this ion implantation technique is quite professional and expensive. After high-temperature ion implantation and subsequent annealing, the contact metal is deposited on the surface of the implanted substrate and annealed at a temperature above 900 ° C. This method of forming contacts on a semiconductor device incorporating gallium nitrate or indium gallium nitride is not feasible because these compounds decompose at elevated temperatures. The solution to this problem is theoretically to form an ohmic contact on the substrate before completing the fragile stupid layer (such as a gallium bowl layer) that the semiconductor device must generate. However, this method is not desirable, because unnecessary pollutants ′ contact metal ^ are brought into the stupid crystal growth system. This contaminated gold layer can interfere with lattice growth, doping, reaction rate, or such factors, and affect stupid crystal growth. In addition, impure metals can reduce the optoelectronic properties of the telecrystal layer. Similarly, many semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETS), require a semiconductor oxide layer (such as silicon dioxide). The commercial temperature associated with traditional ion implantation techniques and the annealing process of implanting or contacting metal applies high pressure on the oxide layer, thereby damaging the oxide layer, the semiconductor-oxide interface, and the device itself. In addition, it is not practical to form an ohmic contact before the oxide layer is established because the oxidizing environment used to form the oxide layer has a negative effect on the ohmic contact. Therefore, there is a need for a practical and economical method for forming a semiconductor device for connecting semiconductor devices that do not suffer from the manufacturing problems discussed above.

Page 6 Ϊ i 449 9 3 2 V. Description of the invention (4) Contact with Mu. There is also a need for a semiconductor device that incorporates ohmic contacts but is economical to manufacture. OBJECTS AND SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device incorporating an ohmic contact. Another object is to provide a device including silicon carbide and an ohmic contact. The semiconductor device of the present invention touches the semiconductor device of the present invention, and the ohmic contact of the invention ohmic access has the semiconductor implanted semi-doped dopant on the semiconductor implanted semiconductor substrate before implanting the semiconductor Another device of the ohm, another semiconducting method that meets the purpose of the conductive substrate, a conductor deatomic, the material of the material, any semiconductor, also conforms to a conductive type, and contains at least one stupid crystal. Combined. After the type of fire is raised and the implanted vermicular crystal material is added to the conductive layer, it is necessary to make the system. A semi-donor implant in the shape of a hair is implanted with a surface fire. It is very economical to provide a semiconductor manufacturing method that combines ohmic contact with a package of substrate. Provides a method for forming a sinking second growth factor with a half-growth that combines the same doping effect as an open-conductor. It is used to include the substrate conductive agent. The first conductor or semiconductor is screened. The surface type lasts for a period of time. The temperature of the fire. First. At the next temperature, a dopant is formed between the device and the metal dopant, and the dopant is implanted prior to the second, and the low temperature ohmic is the second. The conductor is annealed with gold to make it contact with the surface. The substrate, the semiconducting material, and the temperature are planted. It belongs to the surface and the surface of the surface.

Page 7 449 9 3 2 V. Description of the invention (5) One surface. The semiconductor substrate is further defined as having a region of increasing carrier concentration in the substrate extending from the second surface (the surface opposite the epitaxial layer) to the first surface. The device further includes a metal layer deposited on the second surface of the substrate to form an ohmic contact between the interface of the metal and the carrier concentration region. The above and other objects, advantages, and characteristics of the present invention and methods for achieving these objects, advantages, and characteristics will become apparent after considering the following detailed description of the present invention related to the accompanying drawings, which are used to illustrate exemplary Specific embodiments, wherein: Brief description of the drawings FIG. 1 is a schematic cross-sectional view of a semiconductor device according to the present invention. FIG. 2 is a schematic cross-sectional view of a dopant implantation according to the method of the present invention. Detailed description of the invention 3 The present invention is a semiconductor device incorporating an ohmic contact and a method for forming an ohmic contact. Experts who are familiar with wide bandgap semiconductors, such as silicon carbide, and semiconductor devices from this semiconductor, can understand that the present invention is most helpful for semiconductor devices made with n-type or p-type silicon carbide (MSiC ") and ohmic contact. Therefore, for the convenience of explanation, the following descriptions and examples of the present invention will be based on the specific embodiments of the present invention using SiC. However, experts in the industry will easily find that the present invention can also be easily combined with other semiconductor materials, such as silicon, gallium nitrate, aluminum gallium nitride, and copper gallium nitride. ). The gallium nitride and surface gallium nitride used here include compounds that make the molecular ratio of aluminum and gallium or indium and gallium equal

449 9 3 2 5 'Explanation of the invention (6) 1 0' In a broad sense, the present invention is a semiconductor device including a semiconductor substrate. The substrate has an initial concentration of a dopant that provides an initial conductivity type. The semiconductor substrate may be n-type or p-type. The device also includes at least one epitaxial layer adjacent to the surface of the semiconductor substrate. For example, a semiconductor device in the scope of a patent application is further characterized in that the semiconductor substrate is defined by an increased carrier concentration region that extends from the surface of the substrate relative to the epitaxial layer to a surface adjacent to the epitaxial layer. A metal layer is deposited on the substrate of the zone of increased carrier concentration to form an ohmic contact between the metal surface and the substrate. Referring to FIG. 1, a simplified diagram of a semiconductor device 10 according to the present invention β The device 10 includes a semiconductor substrate 12 and will be considered 31 (: for convenience of explanation). However, it should be understood that other semiconductor materials such as silicon, It can also be used as the substrate of the present invention. The SiC substrate 12 can be a p-type or an η-type. Adjacent to the Si C substrate 12 are necessary additional components 14 for completing a semiconductor device. As shown, the semiconductor device may be a light emitting diode (LED) with continuous epitaxial layers i4a, 14b, and 14c of p-type and n-type semiconductor materials. In a preferred embodiment, the present invention is vertical Semiconductor devices, such as LEDs, metal oxide semiconductor field effect transistors (MOSFETs), lasers, or Schottky rectifiers, are composed of certain epitaxial layers adjacent to a semiconductor substrate. The device of the present invention will be discussed later Particularly suitable for vertical semiconductor devices containing low melting points or low separation temperatures. Such materials include gallium nitrate, indium gallium nitride, and aluminum gallium nitride.

449932 V. Description of the invention (7) The device in the scope of patent application is further characterized in that there is a region 16 for increasing the carrier concentration on the back side of the semiconductor substrate. In other words, the semiconductor substrate, Si C in this example, has a carrier concentration close to the surface of the substrate relative to the epitaxial layer, which is higher than the carrier concentration of the rest of the substrate. η, as an edge of the region 16 for increasing the carrier concentration, is indicated by a dashed line, which represents that there is no clear boundary for the carrier concentration when the substrate 12 is suddenly changed. The carrier concentration decreases as the distance from the back surface of the substrate increases until the carrier concentration is equal to the initial carrier concentration. As will be discussed below, the region of increasing the carrier concentration is formed by the room temperature ion implantation technology, and usually dopants related to P-type and n-type semiconductor materials are used.

For example, referring to Fig. 1, a preferred embodiment of a patent-applied device includes an n-type SiC substrate doped with nitrogen. It should be understood that n-type S i C formed with other n-type dopants and different kinds of p-type S i C can also be used according to the present invention. SiC substrate 12 is preferably slightly to highly doped and has an initial carrier concentration between about 1x 1015 and about 1x 1019 cnr3. The words "slightly" and "height" are imprecise and are intentionally used here to show that the initial carrier concentration may vary significantly. Although the initial carrier concentration may vary widely, the test results show that the substrate is initially a medium to highly doped substrate with the best results. By ion implantation of the screened dopant material (eg nitrogen) on the surface opposite to the epitaxial layer 1 4, a region 16 is generated which contains a higher area than the rest of the substrate 12 Carrier concentration. Preferably, the ion implantation performed can generate a region 16 for increasing the carrier concentration on the back side of the substrate, so that the carrier concentration is between about lx 1018 and about lx l02a cur3, and can be maintained. Always above the initial carrier concentration.

Page 10 449 9 3 2 V. Description of the invention (8) Familiar with this technique can reduce the difficulty related to the substrate productivity, and let this party use it to form Helin. Although it can be used for the concentration, boron, and gallium in the application, the concentration region 16 can be used in the embodiment, and the force and the physical concentration region of the carrier form the interface 20. nickel. Then the temperature should not be damaged, but it should be touched. Again, although the carrier concentration region is therefore widely known in its conductor device, a person with advanced technology will find that the carrier concentration region as described above is also formed for a long time. However, it is difficult to perform different feed rate difficulties with the required dopants and other difficult methods usually related to the quartz growth method. — The preferred η-type dopant for increasing the carrier concentration region 16 is nitrogen and arsenic. The preferred ρ-type dopant for increasing the carrier concentration region 16 is 0.00. People do not want to be bound by a specific theory, but it turns out that the increase The carrier is sufficient to produce metal contacts with ohmic properties. The screened contact metal 18, which preferably has melting point and vapour pressure characteristics suitable for the entire semiconductor device, is deposited on the surface of the Si C-based substrate with an increase of 16 in order to form a space between the metal and the substrate. Preferred metals include locks, ε, flips, inscriptions, and titanium, and it is preferred that the device including the metal and the substrate be annealed at a temperature that is too high to prevent the device or, specifically, any epitaxial layer from being sufficiently exposed to The formation of an ohmic interface between the metal and the substrate. The applicant does not want to be bound by a particular theory, but it seems useful to generate an increase in receptors as a contact metal. In other embodiments, the invention includes a method for forming the aforementioned semi-ohmic contact. It appears that the present invention is a method for forming a gold contact of a semiconductor device. The method includes implanting a screened doping material, a conductive semiconductor substrate, and the implanted doping

Page 11 5. Description of the invention (9) The agent provides the same conductivity type as the substrate. For the sake of discussion, we will assume that the semiconductor substrate is a Si substrate, and that the doped material is deposited on the surface of the Si substrate. However, it will be easy for experts in the industry to discover that the invention can also be easily combined with other semiconductor materials. An implantation step is performed after the screened doped material is implanted. In this annealing step, the implanted Si C substrate is annealed at a temperature, and is continued for a period of time to activate the implanted dopant atoms, so as to effectively increase the implanted dopant atoms of the Si C substrate. Carrier concentration. Next, a contact metal system is deposited on the implanted surface of the SiC substrate. Next, the implanted surface of the deposited contact metal and SiC substrate is annealed. The temperature of the second annealing should be lower than the temperature at which severe degradation of any epitaxial layer on the substrate can occur, but the temperature should be high enough to form an ohmic contact between the implanted Si C and the deposited metal. In a preferred embodiment, the semiconductor substrate may include an n-type or p-type substrate with a slightly, moderate, or high initial dopant concentration. For example, where n-type Si C is used as the substrate, the initial dopant concentration of the Si C substrate is from about 1 X 1 015 (slightly doped) to 1 X 1 0ig cnr3 (highly doped). The words "slightly," "moderately," and "highly" are not precise and are used to indicate that the initial dopant concentration on the substrate material may change. Test results show that moderate to highly doped substrates give the best results of the present invention. The receiver then implants a semiconductor-selected material on the semiconductor substrate and fires it. It is better to say that the dopant implantation is performed at room temperature, and the subsequent annealing is performed at about 800 ° C to 130 ° C. A doping agent generally related to the conductivity type of the substrate can be used as a dopant during the implantation step. For example, when using an n-type Si C that is initially doped with nitrogen as the substrate, nitrogen can be used as an implant dopant

Page 12 Γ 449 9 3 2 5 'Explanation of the invention α〇) agent. Similarly, when using a p-type Si C doped with Shaw as the substrate, Ming can be used as an implant dopant. Other useful n-type dopants are arsenic and phosphorus. Boron and gallium are other options for p-type dopants. 0 Experts in the industry will easily find that the process of implanting dopants can be performed at high temperatures. In fact, in the case of SiC, it is usually best to implant at high temperatures to reduce damage to the lattice structure. In the case of SiC, high temperature ion implantation may limit the invention to commercial use. The use of ion implantation equipment capable of heating SiC substrates during implantation is rather unusual, expensive, and suitable for research and development rather than low cost, mass production applications. Even when the SiC substrate is heated to a high temperature, the rate of heating and cooling must not cause cracks to slow down the process speed. Therefore, the present invention is more suitable for the method of implantation at room temperature. We have found that satisfactory results can be obtained by implanting dopants at room temperature in a simple ventilated furnace capable of reaching 130 ° C and holding 100 or more substrate wafers after the annealing step. , And the output has increased significantly. It is preferable to perform dopant implantation at room temperature in order to establish a region where the dopant concentration is increased near the implantation surface of the semiconductor substrate. Figure 2 is a simplified diagram of the implantation process according to the present invention. In this example, the n-type SiC substrate 22 having an initial dopant concentration of about 1 X 1018 cnr3 is implanted with an atom or a dose of lx 1013 cm-2 or more with an energy between 10 and 60 keV. Diatomic nitrogen 2 4. In some cases, more than one implantation energy can be used to generate a more progressive carrier desert distribution. This implantation process produces a region 26 on the implantation surface close to the SiC substrate, with a depth of about 1000 angstroms, and an overall chemical concentration of about lx 1019 to lx 102 () cm-3.

Page 13 4 49 9 32 5. Description of the invention (11) The lower the dopant concentration is. The dopant concentration outside the increased dopant concentration region 26 remains substantially the same as the original dopant concentration. Increasing the carrier concentration The dividing line of the region 26 is indicated by a dashed line, indicating that the change in the carrier concentration between the region 26 and the rest of the substrate is not very clear but gradually changes. Experts in the industry should understand that the implantation energy or dose can be easily changed to achieve the desired concentration and thickness. As mentioned earlier, the implanted substrate must be annealed. The annealing step is necessary because the implanted dopant ions do not begin to "action" immediately after implantation. The term "effect" is used to describe the effectiveness of the overall carrier concentration provided by the implant ion to the implant substrate. At the time of implantation, the crystal lattice of the S i C substrate was mainly impacted by the soot and miscellaneous ions. These ions rushed into the lattice they were blocked in. This impact does not make the dopant ions intercalate into the existing lattice. The initial position of many dopant ions may prevent the ions from acting on the crystal lattice, and may itself be damaged by impact. Annealing (that is, heating) the implanted SiC substrate provides a mechanism for a more organized arrangement of the implanted ions and lattice of the substrate, and will restore the damaged part when implanting the dopant . For ease of explanation, only integers will be used, and the implantation process is shown below. If 100 nitrogen ions are implanted into an η-type SiC substrate with an initial concentration of X nitrogen atoms, once the implantation operation is completed, the substrate may only exhibit the characteristics of a "χ + 10" nitrogen ion substrate. However, if the substrate is subsequently annealed, the implanted ions will be localized in the crystal lattice, and the substrate may exhibit the characteristics of "X + 90" nitrogen ions. Therefore, this annealing step "activates (ac t i v a t e)" about 80 implanted nitrogen ions.

Page 14 449932 V. Description of the invention (12) The test shows that at a temperature between about 100 ° C and 13 0 ° C, a Si substrate that is implanted at room temperature will produce about two hours. Satisfactory results. The temperature and time can easily be adjusted to achieve a more complete and active dose. The semiconductor device including the implanted substrate includes at least one epitaxial layer. The epitaxial layer can be formed by methods well known to experts in the industry. In a preferred embodiment of the invention, the epitaxial layer is deposited before the dopant distribution of the substrate. However, the required epitaxial layer or subsequent manufacturing devices may be formed or contained in materials that cannot withstand the high temperature annealing of the implanted substrate (ie, gallium nitrate or silicon oxide). In this example, the epitaxial layer may be formed after implantation of the dopant. After implanting the semiconductor substrate, establishing an appropriate annealing zone for increasing the dopant concentration, and placing any worm crystal layer on the substrate, the metal selected to form the ohmic contact is applied to the surface of the substrate for increasing the carrier concentration region. The metal may be any metal commonly used to make electronic contacts, the metal has an appropriate high melting point and vapor pressure, and does not adversely affect the substrate material. Preferred metals include bells, ie, flips, titanium, and inscriptions, and the best are recorded. Preferably, the contact metal is deposited on the surface of the substrate to form a deposited layer having a thickness of 300 angstroms. After deposition, a second anneal was performed. However, this annealing is not a high temperature and long time annealing. This annealing is preferably performed at a temperature below about 100 ° C, the best case is below 80 ° C, the performance is 20 minutes or less, and the best case is continuous Within 5 minutes. This temperature and duration should be minimized to avoid damaging the epitaxial layer on the substrate. Annealing contact metals on semiconductor substrates will interface between metal and substrate

Page 15 4 49 9 3 2 Five 'invention description (13) ohmic contact. In a more specific embodiment of the present invention, the metal semiconductor according to the present invention can be generated using an n-type SiC substrate, and the energy is 50 keV, and the n-type SiC substrate is first implanted at a dose of 3x 10 "cnr2 nitrogen atom. The material was then replanted at 25 keV, 5x 1 014 cur2. The cloth value was then annealed in a furnace containing argon at 130 ° C for 60 to 90 minutes. Then, the contact metal nickel was deposited on The implant surface thickness is 2500 angstroms. The contact annealing is then performed in argon at 800 ° C for 2 minutes. The resulting ohmic contact has satisfactory ohmic characteristics. Those skilled in the art should recognize that it is also possible to grow in the worm crystal Contact annealing is performed at the same time. The invention is a vertical device like a photodetector, a light emitting diode (LED), a laser, a power supply device like a metal oxide semiconductor field effect transistor (MOSFET), and an insulated gate bipolar transistor. (IGBT), pn junctions and Schottky rectifiers, and microwave devices like SIT (Static Induction Transistor) provide substantial advantages. Take detectors, LEDs, and lasers as examples, epitaxially grown gallium nitrate and indium gallium nitride layers in It is difficult to anneal at a temperature that can seriously damage this layer. Taking indium gallium nitride as an example, when the indium content of the alloy increases, the time at high temperature becomes more important. Lowering the back contact annealing temperature also reduces the growth on the SiC substrate Potential for fracture in the strained heteroepitaxial film, or the separation of indium or gallium. Take power supply devices as an example, where the co-oriented epitaxial film of Si C grows on the substrate and Grow with heat or re-grow with heat (heavy

Page 16 449932 V. Description of the invention (14) In the case of new oxidation or annealing), the oxide plays a very important role in device performance, and a lower annealing temperature is more helpful. The backside metal contact is not easily affected by the oxidizing environment necessary for the growth of the Si IC interface. Therefore, the backside ohmic contact must be deposited and re-oxidized after the silicon dioxide has grown (reoxidized or regrown). annealing. Unfortunately, the foregoing is necessary for the subsequent formation of the backside contact of the substrate (more typical temperature is 900 to 1050 ° C). An annealing temperature of about 850 ° C or above is necessary, because the thermal expansion rate does not match, so Will damage the Si C-silicon dioxide interface. Especially for MOSFET and i G B T have a great impact. S i C technology is still in its infancy and many related devices and material structures are yet to be tested or developed. Taking this process a step further may result in even lower annealing temperatures, and eventually result in ohmic contact (ie, no annealing) between the metal and the semiconductor by deposition. The invention has been described in detail, please refer to certain preferred embodiments so that the reader will not unduly experiment with the invention. However, those skilled in the art can easily find that many elements and parameters can be changed or adjusted to some extent without departing from the scope and essence of the present invention. In addition, names, titles, etc. are provided to assist the reader in the use of this document and should not be construed as limiting the scope of the invention. Therefore, only the following patent application scopes and reasonable extensions and equivalent meanings define the intellectual property rights of the present invention.

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Claims (1)

449932 VI. Scope of patent application L. A method for semiconductor reputation. The method includes: a conductor-doped substrate selected to form a metal semi-sister & λ wire, and ohmic contact with the conductor. The first surface ^ material to a conductive type having the same conductive substrate as the first conductive substrate J wherein the implanted dopant is provided at a temperature that is half the soil temperature, which is sufficient to activate the implanted dopant two. The substrate is first-annealed, and the effective carrier concentration is added to the semiconductor material for a period of time; on the implanted surface; a metal is deposited; and it is set at a temperature to anneal the metal to the implanted semiconductor material a second time The temperature of the second fire annealing is lower than the temperature at which any remote crystal layer on the substrate may undergo serious degradation, but high enough to form a '^ ohmic contact' between the implanted semiconductor material and the deposited metal = > 2. The method of claim 1 includes applying a screened doped material at room temperature. 3. The method according to item 丨 of the patent application, wherein the semiconductor substrate comprises silicon carbide. 4. The method of claim 3, wherein the screened dopant material is selected from the group consisting of nitrogen, aluminum, arsenic, phosphorus, boron, and gallium. 5. The method according to item 1 of the patent application range, wherein the first annealing is performed at a temperature of about 100 ec to about 1 300. (: Between temperature. 6) If the method of the scope of patent application, the metal is selected from the group including nickel, platinum, platinum, aluminum and convergence. 7. The method of scope of the patent application, 1. , Where the second annealing is O: \ 60 \ 60375.PTD Page 18 449932 VI. Please apply for a patent at a temperature below about 8 50 ° C. Euro 8. A method for treating carbides for semiconductor devices, the method comprising: 10% implanting a screened doped pine surface at room temperature, thereby forming a layer with an increased concentration: carbides ; / Since the implanted silicon carbide substrate is annealed for the first time on the silicon carbide substrate of the miscellaneous material; at least a worm crystal layer is grown on the surface of the broken carbide substrate, and a metal layer is deposited on the implanted surface of the silicon substrate; And the next one, "The second annealing of the metal and the implanted silicon carbide substrate under the coffee degree, the second degree of the two annealing is lower than the temperature of the epitaxial layer, which may be seriously degraded. An ohmic contact is formed between the implanted silicon carbide and the deposited metal. 9. The method as claimed in claim 8 of the patent, wherein the step of growing an epitaxial layer on the silicon carbide substrate is performed by The method is performed before the first annealing. Shi Ru declared the method in the scope of patent No. 8 in which the step of secreting the silicon carbide substrate on the silicon carbide substrate is performed after the first annealing of the silicon carbide substrate. , Arsenic, phosphorus, boron, and gallium. The method of item 8 in the patent range of the I / Λ patent, wherein the implanted carbonized carbon is annealed at a temperature between about wooc and about 130 ° C, and 0: \ 60 \ 60375.PTD No. 19 page 4 49 9 3 2 VI. Scope of Patent Application 1 3. The method according to item 8 of the patent scope, wherein the metal is selected from the group consisting of nickel, palladium, platinum, aluminum and titanium. 14. The method according to item 8 of the patent application, wherein the step of annealing the silicon carbide substrate and the deposited metal occurs at a temperature of less than 8500 t. 15. A semiconductor device comprising: a semiconductor substrate having a first surface, a second surface and a first conductivity type; at least one epitaxial layer on the first surface of the semiconductor substrate; An increased carrier concentration region 'is located in the semiconductor substrate and extends from the second surface of the punch material to the first surface; and two, f layers are deposited on the second surface of the semiconductor substrate, which An ohmic contact is formed on the interface of the region where the carrier concentration is increased. 1 ^, such as the semiconductor device in the scope of Shen Qing patent No. 丨 5, wherein the semiconductor material is a carbonized α α 1 # semiconductor device in the patent scope No. 15, wherein the implantation; A green system consisting of aluminum, arsenic, phosphorous, boron, and gallium, and a silicon alloy, such as: Application for the semiconductor device of the 16th patent area, where is the m-body of the carbide gate? The agricultural degree is between about 1 X 1 015 and about 1 X 1 cm—3. 0 1 9. For example, the semiconductor device in the carrier ’s agricultural item No. 8 in the carrier ’s Handu area within the patent application range. And greater than the carbonized carbon, ranging from about 1 × 10 18 to about 1 × 10 2 ° cnr; nn The starting carrier concentration in the evening. 2 0 · If the patent application is for the semiconductor device of the 15th item, where the epitaxial 0: Obstruct 0375.PTD Page 20 449932 6. The scope of the patent application layer is selected from gallium terminal acid; a 1 uminumga 1. 1 ium nitride; la gallium nitride (indium gailium nitride); and silicon , Gallium, aluminum, and indium oxide. 2 1. The semiconductor device according to item 16 of the scope of patent application, wherein the metal is selected from the group consisting of Lu, Iε, Fan, Ming and Qin. 22. A semiconductor device comprising:-a silicon carbide substrate having a first surface and a second surface and an initial concentration of a dopant imparting an initial conductivity type; There is at least one worm crystal layer on a surface; an increased carrier concentration region is located in the silicon carbide substrate and extends from the second surface to the first surface of the silicon carbide substrate; the doped material region is characterized by A dopant concentration gradually decreases from the second surface to the first surface; and a nickel ohmic contact is on the second surface of the silicon carbide substrate. 2 3. The semiconductor device according to item 22 of the application, wherein the implanted doping material is selected from the group consisting of nitrogen, aluminum, arsenic, phosphorus, boron, and gallium. 2 4. The semiconductor device according to item 22 of the patent application scope, wherein the initial carrier concentration in the silicon carbide is between about 1 X 1 015 and about 1 X 1 019 cnr3. 2 5. The semiconductor device according to item 24 of the patent application scope, wherein the carrier concentration in the increased carrier concentration region is between about lx 1018 and about lx 102 ° C ΠΓ3, and is greater than the carbonized stone. Within the initial carrier concentration. 2 6. The semiconductor device according to item 22 of the patent application scope, wherein the epitaxial Page 21 449 9 32 6. The patent application layer is selected from the group consisting of gallium nitrate; aluminum gallium nitride; indium gailium nitride; and silicon, gallium, aluminum, and indium oxide Groups of people. 27. The semiconductor device according to claim 22, wherein the semiconductor device is a vertical device. Page 22