MXPA01002751A

MXPA01002751A - Low temperature formation of backside ohmic contacts for vertical devices.

Info

Publication number: MXPA01002751A
Application number: MXPA01002751A
Authority: MX
Inventors: David B Slater Jr
Original assignee: Cree Inc
Priority date: 1998-09-16
Filing date: 1999-09-16
Publication date: 2002-04-08
Also published as: WO2000016382A1; TW449932B; CN1178277C; EP1125320A1; CA2343416A1; AU6391699A; JP4785249B2; CN1323446A; KR20010079759A; JP2011151428A; JP2002525849A; KR100694681B1

Abstract

The invention comprises a method for forming a metal-semiconductor ohmic contact (18) for use in a semiconductor device (10) having a plurality of epitaxial layers (14a-c) wherein the ohmic contact (18) is preferably formed after deposition of the epitaxial layers (14a-c). The invention also comprises a semiconductor device comprising a plurality of epitaxial layers and an ohmic contact.

Description

TRAINING AT LOW TEMPERATURE OF DORSAL OCOMMIC CONTACTS FOR VERTICAL DEVICES FIELD OF THE INVENTION The present invention relates to ohmic contacts for semiconductor materials. In particular, the invention relates to methods for forming ohmic contacts for devices that include a variety of semiconductor materials.

BACKGROUND OF THE INVENTION In the context of microelectronics, the circuits are made from the sequential connection of semiconductor devices. Generally speaking, semiconductor devices are operated, and used to control, the flow of electrical current within specific circuits to perform particular tasks. To connect the semiconductor devices with each other, suitable contacts must be made between the semiconductor devices. Due to its high conductivity, the most useful and convenient matepales for transporting current from one device to another are metals. Said metallic contacts must interfere either minimally or preferably not interfere with the operation of the device or the metal carrying the current. In addition, the metallic contact must be physical ? -i, ..i »i and chemically compatible with the semiconductor matepal to which it is connected. The types of contact that show these desirable characteristics are known as "ohmic contacts". An ohmic contact is generally defined as a metallic semiconductor contact having negligible contact resistance in relation to the volumetric or dispersion resistance of the semiconductor, Sze, Physics of Semiconductor Devices, second edition, 1981, page 304. As stated therein , a suitable ohmic contact does not significantly change the performance of the device to which it is connected, and can supply any current required with a voltage drop that is adequately small compared to the drop in the entire active region of the device. Ohmic contacts and methods for producing ohmic contacts are known in the art. For example, the patents of E.U.A. 5,409,859 and 5,323,022 to Glass et al., ("Glass patents"), disclose an ohmic contact structure formed of platinum and p-type silicon carbide and a method for making the ohmic structures. L. SpieB et al., "Aluminum Implantation of p-SiC for Ohmic Contacts," Diamond and Related Materials, vol. 6, pp, 1414-1419 (1997); J. Chen et al., "Contact Resistivity of Re, Pt, and Ta Films On n-type B-SiC: preliminary results", Materials and Science 20 Engineering, B29, pp. 185-189 (1995); and WO 98/37584 also describe ohmic contacts and SiC. Although the ohmic contacts and methods for making them are known, the known methods for producing ohmic contacts, and •? ¥ ** ?? n * 3 «aa, especially those produced using a silicon carbide substrate, are difficult, even when performed properly. The problems related to obtaining ohmic contacts are thousands and cumulative. The limited electrical conductivity of the semiconductor due to the low concentrations of holes or electrons can hinder or even prevent the formation of an ohmic contact. In the same way, the little mobility of holes or electrons inside the semiconductor can hinder and even prevent the formation of an ohmic contact. As described in the Glass patents, differences in work function between the contact metal and the semiconductor can cause a potential barrier resulting in a contact that shows rectifying (non-ohmic) current flow versus applied voltage. Even between two identical semiconductor materials, the intimate contact with very different electron-hole concentrations, there may be a potential barrier (integrated potential), leading to a rectifier contact instead of an ohmic one. In Glass's patents, these problems were attacked by inserting a different p-type doped SiC layer between the p-type SiC substrate and the contact metal. More difficult problems were encountered in forming ohmic contacts for semiconductor devices based on gallium and indium from newer generations. The formation of an ohmic contact between a semiconductor and a metal requires the correct alloy of the semiconductor and the contact metal on its contact surface. Selectively increasing the concentration of voids / electrons on the surface of the semiconductor where the ohmic contact metal is deposited is known as an effective means to help the contact process achieve an ohmic contact. This procedure is typically achieved through ion implantation, which is recognized as a technique of selective doping in silicon and silicon carbide technology. However, in the case of silicon carbide, ion implantation is generally carried out at elevated temperatures (typically >600 ° C) in order to minimize the damage to the crystalline network of silicon carbide. "Activating" the implanted atoms to achieve high carrier concentrations often requires annealing temperatures of more than 1600 ° C, often at an overpressure of silicon. The equipment required for this ion implantation technique is specialized and expensive. After high temperature ion implantation and subsequent annealing, the contact metal is deposited on the surface of the implanted substrate and annealed at temperatures above 900 ° C. This method for forming contacts in semiconductor devices incorporating gallium nitride or indium-gallium nitride is not viable since these compounds disassociate at elevated temperatures. A theoretical answer to this problem would be to form an ohmic contact in the substrate before growing the delicate epitaxial layers (e.g., gallium nitride layers) necessary to complete the semiconductor device. However, this procedure is not convenient, because it inserts an unwanted contaminant, the contact metal, into the epitaxic growth system. The polluting metal can have the effect of an epitaxic growth by interfering with reticulum growth, doping, reaction rate or all of these factors. In addition, metallic impurities can degrade the optical and electrical properties of the epitaxial layers. Similarly, many semiconductor devices, such as metal-oxide semiconductor field effect transistors ("MOSFETS"), require a layer of a semiconductor oxide (eg, silicon dioxide). The high temperatures related to traditional ion implantation techniques and contact metal annealing or implant procedures place a strong stress on the oxide layers, which can damage the oxide layers, the semiconductor-oxide contact surface and the same device. Alternatively, forming the ohmic contact before creating the oxide layer is impractical since the oxidizing environment used to form the oxide layers has adverse effects on the ohmic contact. Therefore, there is a need for a practical and economical method for forming an ohmic contact to be used in conjunction with a semiconductor device that does not show the manufacturing problems discussed above. There is also a need for a type of semiconductor device that incorporates an ohmic contact but is economical in its manufacture.

OBJECTIVE AND BRIEF DESCRIPTION OF THE INVENTION An object of the invention is to provide a semiconductor device incorporating an ohmic contact. Another object of the invention is to provide a semiconductor device comprising silicon carbide and an ohmic contact. It is another object of the invention to provide a semiconductor device incorporating an ohmic contact that is economical in its manufacture. Another object of the invention is to provide a method for forming a semiconductor device incorporating an ohmic contact. The invention meets these objectives with a method for forming an ohmic semiconductor metal contact for a semiconductor device. The method comprises implanting a selected dopant material on a surface of a semiconductor substrate having a type of initial conductivity. The implanted impurifier provides the same type of conductivity as the semiconductor substrate. The implantation of the doping agent is followed by the annealing of the semiconductor substrate implanted a first time at a temperature and for a time sufficient to activate the atoms of the implanted docot and increase the effective concentrations of the carrier. After the first annealing, a metal is deposited on the implanted surface of the semiconductor material. Next, an annealing of the metal and the implanted semiconductor material takes place. This second annealing is at a temperature below the current one would occur a considerable degradation of any epitaxial layer placed on the substrate, but high enough to form an ohmic contact between the implanted semiconductor material and the deposited metal. The invention also achieves these objectives with a semiconductor device comprising a semiconductor substrate having a first surface and a second surface and a first type of conductivity. The device also comprises at least one epitaxial layer that grows or is placed on the first surface of the semiconductor substrate. The semiconductor substrate is further defined because it has an area of increased carrier concentration in the substrate extending from the second surface (the surface opposite the epitaxial layer) to the first surface. The device further comprises a layer of metal deposited on the second surface of the substrate to form an ohmic contact on the contact surface of the metal and the area of increased carrier concentration. The above objects, advantages and features of the invention and others, and the manner in which they are met, will be more apparent after considering the following detailed description of the invention together with the accompanying drawings, which illustrate exemplary embodiments, and in which: BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic cross section diagram of a semiconductor device in accordance with the present invention. Fig. 2 is a schematic cross section diagram of a doping device as used in the method according to the invention.

DETAILED DESCRIPTION OF THE INVENTION The present invention is a semiconductor device incorporating an ohmic contact and a method for forming the ohmic contact. Those familiar with broadband semiconductors, such as silicon carbide, and semiconductor devices formed from them will understand that, the invention is more useful for making a semiconductor device and an ohmic contact using non-p-type silicon carbide ("SiC" ). Therefore, to facilitate the explanation, the following description of the invention and examples will be directed towards an embodiment of the invention using SiC. However, those skilled in the art will readily recognize that the invention can be easily adapted for use with other semiconductor materials such as silicon, gallium nitride, aluminum-gallium nitride., and indium-gallium nitride. As used herein, aluminum-gallium nitride and indium-gallium nitride include compounds wherein the molar percentages of aluminum and gallium or indium and gallium equals 1. In a broad aspect, the invention is a semiconductor device comprising a semiconductor substrate having an initial concentration of dopant imparting a type of initial conductivity. The semiconductor substrate may be of type n or p. The device also comprises at least one epitaxial layer located adjacent to a surface of the semiconductor substrate. The claimed semiconductor device is further characterized in that the semiconductor substrate is defined by a zone of increased carrier concentration extending from the substrate surface opposite the epitaxial layers to the surface adjacent the epitaxial layers. A metal layer is deposited on the substrate in the area of increased carrier concentration to form an ohmic contact on the contact surface of the metal and the substrate. Referring now to Figure 1, a schematic of the semiconductor device 10 according to the invention is presented. The device 10 comprises a semiconductor substrate 12, which for purposes of explanation is considered as SiC, however, it should be understood that other semiconductor materials, such as silicon, can be used as a substrate in the practice of the invention. The SiC 12 substrate can be of the p or n type.

Located adjacent to the SiC 12 substrate are the additional components 14 necessary to complete the semiconductor device. For example and as shown in Figure 1, the semiconductor device may be a light emitting diode ("LED") having sequential epitaxial layers 14a, 14b and 14c of p and n-type semiconductor materials. In a preferred embodiment, the invention is a vertical semiconductor device such as an LED, metal-oxide semiconductor field effect transistor ("MOSFET"), lasers, or Schottky rectifiers that are composed of several epitaxial layers adjacent to the semiconductor substrate. As will be discussed below, the device according to the invention is particularly suitable for vertical semiconductor devices comprising materials having low melting or dissociation temperatures. These materials may include gallium nitride, indium-gallium nitride, and aluminum-gallium nitride. The claimed device is further characterized in that it has an area of increased concentration of carrier 16 in the dorsal part of the semiconductor substrate. In other words, the semiconducting substrate, in this case SiC, has a carrier concentration near the surface of the substrate opposite the epitaxial layers that is greater than the carrier concentration it shows on the remainder of the substrate. The line that serves as the boundary with the area of increased concentration of carrier 16 is dotted to represent the fact that there is no sharp limit to the concentration of carrier when substrate 12 suddenly changes. The carrier concentration decreases as the distance of the dorsal surface of the substrate increases until the carrier concentration is at the initial carrier concentration. As will be discussed below, the area of increased carrier concentration is formed by an ion implantation technique at room temperature using doctores commonly related to semiconductor materials type p and n. For example, and still referring to FIG. 1, a preferred embodiment of the claimed device comprises a n-type SiC substrate doped with nitrogen. It should be understood that the n-type SiC formed from other n-type impurifiers together with the various SiC type t types can also be used in accordance with the invention. The SiC 12 substrate is preferably low to highly contaminated and has an initial carrier concentration between about 1x1015 and about 1x1019cm3. The terms "little" and "very" are imprecise and are used on purpose to show that the initial concentration of carrier can vary considerably. Although the initial carrier concentration can vary considerably, tests have shown that substrates that are impurified from less to more provide the best results. By means of the ionic implantation of a selected dopant material (for example hydrogen) on the surface opposite the epitaxial layers 14, a zone 16 containing a greater concentration of carrier is created than the remainder of the substrate 12. Preferably, the ion implantation is carried out at a level that creates a zone of increased concentration of carrier 16 in the dorsal part of the substrate showing a carrier concentration between approximately 1x10 and approximately 1x1020 cm "3 and which is always greater than the initial concentration of carrier. in the art they will recognize that a zone of increased carrier concentration, as described above, can also be formed during the growth of the substrate, however, the difficulties related to the variable feed rates of the required dopants and other difficulties typically associated with the crystal growth methods h This procedure is impractical. Preferred n-type dopants to be used to form the increased concentration zone of carrier 16 are nitrogen, arsenic and phosphorus. Preferred p-type impurifiers to be used to form the increased concentration zone of carrier 16 are aluminum, boron and gallium. Although the applicant does not wish to be bound by a particular theory, the evidence suggests that the area of increased concentration of carrier 16 allows the creation of a metallic contact that exhibits ohmic properties. In a preferred embodiment, a selected metal contact 18 having a melting point, vapor pressure and suitable physical and chemical properties for use with the general semiconductor device is deposited on the surface of the SiC substrate in the areas of increased concentration of carrier 16 to form a surface of - - -TO*. contact 20 between the metal and the substrate. Preferred metals include nickel, palladium, platinum, aluminum and titanium, with nickel being very preferred. The device, including the metal and the substrate is annealed at a temperature low enough to avoid damaging the device and specifically any epitaxial layer, but high enough to form an ohmic contact on the contact surface of the metal and the substrate. Again, although the applicant does not wish to be bound by any particular theory, it seems useful to create the increased bearer concentration zone to serve as a receiver for the contact metal. Thus, in another embodiment, the invention comprises the method for forming the ohmic contact used in the semiconductor device described above. In a broad aspect, the invention is a method for forming a metal semiconductor contact for a semiconductor device. The method comprises implanting a selected dopant material in a semiconductor substrate having a first type of conductivity and characterized in that the implanted dopant provides the same type of conductivity as the substrate. For purposes of this discussion it will be assumed that the semiconductor substrate is a SiC substrate and that the doping material is deposited on a surface of the SiC substrate. However, those skilled in the art will readily recognize that the invention can easily be adapted for use with other semiconductor materials. An annealing step follows the implantation of the selected dopant material. In this annealing step the SiC substrate t, f implanted is annealed at a temperature and for a time sufficient to activate the atoms of the implanted dopant to efficiently increase the carrier concentration of the impurifier atoms implanted in the SiC substrate. A contact metal is then deposited on the implanted surface of the SiC substrate. The deposited contact metal and the implanted surface of the SiC substrate are annealed. This second annealing is done at a lower temperature at which any epitaxial layer placed on the substrate could undergo considerable degradation but high enough to form an ohmic contact between the implanted SiC and the deposited metal. In a preferred embodiment, the semiconductor substrate may comprise a n-type or p-type substrate that may possess an initial concentration of light, moderate or high dopant. For example, when the substrate is SiC type n, the SiC substrate may possess an initial concentration of dopant of about 1x1015 (slightly contaminated) to 1x1019cm3 (highly contaminated) .The terms "light", "moderate" and " high "are imprecise and are used to indicate that the initial concentration of the dopant in the substrate material may vary.The tests have shown that moderate to high doped substrates achieve the best results with the invention.The semiconductor substrate is then implanted With a selected dopant material and annealed, Preferably impurifier implantation occurs at room temperature and subsequent annealing occurs at a temperature between about 800 ° C and about 1300 ° C. The dopant generally related to the type of conductivity of the substrate can be used as the impurifier for the implantation step, for example when the substrate is SiC type n initially doped with nitrogen, nitrogen can serve as the impurifier implanted. Similarly, when the substrate is SiC type p initially impurified with aluminum, aluminum can serve as the impurifier implanted. Other possible n-type impurifiers are arsenic and phosphorus. Boron and gallium can serve as optional p-type impurifiers. Those skilled in the art will readily recognize that implantation of the doping material can be achieved at high temperatures. In fact, high temperature implantation is typically preferred in the context of SiC in order to reduce the damage to the SiC network structure. However, in the context of SiC, ion implantation at high temperature poses drawbacks in the commercial use of the invention. The ion implantation equipment with the ability to heat the SiC substrate during implantation is atypical, expensive and oriented to research and development uses rather than low-cost, high-volume uses. In addition, when SiC substrates are heated to high temperatures, they must be heated and cooled at a rate that does not cause them to fracture by delaying the production process. Accordingly, the preferred implantation method is implantation at room temperature for use with this invention. It has been It has been discovered that the implantation at room temperature of impuritator followed by an annealing step in a simple ventilated oven able to reach 1300 ° C and with capacity for 100 or more contact plates achieves satisfactory results and increases in a lot of production. The implantation at room temperature of the dopant is preferably carried out in order to create a zone of increased concentration of impurifier near the implanted surface of the semiconductor substrate. Figure 2 is a schematic representation of the implantation procedure according to the invention. In this example, an SiC substrate n 22 having an initial dopant concentration of approximately 1x1018 cm "3 is implanted with atomic or diatomic nitrogen 24 at powers of 10 to 60 keV with doses of 1x1013 cm" 2 or more. In some cases, more than one power of 15 implant can be used to create a more gradual carrier concentration distribution. The implantation procedure produces a zone 26 near the implanted surface of the SiC substrate at approximately 1000 angstroms depth having a total chemical dopant concentration of approximately 1x1019 to 1x1020 cm "3 with the concentration of impurifier 20 implanted decreasing while increasing the distance of the implanted surface The concentration of the purifier outside the increased concentration zone of dopant 26 remains substantially the same as the initial dopant concentration. "*** - - ** • - •" ** enhanced agreement of carrier 26 is represented as a dotted line to indicate that the change in the bearer agreement between zone 26 and the rest of the substrate is not marked but gradual. Those skilled in the art will recognize that the implantation power or dose can be easily changed to achieve the desired concentrations and thicknesses. As already mentioned, it is necessary to anneal the implanted substrate. Annealing is required because some impurifier ions implanted are not "active" immediately after implantation. The term "assets" is used to describe the availability of ions 10 implanted to contribute to the total concentration of carrier of the implanted substrate. During implantation, the crystalline network of the SiC substrate is practically bombarded with doping ions. These ions collide with the crystal lattice where they are retained. This bombing does not give as 15 result in a perfect insertion of the doping ions in the existing crystalline network. The initial placement of many of the doping ions can prevent the ions from being "active" participants in the crystal lattice, which can be damaged by the bombardment. Annealing (i.e., heating) the implanted SiC substrate provides a device by which ions 20 implanted and the crystalline network of the substrate can be rearranged in a more orderly fashion and recover from the damage caused during the implantation of dopants. ____ ¡___v___________________ Using rounded numbers for explanatory purposes only, the implementation procedure can be considered as shown below. If 100 nitrogen ions are implanted in a n- SiC substrate having an initial concentration of nitrogen atoms x, immediately after implantation the substrate can only exhibit characteristics related to a substrate having "x + 10" ions of nitrogen. However, if the substrate is annealed and the implanted ions are allowed to settle into the crystal lattice, the substrate may exhibit characteristics related to a substrate having "x + 90" nitrogen ions. In this way, the annealing step has "activated" about 80 of the nitrogen ions implanted. Tests show that annealing the implanted SiC substrate at room temperature, at temperatures between about 1000 ° C to 1300 ° C for two hours or less will produce satisfactory results. The temperature and time can be easily adjusted to achieve a more complete activation of the implanted dose. The semiconductor device comprising the aforementioned implanted substrate has at least one epitaxial layer. The epitaxial layer can be grown by any means known to those skilled in the art. In a preferred embodiment of the invention, the epitaxial layer is deposited prior to the implantation of substrate dopant. However, the desired epitaxial layer or the subsequently manufactured device may be made of or composed of a material (e.g., gallium nitride or a * - • • • • • • • • silicon oxide) unable to withstand the high temperature annealing of the implanted substrate. In this case, the epitaxial layer can be formed after the implantation of the dopant. After the semiconductor substrate is implanted and a well-annealed zone of increased concentration of dopant is established, and any epitaxial layer is placed on the substrate, the metal selected to form the ohmic contact is applied to the surface of the substrate in the area of increased concentration of carrier. The metal can be any metal typically used to form electrical contacts that has a sufficiently high melting point and vapor pressure and does not interact adversely with the substrate material. Preferred materials include nickel, palladium, platinum, titanium and aluminum with nickel being the most preferred. Preferably, the contact metal is deposited on the surface of the substrate to form a layer 300 angstroms thick or more. A second annealing follows the deposit. However, this annealing is not a long-term annealing at high temperature. This annealing preferably occurs at a temperature of less than about 1000 ° C and most preferably less than about 800 ° C for 20 minutes or less and most preferably for 5 minutes or less. These temperatures and periods are low enough to avoid damaging any epitaxial layer found in the substrate. He - annealing the contact metal to the semiconductor substrate results in an ohmic contact at the contact surface of the metal and the substrate. In a more specific embodiment of the invention, a metal semiconductor according to the invention was created using an SiC type n substrate that was first implanted at a power of 50 keV with a dose of 3x1014 cm 2 of atomic nitrogen followed by an implantation secondary to 25 keV at 5x1014 cm "2. The implantation followed an activation anneal at 1300 ° C for 60 to 90 minutes in an argon environment in an oven. Subsequently, the contact metal, nickel, was deposited on the implanted surface at a thickness of 2500 angstroms. The contact annealing was carried out at 800 ° C for 2 minutes in argon. The resulting ohmic contact showed satisfactory ohmic properties. Those skilled in the art will recognize that it is also possible to carry out contact annealing in situ with epitaxic growth. The invention offers a substantial advantage for vertical devices such as photodetectors, light emitting diodes (LEDs), lasers, power devices such as metal-oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), pn connections and Schottky rectifiers, and microwave devices such as SITs (static induction transistors). In the case of detectors, LEDs and lasers, epitaxially grown gallium nitride and indium-gallium nitride layers should not be annealed at temperatures that could severely damage the layers. In the case of indium-gallium nitride, time at elevated temperatures becomes critical as the alloy composition of the alloy increases. Reducing the annealing temperature of the dorsal contact also reduces the potential for disintegration or dissociation of the indium or gallium components in the stretched heteroepitaxial films grown on the SiC substrates. In the case of power devices in which SiC homoepitaxial films grow on the substrate and grow or re-grow thermally (reoxidized or annealed), the oxides have an integral role in the performance of the device and a lower annealing temperature is an advantage. The metallic dorsal contact can not be subjected to the oxidizing environment required to grow the contact surface of silicon dioxide - SiC, therefore, the dorsal ohmic contact must be deposited and annealed after the silicon oxide grows (reoxidized or returned to grow). Unfortunately, prior art annealing temperatures of about 850 ° C or higher are required to subsequently form a contact at the back of the substrate (typically 900 to 1050 ° C) which will create defects in the dioxide contact surface SiC silicon due to imbalances in the speed of thermal expansion. This is particularly bad for MOSFETs and IGBTs. SiC technology is starting and many proposed devices and material structures have yet to be examined or developed.

Further development of this process can lead to annealing temperatures that are even lower, ultimately leading to an ohmic contact between the metal and the semiconductor as it is deposited (ie, without annealing). The invention has been described in detail, with reference to certain preferred embodiments, in order to allow the reader to practice the invention without much experimentation. However, one skilled in the art will readily recognize that many of the components and parameters may vary or be modified to some degree without departing from the scope and essence of the invention. In addition, titles, headings or the like are provided to improve reader understanding of this document, and should not be read as limiting the scope of the present invention. Therefore, only the following claims and extensions and reasonable equivalences define the intellectual property rights of the invention.

Claims

NOVELTY OF THE INVENTION CLAIMS

1. - A method for forming an ohmic contact for silicon carbide (12) for a semiconductor device, said method comprising: implanting at room temperature a selected dopant material to a surface of a silicon carbide substrate (12) thereby forming a layer ( 16) on the silicon carbide substrate having an increased concentration of dopant material; annealing the implanted silicon carbide substrate a first time; growing at least one epitaxial layer of a compound other than SiC that dissociates at less than the dissociation temperature of SiC (14) on the silicon carbide substrate opposite the implanted surface; depositing a layer of metal (18) on the implanted surface; of the silicon carbide substrate (12); and then annealing the metal (18) and the implanted silicon carbide substrate (12,16) a second time at a temperature lower than that at which considerable degradation of the compound forming the epitaxial layer (14) would occur, but sufficiently high to form an ohmic contact between the implanted silicon carbide (12,16) and the deposited metal.

2. A method according to claim 1, further characterized in that the step of growing the epitaxial layer (14) on the silicon carbide substrate (12) precedes the first annealing of the implanted silicon carbide substrate (12). ).

3. A method with claim 1, further characterized in that the step of growing the epitaxial layer (14) on the silicon carbide substrate (12) follows the first annealing of the implanted silicon carbide substrate (12).

4. A method according to claim 1, further characterized in that the selected impurifier material is selected from the group consisting of nitrogen, aluminum, arsenic, phosphorus, boron and gallium.

5. A method according to claim 1, further characterized in that the first annealing of the implanted silicon carbide substrate (12,16) occurs at a temperature greater than 1000 ° C at 1300 ° C.

6. A method according to claim 1, further characterized in that the metal (18) is selected from the group comprising nickel, palladium, platinum, aluminum and titanium.

7. A method according to claim 1, further characterized in that the annealing step of the silicon carbide substrate (12) and the deposited metal (18) occurs at a temperature lower than 850 ° C.

8. A semiconductor device (10) comprising: a semiconductor substrate (12) having a first surface and a second surface and a first type of conductivity; at least one epitaxial layer (14) on the first surface of the semiconductor substrate (12), said epitaxial layer formed of a material with a dissociation temperature lower than that of the semiconductor substrate; a zone (16) of increased carrier concentration in said semiconductor substrate (12) and extending from the second surface of the semiconductor material towards the first surface; and a metal layer (18) deposited on the second surface of the semiconductor substrate (12) which forms an ohmic contact on the contact surface (20) of the metal and the area of increased carrier concentration (16).

9. A semiconductor device according to claim 8, further characterized in that the semiconductor substrate (12) is a silicon carbide.

10. A semiconductor device according to claim 8, further characterized in that the impurifier material implanted is selected from the group consisting of nitrogen, aluminum, arsenic, phosphorus, boron and gallium.

11. A semiconductor device according to claim 9, further characterized in that the initial concentration of carrier in the silicon carbide is between 1x1015 to 1x1019 cm "3. A semiconductor device according to claim 11, further characterized because the concentration of carrier in the area of increased concentration of carrier (16) is between 1x1018 and ____________! 1x1020 cm "3 and is greater than the initial concentration of carrier in the silicon carbide 13. A semiconductor device according to claim 8, further characterized in that the epitaxial layers (14) are selected from the group consisting of gallium, aluminum-gallium nitride, indium-gallium nitride, and silicon, gallium, aluminum, and indium oxides 14. A semiconductor device according to claim 9, further characterized in that the metal (18) is selected from the group comprising nickel, palladium, platinum, aluminum and titanium 15. A semiconductor device (10), comprising: a silicon carbide substrate (12) having a first surface and a second surface and an initial concentration of dopant imparting an initial type of conductivity, at least one epitaxial layer (14) on the first substrate surface of silicon carbide (12), an area of increased concentration of carrier (16) in the substrate of silicon carbide (12) and extending from the second surface of the silicon substrate (12) to the first surface, said area of doping material (16) being characterized by a concentration of dopant progressively decreasing from the second surface towards the first surface; and an ohmic nickel contact (18) on the second surface of the silicon carbide substrate (12). 16. A semiconductor device according to claim 15, further characterized in that the doping material __i__________? implanted is selected from the group consisting of nitrogen, aluminum, arsenic, phosphorus, boron and gallium. 17. A semiconductor device according to claim 15, further characterized in that the initial concentration of carrier in the silicon carbide is between 1x1015 to 1x1019 cm "3. A semiconductor device according to claim 17, further characterized because the carrier concentration in the area of increased carrier concentration is between 1x1018 and 1x1020 cm'3 and is greater than the initial concentration of carrier in the silicon carbide 19.- A semiconductor device according to claim 15, characterized in addition, because the epitaxial layers (14) are selected from the group consisting of gallium nitride, aluminum-gallium nitride, indium-gallium nitride, and silicon, gallium, aluminum, and indium oxides 20.- A semiconductor device in compliance with claim 15, further characterized in that the semiconductor device is a vertical device. _______ "- - ~» «• -