JP3303530B2 - Method for manufacturing silicon carbide semiconductor device - Google Patents
Method for manufacturing silicon carbide semiconductor deviceInfo
- Publication number
- JP3303530B2 JP3303530B2 JP14133794A JP14133794A JP3303530B2 JP 3303530 B2 JP3303530 B2 JP 3303530B2 JP 14133794 A JP14133794 A JP 14133794A JP 14133794 A JP14133794 A JP 14133794A JP 3303530 B2 JP3303530 B2 JP 3303530B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon carbide
- carbide semiconductor
- semiconductor device
- sic
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【0001】[0001]
【産業上の利用分野】本発明は、炭化けい素 (以下Si
Cと記す) からなる半導体基体にオーム性接触する電極
を備えたSiC半導体素子の製造方法に関する。The present invention relates to silicon carbide (hereinafter referred to as Si)
C) which is provided with an electrode that makes ohmic contact with a semiconductor substrate made of SiC.
【0002】[0002]
【従来の技術】半導体材料として広く用いられているシ
リコン (Si) に対してその性能限界が考慮され、過酷
な環境下でも使用に耐えうる半導体材料が模索されてき
ている。そして、例えば3eVのバンドギャップを持つ
SiCのようなワイドギャップ半導体が次世代の半導体
材料として有望視されている。SiCはSiと比較して
熱伝導度が3倍、最大電界強度が10倍、電子ドリフト
速度が2倍という特性を持っている。2. Description of the Related Art Considering the performance limit of silicon (Si), which is widely used as a semiconductor material, a semiconductor material which can be used even in a severe environment has been sought. For example, a wide gap semiconductor such as SiC having a band gap of 3 eV is expected to be used as a next-generation semiconductor material. Compared to Si, SiC has characteristics of three times the thermal conductivity, 10 times the maximum electric field strength, and twice the electron drift velocity.
【0003】[0003]
【発明が解決しようとする課題】大きい電流が流れる電
力用半導体素子では、金属・半導体界面のオーム性接触
が重要となる。良好なオーム性接触は、素子の特性を劣
化させることがない。SiCは、キャリア濃度が高いほ
ど金属の半導体界面の接触抵抗が低いという報告があ
る。すなわち、Appl. Phys. Lett. Vol 62、No4
(Jan.1933) p25 に記載されているように、エピタキシ
ャル成長時にAlをドーピングして得られたp形6H−
SiCでは、キャリア濃度が5.5×1015cm3 と低い
ときにAl−Tiからなる電極との間のRcは2.9×1
0-2Ω・cm3 と高く、キャリア濃度が2.9×1019/
cm3 のときにRcが1.5×10-5Ω・cm2 となる。
キャリア濃度が1015〜1017/cm3 程度と低い良質
のSiCは市販されているが、この市販のSiCにより
素子を作製した場合には低いRcは得られない。逆に高
キャリア濃度のSiC結晶では、低いRcをもつ電極は
形成できるが、マイクロパイプと呼ばれる結晶欠陥が多
数存在するなど、質のより高いキャリア濃度のSiC結
晶を得るのが難しい。In a power semiconductor element through which a large current flows, ohmic contact between a metal and a semiconductor interface is important. Good ohmic contact does not degrade device characteristics. It has been reported that the higher the carrier concentration of SiC, the lower the contact resistance at the metal-semiconductor interface. That is, Appl. Phys. Lett. Vol 62, No. 4
(Jan. 1933) As described in p25, p-type 6H-
In the case of SiC, when the carrier concentration is as low as 5.5 × 10 15 cm 3 , Rc between the electrode made of Al—Ti is 2.9 × 1.
It is as high as 0 -2 Ω · cm 3 and the carrier concentration is 2.9 × 10 19 /
When it is cm 3 , Rc is 1.5 × 10 −5 Ω · cm 2 .
Although SiC carrier concentration 10 15 ~10 17 / cm 3 as low as about quality are commercially available, low Rc can not be obtained in the case of manufacturing an element by a commercially available SiC this. Conversely, in the case of a SiC crystal having a high carrier concentration, an electrode having a low Rc can be formed, but it is difficult to obtain a SiC crystal having a higher carrier concentration because of the presence of many crystal defects called micropipes.
【0004】本発明の目的は、上述の問題を解決し、良
質の低キャリア濃度のSiC結晶に低いRcをもつ電極
を形成するSiC半導体素子の製造方法を提供すること
にある。An object of the present invention is to solve the above-mentioned problems and to provide a method of manufacturing an SiC semiconductor device in which an electrode having a low Rc is formed on a high-quality low-carrier-concentration SiC crystal.
【0005】[0005]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明のSiC半導体素子の製造方法は、一導電
形の炭化けい素半導体基体の一面から同一導電形化する
ドーパントをイオン種としてイオン注入し、次いで前記
一面の表面層を熱酸化し、生じた酸化層を除去したの
ち、露出した基体面に金属電極を被着してオーム性接触
電極を形成する工程において、基体表面からイオン注入
するイオン種の濃度がピーク値にある深さまで熱酸化す
る。そして、熱酸化を水蒸気酸化で行うのが良い。ま
た、酸化層の除去を弗酸の水溶液を用いて行うことが良
い。In order to achieve the above object, a method of manufacturing a SiC semiconductor device according to the present invention is directed to a method of manufacturing a SiC semiconductor device, comprising: ion implantation as, and then the surface layer of said one surface is thermally oxidized after removing the resulting oxide layer, a metal electrode on the exposed substrate surface in the step of forming the ohmic contact electrode by adhering, from the substrate surface Ion implantation
Thermal oxidization to a depth where the concentration of the ionic species is at a peak value . Then, the thermal oxidation is preferably performed by steam oxidation. Ma
Was, it is better to perform the removal of the oxide layer with an aqueous solution of hydrofluoric acid.
【0006】[0006]
【作用】イオン注入により半導体基体に入射したイオン
種は、ジグザグの径路を通って停止する。入射点より停
止点までを直線で結び、これを入射点よりの垂線に投影
した値、つまり基体表面よりの深さを射影飛程と呼ぶ。
射影飛程は統計的な変動幅をもって分布する結果、打ち
込まれたイオン種は半導体基体中でピーク濃度を中心と
するガウス形の分布をすると考えられる。従って、Si
C基体と同一導電形のドーパントをイオン注入し、表面
からそのピーク濃度の位置までSiC基体を熱酸化し、
その酸化層を除去すれば、打ち込まれたドーパントの最
も濃度の高い、低抵抗の部分が露出するので、基体自体
は低キャリア濃度でも低い接触抵抗をもつオーム性接触
電極をSiC基体上に形成することができる。The ion species incident on the semiconductor substrate by the ion implantation stops through the zigzag path. A value obtained by connecting a line from the incident point to the stop point with a straight line and projecting the line to a perpendicular line from the incident point, that is, a depth from the substrate surface is called a projection range.
As a result, the projected range is distributed with a statistical fluctuation range, and it is considered that the implanted ion species have a Gaussian distribution centered on the peak concentration in the semiconductor substrate. Therefore, Si
Ion implantation of a dopant of the same conductivity type as the C base, thermal oxidation of the SiC base from the surface to the position of its peak concentration,
If the oxide layer is removed, the portion of the implanted dopant with the highest concentration and low resistance is exposed, so that the substrate itself forms an ohmic contact electrode having low contact resistance even at a low carrier concentration on the SiC substrate. be able to.
【0007】[0007]
【実施例】以下、図を引用して本発明の実施例について
述べる。図1に示すようにn形6H−SiCよりなる基
板1に、イオン種2としてn形のドーパントである窒素
を用いてイオン注入した。イオン注入の条件は、加速エ
ネルギー100KeV、ドーズ量は5×1015/cm2
である。これにより、図2に示すように射影飛程分布の
ピーク値Ro=0.25μmを中心として高濃度ドープ層
3が形成される。図6は、n形6HSiC基板に上述と
同様の条件で窒素のイオン注入を行い、窒素雰囲気中、
1200℃で10時間のアニールを行ったのちの拡がり
抵抗の測定結果である。図のように抵抗値は窒素のRo
0.25μm付近を中心とするガウス分布を示し、深さ0.
27〜0.29μmの位置で急激に抵抗が低下している。
このことは、注入された窒素がほとんど拡散せずに、そ
の場で低抵抗の高濃度層を形成していることを示してい
る。そこで、1200℃での3時間35分のスチーム酸
化により表面から射影飛程分布のピーク値Roの深さま
で酸化した。これにより図3に示すように基板1の表面
は膜厚0.49μmの酸化膜4で覆われた。スチーム酸化
のようなウエット酸化は、酸化速度の遅いSiCには適
している。酸化されるSiCは、酸化膜の体積1に対し
て0.54である。このあと、体積比で弗酸を20倍の水
で稀釈したエッチング液を用い、酸化膜を除去した。こ
の結果、図4に示すように低抵抗の高濃度ドープ層3が
露出した。この高濃度ドープ層3の表面は平滑であっ
た。次いで、図5に示すように電極材料としてNiを用
いて金属電極5を高濃度ドープ層3に接触させた。この
電極は、n形6H−SiCの上にそのまま被着した電極
よりも約4割以上低いRcを示した。しかし、酸化膜4
をドライエッチングにより除去すると、高濃度ドープ層
3の表面が凹凸となり、低いRcは得られなかった。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. As shown in FIG. 1, ions were implanted into a substrate 1 made of n-type 6H—SiC using nitrogen as an n-type dopant as an ion species 2. The conditions for the ion implantation are acceleration energy of 100 KeV and a dose of 5 × 10 15 / cm 2.
It is. Thereby, as shown in FIG. 2, the heavily doped layer 3 is formed around the peak value Ro = 0.25 μm of the projected range distribution. FIG. 6 shows that an ion implantation of nitrogen is performed on an n-type 6HSiC substrate under the same conditions as described above,
It is a measurement result of the spreading resistance after annealing at 1200 ° C. for 10 hours. As shown in the figure, the resistance value is Ro of nitrogen.
It shows a Gaussian distribution centered around 0.25 μm and a depth of 0.2.
The resistance sharply drops at the position of 27 to 0.29 μm.
This indicates that the implanted nitrogen hardly diffuses and forms a low-resistance high-concentration layer in situ. Therefore, the sample was oxidized from the surface to the depth of the peak value Ro of the projected range distribution by steam oxidation at 1200 ° C. for 3 hours and 35 minutes. As a result, as shown in FIG. 3, the surface of the substrate 1 was covered with the oxide film 4 having a thickness of 0.49 μm. Wet oxidation such as steam oxidation is suitable for SiC having a slow oxidation rate. The SiC to be oxidized is 0.54 per volume 1 of the oxide film. Thereafter, the oxide film was removed using an etching solution obtained by diluting hydrofluoric acid with water at a volume ratio of 20 times. As a result, as shown in FIG. 4, the low-resistance high-concentration doped layer 3 was exposed. The surface of this highly doped layer 3 was smooth. Next, as shown in FIG. 5, the metal electrode 5 was brought into contact with the highly doped layer 3 using Ni as an electrode material. This electrode exhibited a lower Rc by about 40% or more than an electrode directly attached on n-type 6H-SiC. However, the oxide film 4
Was removed by dry etching, the surface of the highly doped layer 3 became uneven, and a low Rc was not obtained.
【0008】基板がp形SiCよりなるときは、イオン
種2にアルミニウムを用いる。スチーム酸化の時間は、
イオン注入するドーパントの射影飛程により異なる。な
お、金属電極5の材料としては、Ni以外の金属材料を
用いることもできる。[0008] When the substrate is made of p-type SiC, aluminum is used as the ion species 2. Steam oxidation time is
It depends on the projection range of the dopant to be ion-implanted. In addition, as the material of the metal electrode 5, a metal material other than Ni can be used.
【0009】[0009]
【発明の効果】本発明によれば、SiC基体の表面から
基体と同一導電形のドーパントをイオン種としてイオン
注入したのち、そのピーク濃度の深さまでを熱酸化とエ
ッチングの組み合わせで除去して高キャリア濃度の層を
表面に露出させる。従って、この表面に金属電極を形成
すれば、基体自体は低キャリア濃度でもオーム性接触と
なり、良質のSiC結晶を用いた半導体素子の製造が可
能になった。According to the present invention, a dopant having the same conductivity type as that of the substrate is ion-implanted from the surface of the SiC substrate as an ion species, and then the depth of the peak concentration is removed by a combination of thermal oxidation and etching to achieve a high concentration. The carrier concentration layer is exposed on the surface. Therefore, if a metal electrode is formed on this surface, the substrate itself will be in ohmic contact even at a low carrier concentration, and it has become possible to manufacture a semiconductor device using high quality SiC crystals.
【図1】本発明の一実施例におけるイオン注入時のSi
C基板の断面図FIG. 1 shows an example of Si during ion implantation according to an embodiment of the present invention.
Cross section of C board
【図2】図1のイオン注入後のSiC基板の断面図FIG. 2 is a cross-sectional view of the SiC substrate after the ion implantation of FIG.
【図3】図2につづく熱酸化後のSiC基板の断面図FIG. 3 is a sectional view of the SiC substrate after thermal oxidation, following FIG. 2;
【図4】図3につづく酸化膜除去後のSiC基板の断面
図FIG. 4 is a sectional view of the SiC substrate after the removal of the oxide film, following FIG. 3;
【図5】図4につづく金属電極形成後のSiC基板の断
面図FIG. 5 is a sectional view of the SiC substrate after the formation of the metal electrode, following FIG. 4;
【図6】窒素イオンアニール後のSiC基板の深さ方向
における拡がり抵抗分布図FIG. 6 is a diagram showing a spreading resistance distribution in the depth direction of the SiC substrate after nitrogen ion annealing.
【符号の説明】 1 SiC基板 2 イオン種 3 高濃度ドープ層 4 酸化膜 5 金属電極[Description of Signs] 1 SiC substrate 2 ion species 3 highly doped layer 4 oxide film 5 metal electrode
フロントページの続き (56)参考文献 特開 昭64−33925(JP,A) 特開 昭59−145539(JP,A) 特開 昭56−67966(JP,A) 特開 平2−196421(JP,A) 特開 昭47−9415(JP,A) 特開 平8−64802(JP,A) 特開 平5−90206(JP,A) 特開 昭57−207372(JP,A) 特開 平5−90280(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 21/28 301 H01L 29/161 Continuation of the front page (56) References JP-A-64-33925 (JP, A) JP-A-59-145539 (JP, A) JP-A-56-67966 (JP, A) JP-A-2-196421 (JP) JP-A-47-9415 (JP, A) JP-A-8-64802 (JP, A) JP-A-5-90206 (JP, A) JP-A-57-207372 (JP, A) 5-90280 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21/28 301 H01L 29/161
Claims (3)
ら同一導電形化するドーパントをイオン種としてイオン
注入し、次いで前記一面の表面層を熱酸化し、生じた酸
化層を除去したのち、露出した基体面に金属電極を被着
してオーム性接触電極を形成する工程において、前記熱
酸化が、基体表面からイオン注入するイオン種の濃度が
ピーク値にある深さまで熱酸化することを特徴とする炭
化けい素半導体素子の製造方法。An ion implantation of a dopant having the same conductivity type is performed from one surface of a silicon carbide semiconductor substrate of one conductivity type as an ion species, and then the surface layer of the one surface is thermally oxidized to remove the generated oxide layer. , a metal electrode on the exposed substrate surface in the step of forming the ohmic contact electrode by adhering, the heat
Oxidation reduces the concentration of ion species implanted from the substrate surface.
A method for producing a silicon carbide semiconductor device, comprising thermally oxidizing to a depth at a peak value .
炭化けい素半導体素子の製造方法。2. A method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the thermal oxidation is performed in steam oxidation.
項1あるいは請求項2記載の炭化けい素半導体素子の製
造方法。3. The method for producing a silicon carbide semiconductor device according to claim 1 or claim 2, wherein an aqueous solution of hydrofluoric acid to remove the oxide layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14133794A JP3303530B2 (en) | 1994-06-23 | 1994-06-23 | Method for manufacturing silicon carbide semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14133794A JP3303530B2 (en) | 1994-06-23 | 1994-06-23 | Method for manufacturing silicon carbide semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH088210A JPH088210A (en) | 1996-01-12 |
JP3303530B2 true JP3303530B2 (en) | 2002-07-22 |
Family
ID=15289615
Family Applications (1)
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JP14133794A Expired - Lifetime JP3303530B2 (en) | 1994-06-23 | 1994-06-23 | Method for manufacturing silicon carbide semiconductor device |
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JP (1) | JP3303530B2 (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
MXPA01002751A (en) * | 1998-09-16 | 2002-04-08 | Cree Inc | Low temperature formation of backside ohmic contacts for vertical devices. |
JP5282382B2 (en) | 2007-08-17 | 2013-09-04 | 富士電機株式会社 | Silicon carbide semiconductor device, manufacturing method thereof, and silicon carbide device |
JP6018501B2 (en) * | 2012-12-27 | 2016-11-02 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
JP6183200B2 (en) | 2013-12-16 | 2017-08-23 | 住友電気工業株式会社 | Silicon carbide semiconductor device and manufacturing method thereof |
JP6208106B2 (en) | 2014-09-19 | 2017-10-04 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
JP6441412B2 (en) * | 2017-05-30 | 2018-12-19 | 株式会社東芝 | Semiconductor device |
-
1994
- 1994-06-23 JP JP14133794A patent/JP3303530B2/en not_active Expired - Lifetime
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