JP2595676B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device such as an integrated circuit element provided with a means for preventing over-etching. When an internal circuit is formed, the etching method is switched and fine adjustment is made near the etching end point. The object of the present invention is to provide a method of manufacturing a semiconductor device which does not require the trouble of performing etching while performing etching, and which does not cause a defect in the function as an element even if it cannot be etched to a desired etching depth. A second impurity which is made of the same semiconductor polycrystal as the first semiconductor layer and has a conductivity type impurity lower than the first impurity concentration on a surface of the first semiconductor layer containing the conductivity type impurity at the first impurity concentration. Forming a second semiconductor layer containing at a concentration, forming an insulating layer on the surface of the second semiconductor layer; Forming a mask having an opening in a region on the second semiconductor layer; and etching and removing a portion of the insulating layer exposed by the opening in the mask until the second semiconductor layer is exposed. ,
After the second semiconductor layer is exposed, adding the conductivity type impurity to the second semiconductor layer so that the second semiconductor layer has an impurity concentration substantially equal to that of the first semiconductor layer. Configure.

[Industrial applications]

The present invention relates to a method for manufacturing a semiconductor device such as an integrated circuit element which is provided with a means for preventing over-etching.

Conventionally, the etching method employed when forming an internal circuit of a semiconductor element, particularly an integrated circuit element such as an IC or LSI, has many problems accompanied by an etching stop control in a step of opening an electrode window in an ion implantation region. In the ion implantation region, the etch rate tends to be high. The reason for this is that the orderly arrangement of the original crystal lattice is disturbed in the ion-implanted semiconductor layer, so that the strength of the crystal itself is reduced and the semiconductor layer is easily broken with weak energy. For this reason, if over-etching is performed too much, the ion-implanted region will be scrambled, resulting in an increase in the layer resistance.

In other words, there is a problem that the first semiconductor layer does not function as rated, which must be provided as an element. Therefore, means for preventing such a situation is required.

[Conventional technology]

As means for preventing such a situation from occurring, a method using a so-called "etch stopper" is widely known.

Hereinafter, this method will be described with reference to FIG.

This method uses a semiconductor substrate 1 made of Si (silicon) or the like.
After the first semiconductor layer 10 (polycrystalline silicon) is formed on the surface, a layer whose etching rate is significantly reduced, that is, an etch stopper 20 is formed on the surface of the first semiconductor layer 10 by forming a nitride film or the like. is there.

By providing the etch stopper 20, it is possible to obtain time to instruct to stop the etching,
As shown in (a), the removal of the oxide film (SiO ₂ ) 31 is advanced,
(B), the etching stopper 20 is reached. Next, the etching is temporarily stopped when it is recognized that the etching stopper 20 has been reached, that is, at the time shown in (c). Thereafter, as shown in (d), the gas is switched little by little in an attempt to stop the etching at the surface of the first semiconductor layer (polycrystalline silicon) 10 accurately. This is a method for avoiding a situation that has conventionally occurred such that even a certain first semiconductor layer (polycrystalline silicon) 10 is removed.

[Problems to be solved by the invention]

However, in this method, while the etch stopper 20 is made of a nitride film, the first semiconductor layer 10 is made of polycrystalline silicon, and both are made of different materials. For this reason, in order to function as an element, it is necessary to remove all of the nitride film forming the etching stopper 20.

Moreover, if the etching reaches the first semiconductor layer 10, there is a problem of overetching.

In other words, the problem is that in the conventional etching method using an etch stopper, the etching must be stopped accurately at the boundary surface between the etch stopper and the semiconductor layer under the etch stopper. In FIG. 3C, the etching must be advanced with the etching rate reduced. As a result, great waste must be paid in terms of work efficiency.

The present invention has been made in view of the above-described problems of the conventional etch stopper, and takes care of switching the etching method when forming an internal circuit and performing the etching while performing fine adjustment near the etching end point. It is an object of the present invention to provide a method for manufacturing a semiconductor device which does not cause a defect in its function as an element even if it cannot be etched to a desired etching depth.

[Means for solving the problem]

In order to solve the above-described problems, a method for manufacturing a semiconductor device according to the present invention provides a method for manufacturing a semiconductor device, comprising the steps of: providing a first semiconductor layer surface containing a conductive impurity at a first impurity concentration;
Forming a second semiconductor layer made of polycrystal of the same semiconductor as the semiconductor layer and containing the conductivity type impurity at a second impurity concentration lower than the first impurity concentration; and forming an insulating layer on the surface of the second semiconductor layer. Forming a layer, forming a mask having an opening in a region on the second semiconductor layer on the surface of the insulating layer, and exposing the opening of the mask in the insulating layer. Etching the portion until the second semiconductor layer is exposed; and removing the second semiconductor layer after the second semiconductor layer is exposed such that the second semiconductor layer has an impurity concentration substantially equal to that of the first semiconductor layer. Adding the conductive impurity to the semiconductor layer.

[Action]

In the present invention, as shown in FIG. 1, a second semiconductor layer 2 made of the same semiconductor polycrystal as the semiconductor substrate 1 is formed, and functions as a means for delaying the etching as in the conventional etch stopper.

 Hereinafter, this will be described in detail.

The second semiconductor layer 2 has no addition of conductive impurities. In addition, since the second semiconductor layer 2 is made of polycrystal which can be formed at a relatively low temperature, diffusion of impurities from the first semiconductor layer 10 is minimized.

As described above, since the conductivity type impurities are not added to the second semiconductor layer 2, the bonding of atoms is not disturbed by the impurity ions, and the arrangement of the crystal lattice remains orderly. That is, the semiconductor layer without the addition of the conductive impurity becomes stronger than the state where the impurity is added. In other words, it will not break unless you give it strong energy.

Therefore, the layer to which the conductivity type impurity is not added (the second semiconductor layer 2) is a layer to which the conductivity type impurity is added (the first semiconductor layer 2).
The progress of the etching is slower than in 10), and it functions as an etch stopper.

Further, the second semiconductor layer 2 is finally doped with an impurity and becomes equal to the first semiconductor layer 10.
It is not necessary to completely remove the semiconductor layer 2. Second
In order to obtain an etch stopper function, the thickness of the semiconductor layer 2 itself may be as thin as, for example, 500 to 1000 °. Then, a portion of the second semiconductor layer 2 that remains without being etched is
At most a few hundred square meters. Therefore, for example, as an electrode
When Al (aluminum) is formed in the opening, the electrical resistance value does not increase, and the portion of the second semiconductor layer 2 that remains without being etched may affect the rating as an element. Absent. Therefore, the etching is
The stop may be performed before reaching the interface between the semiconductor layer 2 and the first semiconductor layer 10.

From the above, the layer forming the etch stopper and the first semiconductor layer 10
The conventional difficulty that the etching must be stopped accurately at the interface with the substrate is completely eliminated.

〔Example〕

(A) Description of First Embodiment Hereinafter, a first embodiment of the present invention will be described with reference to FIG. 2 showing a cross section of a main part of a semiconductor device in each step along a manufacturing process of the present invention. explain.

FIG. 2 shows a portion to be a resistance element of an IC circuit, and RIE (reactive ion etching) is applied as an etching method.

In FIG. 2, the same reference numerals as in FIG. 1 denote the same as those in FIG. 1, 1 is a semiconductor substrate, which is made of single-crystal silicon, and 10 is 1 a semiconductor layer in which B ⁺ (boron ion) is implanted as impurity ions 5 into a layer made of polycrystalline silicon; 2
Denotes a second semiconductor layer, which is made of polycrystalline silicon, is etched in a state where it does not contain a conductive impurity, and thereafter is doped with impurity ions so as to have an impurity concentration similar to that of the first semiconductor layer 10. An insulating layer, the surface of the semiconductor substrate 1 is made of SiO ₂ (silicon dioxide) by means of thermal oxidation or the like.
It is what it was. Reference numerals 41 and 42 are photoresists.

First, the semiconductor substrate 1 made of silicon shown in FIG.
An oxide film 3 made of SiO ₂ (silicon dioxide) is formed at a uniform depth by thermally oxidizing the surface.

Next, a polycrystalline silicon layer is uniformly formed on the surface of the oxide film 3 by 67.
Vapor phase growth is performed at 0 ° C to 860 ° C. A nitride film (Si ₃ N ₄ ) is entirely formed on the surface of the polycrystalline silicon layer by vapor phase growth. The portion of the nitride film (Si ₃ N ₄ ) other than the portion corresponding to the element region is removed by etching. This substrate surface is thermally oxidized to form SiO ₂ (silicon dioxide) on the surface of the oxide film 3 other than the element region. After this, the whole board
The nitride film (Si ₃ N ₄ ) is removed by placing it in an H ₃ PO ₄ (phosphoric acid) solution heated to about 80 ° C. The oxide film 3 is uniformly formed on the surface of the semiconductor substrate 1 other than the surface to function as an element.

On the surface of the substrate thus formed, a photoresist having a hole at a portion to function as an element was used as a photoresist.
Form 41.

Next, impurity ions 5 are incident and implanted on the substrate surface. The concentration of the impurity added in this manner is about 10 ¹⁶ cm ⁻³ .

Thereafter, the photoresist 41 is removed by etching with O ₂ (oxygen) plasma.

As described above, the first semiconductor layer 10 contains the impurities of the conductivity type, and a substrate as an element can be formed.

Next, in the step of FIG. 2B, in order to form the second semiconductor layer 2, polycrystalline silicon is deposited at about 670 ° C. to 680 ° C.
Vapor growth to a thickness of 0 to 2000 mm.

The reason why silicon is used as a polycrystalline material for the second semiconductor layer 2 is that the first semiconductor layer 10 into which the conductivity type impurity has already been implanted in the previous step (a) is used because vapor phase growth can be performed at a low temperature.
This is because the diffusion of the conductive impurity from the second into the second semiconductor layer 2 can be reduced.

In the step of FIG. 2 (c), an oxide film 31 is formed on the substrate surface formed in the step (b). First, of the second semiconductor layer 2 already formed on the entire surface of the substrate, other portions are removed except for desired portions, and thereafter, an oxide film 31 is entirely formed on the surface.

The oxide film 31 is a chemical vapor deposition silicon oxide film, and is formed as SiO ₂ (silicon dioxide) by vapor phase growth at a low temperature (800 ° C. or lower).

In the step of FIG. 2D, the oxide film 31 on the substrate surface formed in the step (c) is etched. In this step, first, a photoresist is formed on a portion other than a desired portion of the surface of the oxide film 31. Next, even if the etching process is performed, the etching operation is stopped before reaching the boundary between the second semiconductor layer 2 and the first semiconductor layer 10.

In the step shown in FIG. 2E, the second semiconductor layer 2 containing no conductive impurity contains the same impurity as the first semiconductor layer 10 in the same concentration as in the step (a).
In the same manner as described above, impurity ions (B ⁺ ) 5 are implanted into the second semiconductor layer 2.

In the steps up to (e), since the impurity diffusion is not uniform according to the depth, the added conductivity type impurity is uniformly diffused. Therefore, heat treatment of the substrate (800-900
C.) to diffuse the conductive impurities uniformly into the second semiconductor layer 2 and activate the dynamic layer 2 second.

FIG. 3 is a perspective view of the resistance element formed through the above steps. The cross section in FIG. 3 corresponds to the cross section shown in FIG.

If an electrode is formed of Al (aluminum) or the like in the electrode forming region 8 in FIG. 3, the space between both electrodes can be used as a resistance element.

At this time, the etching does not reach the first semiconductor layer 10 as in the related art, and the electric resistance value does not unexpectedly increase. For example, the first impurity concentration of about 10 ¹⁵ cm ^-3
When the impurity concentration of the second semiconductor layer 2 formed on the surface of the semiconductor layer 10 is about 10 ¹³ cm ⁻³ , the etching rate of the second semiconductor layer is about half that of the first semiconductor layer. About.

With the above configuration, the problem of the conventional method is completely solved. In addition, the greatest advantage of the conventional etch stopper that it is possible to avoid a situation where a region that should not be etched is avoided can be avoided without any loss.

(B) Description of the Second Embodiment By the way, in the above-described embodiment, the description has been given by taking the part which becomes the resistance element of the IC circuit. Can be expected.

As an example, a part to be a bipolar transistor of an IC circuit is taken, and a cross-sectional view of a main part for each process is shown in FIG. 4 as in the previous embodiment.

4, reference numeral 101 denotes a boron-doped p-type first semiconductor layer; 102, an arsenic-doped n-type first semiconductor layer; 51, an impurity ion (As ⁺ ); The same thing shows the same thing as FIG.

Now, each step in the drawing corresponds to the step in FIG. 2 and is almost the same.

In (a), first, of the two etched regions in the cross section of the drawing, the region on the left side of the drawing contains impurity ions (B ⁺ ).
5 is implanted to form a boron-doped p-type first semiconductor layer 101. On the other hand, the region on the right side of the drawing contains impurity ions (A
s ⁺ ) 51 is implanted to form an arsenic-doped n-type first semiconductor layer 102.

Thereafter, the second semiconductor layer 2 is formed in the step (b),
The oxide film 31 is etched in the step (c) (the same procedure as in the embodiment of FIG. 2 is performed), and the process proceeds to the step (e).

(E) of the drawing illustrates a step of implanting a conductive impurity into the second semiconductor layer 2 which has functioned as an etch stopper in the step (d).

In this step, a boron-doped p-type first semiconductor layer is formed in the base formation region (the left side region in FIG. 4 of the second semiconductor layer 2 containing no conductivity type impurity).
At the same concentration as 101, the arsenic-doped n-type first semiconductor layer 102 is formed in the collector forming region (the right region in FIG. 4).
Impurity ions (As ⁺ ) 51 are implanted so as to contain the conductivity type impurity at the same concentration as the above. The impurity concentration of the base layer is 1
0 ¹⁵ cm ^-3 and the impurity concentration of the collector layer is 10 ¹⁷ cm
It is about ^-3 . On the other hand, the emitter formation region (in FIG. 4,
Impurity ion (As ⁺ ) 51 to the left side (before the paper)
Is implanted so as to reach the lower layer of the second semiconductor layer 2 and a new arsenic-doped n-type first semiconductor layer 102 is formed.
To form The impurity concentration of this layer is about 10 ¹⁷ cm ⁻³ .

In this way, the second semiconductor layer 2 functioning as an etch stopper becomes the same semiconductor layer as the lower layer in portions where each of the base, the collector and the emitter should function.

Thereafter, as in the second embodiment, the process proceeds to the step of uniformly diffusing the added conductivity type impurities. The bottom surface of the semiconductor substrate is heated at 900 ° C. for 30 minutes.

The base of what was made through the process described above,
Al (aluminum) for each of the collector and emitter regions
If the electrode is formed of such a metal, a function as a bipolar transistor can be obtained.

In the second embodiment, similarly to the embodiment of FIG. 2, the electric resistance value does not unexpectedly increase. As an effect spread from this, the operating speed of the transistor can be increased because the emitter resistance and the base resistance are not increased.

It is preferable that the second semiconductor layer 2 does not contain an impurity. In the case of the first embodiment, the second semiconductor layer 10 has an impurity concentration of 10 ¹⁶ cm ⁻³ , whereas the second semiconductor layer 2 has an impurity concentration of 10 ¹⁶ cm ⁻³ . Even if the semiconductor layer 22 contained an impurity concentration of about 10 ¹⁴ cm ⁻³ , it did not hinder the function as an etch stopper.

It is to be noted that, of course, effects such as elimination of troublesome steps can be obtained for a portion having another function as an element, and the present invention does not exclude these effects.
Alternatively, the type of ion to be added as a conductive impurity is not limited to As ⁺ (arsenic ion).
Other ions such as ⁺ (phosphorus ion) can also be used.
In addition, various layers are stacked in each step. In the formation of these layers, diffusion is performed in the embodiment, but they can also be obtained by vapor phase growth.

〔The invention's effect〕

In the present invention, as shown in FIG. 1, the second semiconductor layer 2 is formed so that the surface of the portion to be etched of the first semiconductor layer 10 does not contain impurities. The layer to which the conductive impurity is not added (the second semiconductor layer 2) is less likely to be etched than the layer to which the conductive impurity is added (the first semiconductor layer 10).

In addition, since the conductive type impurities are included after the etching to have the same composition as the first semiconductor layer 10,
Eventually, the second semiconductor layer 2 has the same function as the first semiconductor layer 10.

Therefore, the etching depth reaches the second semiconductor layer 2 provided as an etch stopper after the etching of the oxide film 31 is completed, as in the related art, so that the etching ends at the second semiconductor layer 2 and the first semiconductor layer 2. Knowing that the boundary with the layer 10 has been considerably approached, there is no need to reduce the etching speed. Further, according to the present invention, since the second semiconductor layer 2 is finally the same as the first semiconductor layer 10, there is no need to completely remove the second semiconductor layer 2 serving as an etch stopper. .

The present invention is characterized in that the conventionally known method completely eliminates the difficulty that etching must be stopped accurately at the interface between the layer forming the etch stopper and the first semiconductor layer 10, which was an essential requirement. According to the method of the present invention, the etching speed is reduced by trying to stop the etching accurately at the boundary surface, so that time is not wasted, the work efficiency is improved, and the element performance itself is improved. You will get benefits such as improved reliability.

[Brief description of the drawings]

1 is a sectional view of a main part of a semiconductor device according to the present invention, FIG. 2 is a process explanatory view (cross-sectional view) according to the first embodiment of the present invention, and FIG. 3 is a first embodiment of the present invention. FIG. 4 is an explanatory view (perspective view) of a resistive element completed from FIG. 4, FIG. 4 is an explanatory view (cross-sectional view) of a process according to a second embodiment of the present invention, and FIG. 5 is an explanatory view (cross-sectional view) of a conventional etch stopper. ). In the figure, reference numeral 1 denotes a semiconductor substrate 10, a first semiconductor layer (polycrystalline Si) 101, a boron-doped p-type first semiconductor layer 102, an arsenic-doped n-type first semiconductor layer 2, a second semiconductor layer (Polycrystalline Si) 20, etch stopper (nitride film) 3, insulating layer (oxide film) (SiO ₂ ) 31, insulating layer (oxide film) (SiO ₂ ) 4, mask 41, photoresist 42 Is a photoresist 5, an impurity ion (B ⁺ ) 51 is an impurity ion (As ⁺ ) 8 is an electrode formation region.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical indication H01L 29/73

Claims (1)

(57) [Claims] 1. A method according to claim 1, wherein the surface of the semiconductor substrate has a first impurity concentration containing a conductive impurity at a first impurity concentration.
The first semiconductor layer (10) is made of the same semiconductor polycrystal;
Forming a second semiconductor layer (2) containing the conductivity type impurity at a second impurity concentration lower than the first impurity concentration; and forming an insulating layer (31) on the surface of the second semiconductor layer (2). Forming a mask (4) having an opening in a region on the second semiconductor layer (2) on the surface of the insulating layer (31); Etching away the portion of the mask (4) exposed by the opening until the second semiconductor layer (2) is exposed; and, after exposing the second semiconductor layer (2), the second semiconductor layer ( 2) adding the conductive impurity to the second semiconductor layer (2) so that the second semiconductor layer (2) has an impurity concentration substantially equal to that of the first semiconductor layer (10).