EP1105844A1 - Graphics processor with deferred shading - Google Patents

Graphics processor with deferred shading

Info

Publication number
EP1105844A1
EP1105844A1 EP99943867A EP99943867A EP1105844A1 EP 1105844 A1 EP1105844 A1 EP 1105844A1 EP 99943867 A EP99943867 A EP 99943867A EP 99943867 A EP99943867 A EP 99943867A EP 1105844 A1 EP1105844 A1 EP 1105844A1
Authority
EP
European Patent Office
Prior art keywords
unit
texture
primitive
pixel
block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99943867A
Other languages
German (de)
English (en)
French (fr)
Inventor
Jerome F. Duluk, Jr.
Richard E. Hessel
Vaughn T. Arnold
Jack Benkual
Joseph P. Bratt
George Cuan
Steven L. Dodgen
Emerson S. Fang
Zhaoyu G. Gong
Thomas Y. Ho
Hengwei Hsu
Sidong Li
Sam Ng
Matthew N. Papakipos
Jason R. Redgrave
Sushma S. Trivedi
Nathan D. Tuck
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Apple Inc
Original Assignee
Apple Computer Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Apple Computer Inc filed Critical Apple Computer Inc
Publication of EP1105844A1 publication Critical patent/EP1105844A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/003D [Three Dimensional] image rendering
    • G06T15/50Lighting effects
    • G06T15/80Shading
    • G06T15/87Gouraud shading
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/003D [Three Dimensional] image rendering
    • G06T15/10Geometric effects
    • G06T15/30Clipping
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00General purpose image data processing
    • G06T1/20Processor architectures; Processor configuration, e.g. pipelining
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T11/002D [Two Dimensional] image generation
    • G06T11/40Filling a planar surface by adding surface attributes, e.g. colour or texture
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/003D [Three Dimensional] image rendering
    • G06T15/005General purpose rendering architectures
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/003D [Three Dimensional] image rendering
    • G06T15/04Texture mapping
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/003D [Three Dimensional] image rendering
    • G06T15/10Geometric effects
    • G06T15/20Perspective computation
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/003D [Three Dimensional] image rendering
    • G06T15/10Geometric effects
    • G06T15/40Hidden part removal
    • G06T15/405Hidden part removal using Z-buffer
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/003D [Three Dimensional] image rendering
    • G06T15/50Lighting effects
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/003D [Three Dimensional] image rendering
    • G06T15/50Lighting effects
    • G06T15/80Shading
    • G06T15/83Phong shading

Definitions

  • This invention relates to computing systems generally, to three-dimensional computer graphics, more particularly, and more most particularly to structure and method for a three- dimensional graphics processor implementing differed shading and other enhanced features.
  • Computer graphics is the art and science of generating pictures with a computer. Generation of pictures, or images, is commonly called rendering.
  • rendering Generally, in three-dimensional (3D) computer graphics, geometry that represents surfaces (or volumes) of objects in a scene is translated into pixels stored in a frame buffer, and then displayed on a display device.
  • Real-time display devices such as CRTs used as computer monitors, refresh the display by continuously displaying the image over and over. This refresh usually occurs row-by-row, where each row is called a raster line or scan line. In this document, raster lines are numbered from bottom to top, but are displayed in order from top to bottom.
  • each renderable object In a 3D animation, a sequence of images is displayed, giving the illusion of motion in three-dimensional space.
  • Interactive 3D computer graphics allows a user to change his viewpoint or change the geometry in real-time, thereby requiring the rendering system to create new images on-the-fly in real-time.
  • each renderable object generally has its own local object coordinate system, and therefore needs to be translated (or transformed) from object coordinates to pixel display coordinates.
  • this is a 4-step process: 1 ) translation (including scaling for size enlargement or shrink) from object coordinates to world coordinates, which is the coordinate system for the entire scene; 2) translation from world coordinates to eye coordinates, based on the viewing point of the scene; 3) translation from eye coordinates to perspective translated eye coordinates, where perspective scaling (farther objects appear smaller) has been performed; and 4) translation from perspective translated eye coordinates to pixel coordinates, also called screen coordinates.
  • Screen coordinates are points in three-dimensional space, and can be in either screen-precision (i.e., pixels) or object-precision (high precision numbers, usually floating-point), as described later.
  • the geometry is in screen coordinates, it is broken into a set of pixel color values (that is "rasterized") that are stored into the frame buffer.
  • pixel color values that is "rasterized"
  • Many techniques are used for generating pixel color values, including Gouraud shading, Phong shading, and texture mapping.
  • Figure 1 shows a three-dimensional object, a tetrahedron, with its own coordinate axes
  • the geometry representing the surfaces closest to the scene viewing point must be determined.
  • the visible surfaces within the volume subtended by the pixel's area determine the pixel color value, while hidden surfaces are prevented from affecting the pixel.
  • Non-opaque surfaces closer to the viewing point than the closest opaque surface (or surfaces, if an edge of geometry crosses the pixel area) affect the pixel color value, while all other non-opaque surfaces are discarded.
  • the term "occluded" is used to describe geometry which is hidden by other non- opaque geometry.
  • the depth complexity of a scene is a measure of the wasted processing. For example, for a scene with a depth complexity of ten, 90% of the computation is wasted on hidden pixels.
  • This wasted computation is typical of hardware renderers that use the simple Z-buffer technique (discussed later herein), generally chosen because it is easily built in hardware. Methods more complicated than the Z Buffer technique have heretofore generally been too complex to build in a cost-effective manner.
  • An important feature of the method and apparatus invention presented here is the avoidance of this wasted computation by eliminating hidden portions of geometry before they are rasterized, while still being simple enough to build in cost- effective hardware.
  • the point When a point on a surface (frequently a polygon vertex) is translated to screen coordinates, the point has three coordinates: 1) the x-coordinate in pixel units (generally including a fraction); 2) the y-coordinate in pixel units (generally including a fraction); and 3) the z-coordinate of the point in either eye coordinates, distance from the virtual screen, or some other coordinate system which preserves the relative distance of surfaces from the viewing point.
  • positive z-coordinate values are used for the "look direction" from the viewing point, and smaller values indicate a position closer to the viewing point.
  • a surface is approximated by a set of planar polygons
  • the vertices of each polygon are translated to screen coordinates.
  • the screen coordinates are interpolated from the coordinates of vertices, typically by the processes of edge walking and span interpolation.
  • a z-coordinate value is generally included in each pixel value (along with the color value) as geometry is rendered.
  • the Deering Reference includes a diagram of a generic 3D graphics pipeline (i.e., a renderer, or a rendering system) that it describes as "truly generic, as at the top level nearly every commercial 3D graphics accelerator fits this abstraction", and this pipeline diagram is reproduced here as Figure 2.
  • Such pipeline diagrams convey the process of rendering, but do not describe any particular hardware.
  • This document presents a new graphics pipeline that shares some of the steps of the generic 3D graphics pipeline.
  • the first step within the floating-point intensive functions of the generic 3D graphics pipeline after the data input is the transformation step (Step 214), which was described above.
  • the transformation step is also shown in Figure 3 as the first step in the outer loop of the method flow diagram, and also includes "get next polygon".
  • the second step, the clip test checks the polygon to see if it is at least partially contained in the view volume
  • the third step is face determination, where polygons facing away from the viewing point are discarded (Step 218). Generally, face determination is applied only to objects that are closed volumes.
  • the fourth step, lighting computation generally includes the set up for Gouraud shading and/or texture mapping with multiple light sources of various types, but could also be set up for Phong shading or one of many other choices (Step 222).
  • the fifth step, clipping deletes any portion of the polygon that is outside of the view volume because that portion would not project within the rectangular area of the viewing plane (Step 224).
  • polygon clipping is done by splitting the polygon into two smaller polygons that both project within the area of the viewing plane. Polygon clipping is computationally expensive.
  • the sixth step, perspective divide does perspective correction for the projection of objects onto the viewing plane (Step 226). At this point, the points representing vertices of polygons are converted to pixel space coordinates by step seven, the screen space conversion step (Step 228).
  • RGB color texture map space u and v-coordinates; and the like).
  • edge walking incrementally generates horizontal spans for each raster line of the display device by incrementing values from the previously generated span (in the same polygon), thereby "walking" vertically along opposite edges of the polygon.
  • span interpolation Step 2344 "walks" horizontally along a span to generate pixel values, including a z-coordinate value indicating the pixel's distance from the viewing point.
  • the z-buffered blending also referred to as Testing and Blending (Step 236) generates a final pixel color value.
  • the pixel values also include color values, which can be generated by simple Gouraud shading (i.e., interpolation of vertex color values) or by more computationally expensive techniques such as texture mapping (possibly using multiple texture maps blended together), Phong shading (i.e., per-fragment lighting), and/or bump mapping (perturbing the interpolated surface normal).
  • texture mapping possibly using multiple texture maps blended together
  • Phong shading i.e., per-fragment lighting
  • bump mapping perturbing the interpolated surface normal.
  • the z-buffered blend By comparing the generated z-coordinate value to the corresponding value stored in the Z Buffer, the z-buffered blend either keeps the new pixel values (if it is closer to the viewing point than previously stored value for that pixel location) by writing it into the frame buffer, or discards the new pixel values (if it is farther). At this step, antialiasing methods can blend the new pixel color with the old pixel color.
  • the z-buffered blend generally includes most of the per-fragment operations, described below.
  • the generic 3D graphics pipeline includes a double buffered frame buffer, so a double buffered MUX is also included. An output lookup table is included for translating color map values. Finally, digital to analog conversion makes an analog signal for input to the display device.
  • a major drawback to the generic 3D graphics pipeline is its drawing intensive functions are not deterministic at the pixel level given a fixed number of polygons. That is, given a fixed number of polygons, more pixel-level computation is required as the average polygon size increases.
  • the floating-point intensive functions are proportional to the number of polygons, and independent of the average polygon size. Therefore, it is difficult to balance the amount of computational power between the floating-point intensive functions and the drawing intensive functions because this balance depends on the average polygon size.
  • Prior art Z Buffers are based on conventional Random Access Memory (RAM or DRAM), Video RAM (VRAM), or special purpose DRAMs.
  • RAM Random Access Memory
  • VRAM Video RAM
  • special purpose DRAMs One example of a special purpose DRAM is presented in "FBRAM: A new Form of Memory Optimized for 3D Graphics", by Deering, Schlapp, and Lavelle, pages 167 to 174 of SIGGRAPH94 Proceedings, 24-29 July 1994, Computer
  • OpenGL is a software interface to graphics hardware which consists of several hundred functions and procedures that allow a programmer to specify objects and operations to produce graphical images.
  • the objects and operations include appropriate characteristics to produce color images of three-dimensional objects.
  • Most of OpenGL (Version 1.2) assumes or requires a that the graphics hardware include a frame buffer even though the object may be a point, line, polygon, or bitmap, and the operation may be an operation on that object.
  • the general features of OpenGL (just one example of a graphical interface) are described in the reference "The OpenGL ® Graphics System: A Specification (Version 1.2) edited by Mark Segal and Kurt Akeley, Version 1.2, March 1998; and hereby incorporated by reference.
  • the invention is not limited to structures, procedures, or methods which are compatible or consistent with OpenGL, or with any other standard or non-standard graphical interface.
  • the inventive structure and method may be implemented in a manner that is consistent with the OpenGL, or other standard graphical interface, so that a data set prepared for one of the standard interfaces may be processed by the inventive structure and method without modification.
  • the inventive structure and method provides some features not provided by OpenGL, and even when such generic input/output is provided, the implementation is provided in a different manner.
  • pipeline state does not have a single definition in the prior-art.
  • the OpenGL specification sets forth the type and amount of the graphics rendering machine or pipeline state in terms of items of state and the number of bits and bytes required to store that state information.
  • pipeline state tends to include object vertex pertinent information including for example, the vertices themselves the vertex normals, and color as well as "non-vertex" information.
  • object geometry information When information is sent into a graphics renderer, at least some object geometry information is provided to describe the scene.
  • the object or objects are specified in terms of vertex information, where an object is modeled, defined, or otherwise specified by points, lines, or polygons (object primitives) made up of one or more vertices.
  • a vertex In simple terms, a vertex is a location in space and may be specified for example by a three-space (x,y,z) coordinate relative to some reference origin.
  • Associated with each vertex is other information, such as a surface normal, color, texture, transparency, and the like information pertaining to the characteristics of the vertex. This information is essentially "per-vertex" information.
  • a color value may be specified in the data stream for a particular vertex and then not respecif ⁇ ed in the data stream until the color changes for a subsequent vertex.
  • the color value may still be characterized as per- vertex data even though a color value is not explicitly included in the incoming data stream for each vertex.
  • Texture mapping presents an interesting example of information or data which could be considered as either per-vertex information or pipeline state information.
  • one or more texture maps may be specified, each texture map being identified in some manner, such as with a texture coordinate or coordinates.
  • pipeline state Other information, not related on a one-to-one basis to the geometry object primitives, used by the renderer such as lighting location and intensity, material settings, reflective properties, and other overall rules on which the renderer is operating may more accurately be referred to as pipeline state.
  • Parameters considered to be renderer (pipeline) state in OpenGL are identified in Section 6.2 of the afore referenced OpenGL Specification (Version 1.2, at pages 193-217).
  • APIs such as OpenGL (Open Graphics Library) and D3D
  • OpenGL Open Graphics Library
  • D3D D3D
  • a frame buffer stores a set of pixels as a two-dimensional array.
  • Each picture-element or pixel stored in the frame buffer is simply a set of some number of bits. The number of bits per pixel may vary depending on the particular GL implementation or context.
  • Corresponding bits from each pixel in the framebuffer are grouped together into a bitplane; each bitplane containing a single bit from each pixel.
  • the bitplanes are grouped into several logical buffers referred to as the color, depth, stencil, and accumulation buffers.
  • the color buffer in turn includes what is referred to under OpenGI as the front left buffer, the front right buffer, the back left buffer, the back right buffer, and some additional auxiliary buffers.
  • the values stored in the front buffers are the values typically displayed on a display monitor while the contents of the back buffers and auxiliary buffers are invisible and not displayed.
  • Stereoscopic contexts display both the front left and the front right buffers, while monoscopic contexts display only the front left buffer.
  • the color buffers must have the same number of bitplanes, but particular implementations of context may not provide right buffers, back buffers, or auxiliary buffers at all, and an implementation or context may additionally provide or not provide stencil, depth, or accumulation buffers.
  • the color buffers consist of either unsigned integer color indices or R, G, B, and, optionally, a number "A" of unsigned integer values; and the number of bitplanes in each of the color buffers, the depth buffer (if provided), the stencil buffer (if provided), and the accumulation buffer (if provided), is fixed and window dependent. If an accumulation buffer is provided, it should have at least as many bit planes per R, G, and B color component as do the color buffers.
  • a fragment produced by rasterization with window coordinates of (x,,, y w ) modifies the pixel in the framebuffer at that location based on a number of tests, parameters, and conditions.
  • the pixel ownership test determines if the pixel at location (x ⁇ y in the framebuffer is currently owned by the GL context. If it is not, the window system decides the fate of the incoming fragment. Possible results are that the fragment is discarded or that some subset of the subsequent per-fragment operations are applied to the fragment. This pixel ownership test allows the window system to properly control the GL's behavior.
  • the associated window defines the pixels the process wants to write or render to.
  • the window associated with one process may be in front of the window associated with another process, behind that window, or both windows may be entirely visible. Since there is only a single frame buffer for the entire display screen or desktop, the pixel ownership test involves determining which process and associated window owns each of the pixels. If a particular process does not "own" a pixel, it fails the pixel ownership test relative to the frame buffer and that pixel is thrown away.
  • the pixel ownership test is run by each process, and that for a give pixel location in the frame buffer, that pixel may pass the pixel ownership test for one of the processes, and fail the pixel ownership test for the other process.
  • a particular pixel can pass the ownership test for only one process because only one process can own a particular frame buffer pixel at the same time.
  • the pixel ownership test may not be particularly relevant. For example, if the scene is being rendered to an off-screen buffer, and subsequently Block Transferred or "blitted" to the desktop, pixel ownership is not really even relevant.
  • Each process automatically or necessarily passes the pixel ownership test (if it is executed) because each process effectively owns its own off-screen buffer and nothing is in front of that buffer.
  • the pixel is not owned by that process, then there is no need to write a pixel value to that location, and all subsequent processing for that pixel may be ignored.
  • all the data associated with a particular pixel on the screen is read during rasterization. All information for any polygon that feeds that pixel is read, including information as to the identity of the process that owns that frame buffer pixel, as well as the z-buffer, the color value, the old color value, the alpha value, stencil bits, and so forth.
  • a process owns the pixel, then the other downstream process are executed (for example, scissor test, alpha test, and the like) On the other hand, if the process does not own the pixel and fails the ownership test for that pixel, the process need not consider that pixel further and that pixel is skipped for subsequent tests.
  • the scissor test determines if (x ⁇ y w ) lies within a scissor rectangle defined by four coordinate values corresponding to a left bottom (left, bottom) coordinate, a width of the rectangle, and a height of the rectangle. The values are set with the procedure "void Scissor( int left, int bottom, sizei width, sizei height)" under OpenGL. If left ⁇ x w ⁇ left+width and bottom ⁇ y w ⁇ bottom+height, then the scissor test passes; otherwise the scissor test fails and the particular fragment being tested is discarded. Various initial states are provided and error conditions monitored and reported.
  • a rectangle defines a window which may be an on-screen or off-screen window.
  • the window is defined by an x-left, x-right, y-top, and y-bottom coordinate (even though it may be expressed in terms of a point and height and width dimensions from that point).
  • This scissor window is useful in that only pixels from a polygon fragment that fall in that screen aligned scissor window will change. In the event that a polygon straddles the scissor window, only those pixels that are inside the scissor window may change.
  • the pipeline calculates everything it needs to in order to determine the z-value and color of that pixel. Once z-value and color are determined, that information is used to determine what information should be placed in the frame buffer (thereby determining what is displayed on the display screen).
  • the scissor test provides means for discarding pixels and/or fragments before they actually get to the frame buffer to cause the output to change.
  • Color is defined by four values, red (R), green (G), blue (B), and alpha (A).
  • the RGB values define the contribution from each of the primary colors, and alpha is related to the transparency.
  • color is a 32-bit value, 8-bits for each component, though such representation is not limited to 32-bits.
  • Alpha test compares the alpha value of a given pixel to an alpha reference value. The type of comparison may also be specified, so that for example the comparison may be a greater-than operation, a less-than operation, and so forth. If the comparison is a greater-than operation, then the pixel's alpha value has to be greater than the reference to pass the alpha test.
  • Alpha test is a per-fragment operation and happens after all of the fragment coloring calculations and lighting and shading operations are completed. Each of these per-fragment operations may be though of as part of the conventional z-buffer blending operations.
  • Color test is similar to the alpha test described hereinbefore, except that rather than performing the magnitude or logical comparisons between the pixel alpha (A) value and a reference value, the color test performs a magnitude or logical comparison between one or a combination of the R, G, or B color components and reference value(s).
  • the comparison test may be for example, greater-than, less-than, equal-to, greater-than-or-equal-to, "greater-than-c , and less- than 0 2 " where c, and 0 2 are sore predetermined reference values, and so forth.
  • One might for example, specify a reference minimum R value, and a reference maximum R value, such that the color test would be passed only if the pixel R value is between that minimum and maximum.
  • Color test might, for example, be useful to provide blue-screen functionality.
  • the comparison test may also be performed on a single color component or on a combination of color components.
  • stencil test conditionally discards a fragment based on the outcome of a comparison between a value stored in a stencil buffer at location (xicide yj and a reference value.
  • Several stencil comparison functions are permitted such that the stencil test passes never, always, if the reference value is less than, less than or equal to, equal to, greater than or equal to, greater than, or not equal to the masked stored value in the stencil buffer.
  • the Under OpenGL if the stencil test fails, the incoming fragment is discarded.
  • the reference value and the comparison value can have multiple bits, typically 8 bits so that 256 different values may be represented.
  • a tag having the stencil bits is also written into the frame buffer. These stencil bits are part of the pipeline state.
  • the type of stencil test to perform can be specified at the time the geometry is rendered.
  • the stencil bits are used to implement various filtering, masking or stenciling operations.
  • the stencil bits can be written to the frame buffer along with the pixel information.
  • the depth buffer test discards the incoming fragment if a depth comparison fails.
  • the comparison is enabled or disabled with the generic Enable and Disable commands using the OpenGL symbolic constant DEPTH_TEST.
  • depth test is disabled, the depth comparison and subsequent possible updates to the depth buffer value are bypassed and a fragment is passed to the next operation.
  • the stencil bits are also involved and are modified even if the test is bypassed.
  • the stencil value is modified if the depth buffer test passed. If depth test is enabled, the depth comparison takes place and the depth buffer and stencil value may subsequently be modified. The manner in which the depth test is implemented in OpenGL is described in greater detail in the OpenGL specification at page 145.
  • Depth comparisons are implemented in which possible outcomes are as follows: the depth buffer test passes never, always, if the incoming fragment's z ⁇ value is less than, less than or equal to, equal to, greater than, greater than or equal to, or not equal to the depth value stored at the location given by the incoming fragment's (x ⁇ ,, y w ) coordinates. If the depth buffer test fails, the incoming fragment is discarded. The stencil value at the fragment's (x,,, y w ) coordinate is updated according to the function currently in effect for depth buffer test failure. Otherwise, the fragment continues to the next operation and the value of the depth buffer at the fragment's (x ⁇ y w ) location is set to the fragment's z w value. In this case the stencii value is updated according to the function currently in effect for depth buffer test success.
  • the necessary OpenGL state is an eight-valued integer and a single bit indicating whether depth buffering is enabled or disabled.
  • blending combines the incoming fragment's R, G, B, and A values with the R, G, B, and A values stored in the framebuffer at the incoming fragment's (X ⁇ Y location.
  • This blending is typically dependent on the incoming fragment's alpha value (A) and that of the corresponding frame buffer stored pixel.
  • A alpha value
  • Cs refers to the source color for an incoming fragment
  • Cd refers to the destination color at the corresponding framebuffer location
  • Cc refers to a constant color in-the GL state.
  • Individual RGBA components of these colors are denoted by subscripts of s, d, and c respectively.
  • Blending is basically an operation that takes color in the frame buffer and the color in the fragment, and blends them together.
  • the manner in which blending is achieved, that is the particular blending function, may be selected from various alternatives for both the source and destination.
  • Blending is described in the OpenGL specification at page 146-149 and is hereby incorporated by reference.
  • Various blend equations are available under OpenGL.
  • the blending equation is evaluated separately for each color component and its corresponding weighting coefficient.
  • Each of the four R, G, B, A components has its own weighting factor.
  • the blending test (or blending equation) is part of pipeline state and can potentially change for every polygon, but more typically would chang only for the object made up or several polygons. ln generally, blending is only performed once other tests such as the pixel ownership test and stencil test have been passed so that it is clear that the pixel or fragment under consideration would or could have an effect in the output.
  • dithering selects between two color values or indices.
  • RGBA mode consider the value of any of the color components as a fixed-point value with m bits to the left of the binary point, where m is the number of bits allocated to that component in the framebuffer; call each such value c.
  • dithering selects a value d such that d e ⁇ max ⁇ 0, [c]-1 , [c] ⁇ . This selection may depend on the x ⁇ , and y w coordinates of the pixel.
  • color index mode the same rule applies with c being a single color index. The value of c must not be larger than the maximum value representable in the framebuffer for either the component or the index.
  • each color component is truncated to a fixed-point value with as many bits as there are in the corresponding framebuffer component, and the color index is rounded to the nearest integer representable in the color index portion of the framebuffer.
  • pixels are referred to as the smallest individually controllable element of the display device.
  • spatial aliasing occurs.
  • a typical aliasing artifact is a "staircase" effect caused when a straight line or edge cuts diagonally across rows of pixels.
  • Some rendering systems reduce aliasing effects by dividing pixels into subpixels, where each sub-pixel can be colored independently. When the image is to be displayed, the colors for all sub-pixels within each pixel are blended together to form an average color for the pixel.
  • a renderer that uses up to 16 sub-pixels per pixel is described in "RealityEngine Graphics", by Akeley, pages 109 to 116 of SIGGRAPH93 Proceedings, 1 -6 August 1993, Computer Graphics
  • the A-buffer is an antialiasing technique that reduces aliasing by keeping track of the percent coverage of a pixel by a rendered polygon.
  • the main drawback to this technique is the need to sort polygons front-to-back (or back- to-front) at each pixel in order to get acceptable antialiased polygons.
  • CAM Content Addressable Memories
  • MCCAM Magnitude Comparison CAM
  • the basic internal structure of an MCCAM is a set of memory bits organized into words, where each word can perform one or more arithmetic magnitude comparisons between the stored data and input data.
  • each word can perform one or more arithmetic magnitude comparisons between the stored data and input data.
  • a parallel search comparison operation is called a "query" of the stored data.
  • the invention described here augments the capability of the MCCAM by adding various features, including the ability to output all the query result bits every clock cycle and to logically "or" together these output query result bits to form additional outputs.
  • Computer graphics is the art and science of generating pictures or images with a computer. This picture generation is commonly referred to as rendering.
  • rendering The appearance of motion, for example in a 3-Dimensional animation is achieved by displaying a sequence of images.
  • Interactive 3-Dimensional (3D) computer graphics allows a user to change his or her viewpoint or to change the geometry in real-time, thereby requiring the rendering system to create new images on-the-fly in real-time. Therefore, real-time performance in color, with high quality imagery is becoming increasingly important.
  • the invention is directed to a new graphics processor and method and encompasses numerous substructures including specialized subsystems, subprocessors, devices, architectures, and corresponding procedures.
  • Embodiments of the invention may include one or more of deferred shading, a tiled frame buffer, and multiple-stage hidden surface removal processing, as well as other structures and/or procedures.
  • this graphics processor is hereinafter referred to as the DSGP (for Deferred Shading Graphics Processor), or the DSGP pipeline, but is sometimes referred to as the pipeline.
  • Embodiments of the present invention are designed to provide high-performance 3D graphics with Phong shading, subpixel anti-aliasing, and texture- and bump-mapping in hardware.
  • the DSGP pipeline provides these sophisticated features without sacrificing performance.
  • the DSGP pipeline can be connected to a computer via a variety of possible interfaces, including but not limited to for example, an Advanced Graphics Port (AGP) and/or a PCI bus interface, amongst the possible interface choices. VGA and video output are generally also included.
  • Embodiments of the invention supports both OpenGL and Direct3D APIs.
  • the OpenGL specification entitled “The OpenGL Graphics System: A Specification (Version 1.2)" by Mark Segal and Kurt Akeley, edited by Jon Leech, is included incorporated by reference.
  • Each frame (also called a scene or user frame) of 3D graphics primitives is rendered into a 3D window on the display screen.
  • a window consists of a rectangular grid of pixels, and the window is divided into tiles (hereinafter tiles are assumed to be 16x16 pixels, but could be any size). If tiles are not used, then the window is considered to be one tile.
  • Each tile is further divided into stamps (hereinafter stamps are assumed to be 2x2 pixels, thereby resulting in 64 stamps per tile, but stamps could be any size within a tile).
  • stamps are assumed to be 2x2 pixels, thereby resulting in 64 stamps per tile, but stamps could be any size within a tile).
  • Each pixel includes one or more of samples, where each sample has its own color values and z-value (hereinafter, pixels are assumed to include four samples, but any number could be used).
  • a fragment is the collection of samples covered by a primitive within a particular pixel. The term "fragment" is also used to describe the collection of visible samples
  • the renderer calculates the color value (RGB or RGBA) and z value for each pixel of each primitive, then compares the z value of the new pixel with the current z value in the Z-buffer. If the z value comparison indicates the new pixel is "in front of the existing pixel in the frame buffer, the new pixel overwrites the old one; otherwise, the new pixel is thrown away.
  • Z-buffer rendering works well and requires no elaborate hardware. However, it typically results in a great deal of wasted processing effort if the scene contains many hidden surfaces. In complex scenes, the renderer may calculate color values for ten or twenty times as many pixels as are visible in the final picture.
  • HSR hidden surface removal
  • the HSR process can be complicated by other operations
  • Some of these operations discard a primitive based on its color (such as alpha test), which is not determined in a deferred shading pipeline until after the HSR process (this is because alpha values are often generated by the texturing process, included in pixel fragment coloring). For example, a primitive that would normally obscure a more distant primitive (generally at a greater z-value) can be discarded by alpha test, thereby causing it to not obscure the more distant primitive. A HSR process that does not take alpha test into account could mistakenly discard the more distant primitive.
  • deferred shading and alpha test similarly, with color test and stencil test
  • pixel coloring is postponed until after hidden surface removal, but hidden surface removal can depend on pixel colors.
  • Simple solutions to this problem include: 1 ) eliminating non-depth-dependent tests from the API, such as alpha test, color test, and stencil test, but this potential solution might prevent existing programs from executing properly on the deferred shading pipeline; and 2) having the HSR process do some color generation, only when needed, but this potential solution would complicate the data flow considerably. Therefore, neither of these choices is attractive.
  • a third alternative, called conservative hidden surface removal (CHSR) is one of the important innovations provided by the inventive structure and method. CHSR is described in great detail in subsequent sections of the specification.
  • DSGPvl "DSGPvl"
  • Figure 4 the inventive pipeline ( Figure 4) has been obtained from the generic conventional pipeline ( Figure 2) by replacing the drawing intensive functions 231 with: (1 ) a scene memory 250 for storing the pipeline state and primitive data describing each primitive, called scene memory in the figure; (2) an exact hidden surface removal process 251; (3) a fragment coloring process 252; and (4) a blending process 253.
  • the scene memory 250 stores the primitive data for a frame, along with their attributes, and also stores the various settings of pipeline state throughout the frame.
  • Primitive data includes vertex coordinates, texture coordinates, vertex colors, vertex normals, and the like
  • primitive data also includes the data generated by the setup for incremental render, which includes spatial, color, and edge derivatives.
  • the scene memory 250 can be double buffered, thereby allowing the HSR process to perform computations on one frame while the floating-point intensive functions perform computations on the next frame.
  • the scene memory can also be triple buffered.
  • the scene memory could also be a scratchpad for the HSR process, storing intermediate results for the HSR process, allowing the HSR process to start before all primitive have been stored into the scene memory.
  • every primitive is associated with the pipeline state information that was valid when the primitive was input to the pipeline.
  • the simplest way to associate the pipeline state with each primitive is to include the entire pipeline state within each primitive. However, this would introduce a very large amount of redundant information because much of the pipeline state does not change between most primitives (especially when the primitives are in the same object).
  • the preferred way to store information in the scene memory is to keep separate lists: one list for pipeline state settings and one list for primitives.
  • the pipeline state information can be split into a multiplicity of sub-lists, and additions to each sub-list occurs only when part of the sub-list changes.
  • the preferred way to store primitives is done by storing a series of vertices, along with the connectivity information to re-create the primitives.
  • the HSR process described relative to DSGPvl is required to be an exact hidden surface removal (EHSR) because it is the only place in the DSGPvl where hidden surface removal is done.
  • EHSR exact hidden surface removal
  • the exact hidden surface removal (EHSR) process 251 determines precisely which primitives affect the final color of the pixels in the frame buffer. This process accounts for changes in the pipeline state, which introduces various complexities into the process. Most of these complications stem from the per-fragment operations (ownership test, scissor test, alpha test, and the like), as described above. These complications are solved by the innovative conservative hidden surface removal (CHSR) process, described later, so that exact hidden surface removal is not required.
  • CHSR innovative conservative hidden surface removal
  • the fragment coloring process generates colors for each sample or group of samples within a pixel.
  • This can include: Gouraud shading, texture mapping, Phong shading, and various other techniques for generating pixel colors.
  • This process is different from edged walk 232 and span interpolation 234 because this process must be able to efficiently generate colors for subsections of primitives. That is, a primitive may be partially visible, and therefore, colors need to be generated for only some of its pixels, and edge walk and span interpolation assume the entire primitive must be colored.
  • the HSR process may generate a multiplicity of visible subsections of a primitive, and these may be interspersed in time amongst visible subsections of other primitives.
  • the fragment coloring process 252 should be capable of generating color values at random locations within a primitive without needing to do incremental computations along primitive edges or along the x-axis or y-axis.
  • the blending process 253 of the inventive embodiment combines the fragment colors together to generate a single color per pixel. In contrast to the conventional z-buffered blend process 236, this blending process 253 does not include z-buffer operations because the exact hidden surface removal process 251 as already determined which primitives are visible at each sample.
  • the blending process 253 may keep separate color values for each sample, or sample colors may be blended together to make a single color for the entire pixel. If separate color values are kept per sample and are stored separately into the Frame buffer 240 , then final pixel colors are generated from sample colors during the scan out process as data is sent to the digital to analog converter 242.
  • the scene memory 250 stores: (1) primitive data; and (2) pipeline state.
  • this scene memory 250 is split into two parts: a spatial memory 261 part and polygon memory 262 part. The split of the data is not simply into primitive data and pipeline state data.
  • the part of the pipeline state data needed for HSR is stored into spatial memory 261 , while the rest is stored into polygon memory 262.
  • Examples of pipeline state needed for HSR include (as defined, for example, in the OpenGL Specification) are DepthFunc, DepthMask, Stencil Enable, etc.
  • Examples of pipeline state not needed for HSR include: BlendEquation, BlendFunc, stipple pattern, etc. While the choice or identification of a particular blending function (for example, choosing is not needed for HSR, the HSR process must account for whether the primitive is subject to blending, which generally means the primitive is treated as not being able to fully occlude prior geometry. Similarly, the HSR process must account for whether the primitive is subject to scissor test, alpha test, color test, stencil test, and other per-fragment operations.
  • Primitive data is also split.
  • the part of the primitive data needed for HSR is stored into spatial memory 261 , and the rest of the primitive data is stored into polygon memory 262.
  • the part of primitive data needed for HSR includes vertex locations and spatial derivatives (i.e., ⁇ z/ ⁇ x, ⁇ z/ ⁇ y, dx/dy for edges, etc.).
  • the part of primitive data not needed for HSR includes vertex colors, texture coordinates, color derivatives, etc. If per-fragment lighting is performed in the pipeline, the entire lighting equation is applied to every fragment. But in a deferred shading pipeline, only visible fragments require lighting calculations.
  • the polygon memory may also include vertex normals, vertex eye coordinates, vertex surface tangents, vertex binormals, spatial derivatives of all these attributes, and other per-primitive lighting information.
  • a primitive's spatial attributes are accessed repeatedly, especially if the HSR process is done on a per-tile basis.
  • Splitting the scene memory 250 into spatial memory 261 and polygon memory 262 has the advantage of reducing total memory bandwidth.
  • the output from setup for incremental render 230 is input to the spatial data separation process 263, which stores all the data needed for HSR into spatial memory 261 and the rest of the data into polygon memory 262.
  • the EHSR process 264 receives primitive spatial data (e.g., vertex screen coordinates, spatial derivatives, etc.) and the part of the pipeline state needed for HSR (including all control bits for the per-fragment testing operations).
  • primitive spatial data e.g., vertex screen coordinates, spatial derivatives, etc.
  • the data matching process 265 matches the vertex state and pipeline state with visible fragments, and tile information is stored in tile buffers 266.
  • the remainder of the pipeline is primarily concerned with the scan out process including sample to/from pixel conversion 267, reading and writing to the frame buffer, double buffered MUX output look-up, and digital to analog (D/A) conversion of the data stored in the frame buffer to the actual analog display device signal values.
  • D/A digital to analog
  • a fifth embodiment of the Deferred Shading Graphics Pipeline (Version 5) (DSGPv ⁇ ), illustrated in Figure 8, exact hidden surface removal is used as in the third embodiment, however, the tiling is added, and a tile sorting procedure is added after data separation, and the read is by tile prior to spatial setup.
  • the polygon memory of the first three embodiments is replaced with a state memory.
  • This sixth embodiment is preferred because it incorporates several of the beneficial features provided by the inventive structure and method including: a two-part scene memory, primitive data splitting or separation, spatial setup, tiling and per tile processing, conservative hidden surface removal, and z-buffered blending (Testing & Blending), to name a few features.
  • the pipeline renders primitives, and the invention is described relative to a set of renderable primitives that include: 1 ) triangles, 2) lines, and 3) points. Polygons with more than three vertices are divided into triangles in the Geometry block, but the DSGP pipeline could be easily modified to render quadrilaterals or polygons with more sides. Therefore, since the pipeline can render any polygon once it is broken up into triangles, the inventive renderer effectively renders any polygon primitive.
  • the pipeline To identify what part of a 3D window on the display screen a given primitive may affect, the pipeline divides the 3D window being drawn into a series of smaller regions, called tiles and stamps. The pipeline performs deferred shading, in which pixel colors are not determined until after hidden-surface removal.
  • MCCAM Magnitude Comparison Content Addressable Memory
  • CHSR Conservative Hidden Surface Removal
  • the CHSR process can be considered a finite state machine (FSM) per sample.
  • FSM finite state machine
  • SFSM sample finite state machine
  • Each SFSM maintains per-sample data including: (1 ) z-coordinate information; (2) primitive information (any information needed to generate the primitive's color at that sample or pixel); and (3) one or more sample state bits (for example, these bits could designate the z-value or z-values to be accurate or conservative). While multiple z-values per sample can be easily used, multiple sets of primitive information per sample would be expensive.
  • the SFSM maintains primitive information for one primitive.
  • the SFSM may also maintain transparency information, which is used for sorted transparencies, described in the next section.
  • FIG. 10-14 illustrates the rendering of six primitives (Primitives A, B, C, D, E, and F) at different z-coordinate locations for a particular sample, rendered in the following order (starting with a "depth clear” and with “depth test” set to less-than): primitives A, B, and C (with “alpha test” disabled); primitive D (with "alpha test” enabled); and primitives E and F (with "alpha test” disabled).
  • z A >z c >z B >z E >z D >z F such that primitive A is at the greatest z-coordinate distance.
  • alpha test is enabled for primitive D, but disabled for each of the other primitives.
  • CHSR CHSR process
  • SFSM sample finite state machine
  • Step 1 The depth clear causes the following result in each sample finite state machine (SFSM): 1) z-values are initialized to the maximum value; 2) primitive information is cleared; and
  • SFSM sample finite state machine
  • sample state bits are set to indicate the z-value is accurate.
  • Step 2 When primitive A is processed by the SFSM, the primitive is kept (i.e., it becomes the current best guess for the visible surface), and this causes the SFSM to store: 1) the z-value z A as the "near" z-value; 2) primitive information needed to color primitive A; and 3) the z-value (z A ) is labeled as accurate.
  • Step 3 When primitive B is processed by the SFSM, the primitive is kept (its z-value is less-than that of primitive A), and this causes the SFSM to store: 1 ) the z-value z B as the "near" z-value (z A is discarded); 2) primitive information needed to color primitive B (primitive A's information is discarded); and 3) the z-value (z B ) is labeled as accurate.
  • Step 4 When primitive C is processed by the SFSM the primitive is discarded (i.e., it is obscured by the current best guess for the visible surface, primitive B), and the SFSM data is not changed.
  • Step 5 When primitive D (which has alpha test enabled) is processed by the SFSM, the primitive's visibility can not be determined because it is closer than primitive B and because its alpha value is unknown at the time the SFSM operates. Because a decision can not be made as to which primitive would end up being visible (either primitive B or primitive D) primitive B is sent down the pipeline (to have its colors generated) and primitive D is kept. Hereinafter, this is called “early dispatch" of primitive B.
  • the SFSM stores: 1 ) the "near" z-value is z D and the "far” z-value is z ⁇ ; 2) primitive information needed to color primitive D (primitive B's information has undergone early dispatch); and 3) the z-values are labeled as conservative (because both a near and far are being maintained).
  • the SFSM can determine that a piece of geometry closer than z D obscures previous geometry, geometry farther than z B is obscured, and geometry between z D and z B is indeterminate and must be assumed to be visible (hence a conservative assumption is made).
  • the SFSM method considers the depth value of the stored primitive information to be the near depth value.
  • Step 6 When primitive E (which has alpha test disabled) is processed by the SFSM, the primitive's visibility can not be determined because it is between the near and far z-values (i.e., between z D and Zg). However, primitive E is not sent down the pipeline at this time because it could result in the primitives reaching the z-buffered blend (later described as part of the Pixel
  • primitive D is sent down the pipeline to preserve the time ordering.
  • the SFSM stores: 1) the "near" z-value is z D and the "far" z-value is g. (note these have not changed, and z E is not kept); 2) primitive information needed to color primitive E (primitive D's information has undergone early dispatch); and 3) the z-values are labeled as conservative
  • Step 7 When primitive F is processed by the SFSM, the primitive is kept (its z-value is less-than that of the near z-value), and this causes the SFSM to store: 1 ) the z-value z F as the "near" z-value (z D and % are discarded); 2) primitive information needed to color primitive F (primitive E's information is discarded); and 3) the z-value (z F ) is labeled as accurate.
  • Step 8 When all the geometry that touches the tile has been processed (or, in the case there are no tiles, when all the geometry in the frame has been processed), any valid primitive information is sent down the pipeline.
  • primitive F's information is sent. This is the end-of-tile (or end-of-frame) dispatch, and not an early dispatch.
  • primitives A through F have been processed, and primitives B, D, and F have been sent down the pipeline.
  • a z-buffered blend in the Pixel Block in the preferred embodiment
  • only the color primitive F is used for the sample.
  • all stencil operations are done near the end of the pipeline (in the z-buffered blend, called the Pixel Block in the preferred embodiment), and therefore, stencil values are not available to the CSHR method (that takes place in the Cull Block of the preferred embodiment) because they are kept in the frame buffer. While it is possible for the stencil values to be transmitted from the frame buffer for use in the CHSR process, this would generally require a long latency path that would reduce performance.
  • the stencil values can not be accurately maintained within the CHSR process because, in APIs such as OpenGL, the stencil test is performed after alpha test, and the results of alpha test are not known to the CHSR process, which means input to the stencil test can not be accurately modeled.
  • renderers maintain stencil values over many frames (as opposed to depth values that are generally cleared at the start of each frame), and these stencil values are stored in the frame buffer. Because of all this, the CHSR process utilizes a conservative approach to dealing with stencil operations. If a primitive can affect the stencil values in the frame buffer, then the primitive is always sent down the pipeline (hereinafter, this is called a "CullFlushOverlap", and is indicated by the assertion of the signal CullFlushOverlap in the Cull Block) because stencil operations occur before the depth test (see OpenGL specification). A CullFlushOverlap condition sets the SFSM to its most conservative state.
  • Step 1 The depth clear causes the following in each of the four SFSMs in this example: 1 ) z-values are initialized to the maximum value; 2) primitive information is cleared; and 3) sample state bits are set to indicate the z-value is accurate.
  • Step 2 When primitive A is processed by each SFSM, the primitive is kept (i.e., it becomes the current best guess for the visible surface), and this causes the four SFSMs to store:
  • Step 3 When primitive B is processed by the SFSMs, only samples 1 and 2 are affected, causing SFSMO and SFSM3 to be unaffected and causing SFSM1 and SFSM2 to be updated as follows: 1 ) the far z-values are set to the maximum value and the near z-values are set to the minimum value; 2) primitive information for primitives A and B are sent down the pipeline; and 3) sample state bits are set to indicate the z-values are conservative.
  • Step 4 When primitive C is processed by each SFSM, the primitive is kept, but the SFSMs do not all handle the primitive the same way.
  • SFSMO and SFSM3 the state is updated as: 1 ) Zco and z ⁇ become the "near" z-values (z A0 and z A3 are discarded); 2) primitive information needed to color primitive C (primitive A's information is discarded); and 3) the z-values are labeled as accurate.
  • the state is updated as: 1) Z Q , and Zc 2 become the "far" z- values (the near z-values are kept); 2) primitive information needed to color primitive C; and 3) the z-values remain labeled as conservative.
  • Step 1 The depth clear causes the following in each CHSR SFSM: 1 ) z-values are initialized to the maximum value; 2) primitive information is cleared; and 3) sample state bits are set to indicate the z-value is accurate.
  • Step 2 When primitive A is processed by the SFSM, the primitive is kept (i.e., it becomes the current best guess for the visible surface), and this causes the SFSM to store: 1) the z-value z A as the "near" z-value; 2) primitive information needed to color primitive A; and 3) the z-value is labeled as accurate.
  • Step 3 When primitive B is processed by the SFSM, the primitive is kept (because its z- value is less-than that of primitive A), and this causes the SFSM to store: 1 ) the z-value z B as the
  • Step 4 When primitive C is processed by the SFSM, the primitive is discarded (i.e., it is obscured by the current best guess for the visible surface, primitive B), and the SFSM data is not changed. Note that if primitives B and C need to be rendered as transparent surfaces, then primitive C should not be hidden by primitive B. This could be accomplished by turning off the depth mask while primitive B is being rendered, but for transparency blending to be correct, the surfaces should be blended in either front-to-back or back-to-front order.
  • the depth mask (see OpenGL specification) is disabled, writing to the depth buffer (i.e., saving z-values) is not performed; however, the depth test is still performed.
  • the depth mask is disabled for primitive B, then the value z B is not saved in the SFSM. Subsequently, primitive C would then be considered visible because its z-value would be compared to z A .
  • Samples are done in parallel, and generally all the samples in all the pixels within a stamp are done in parallel. Hence, if one stamp can be processed per clock cycle (and there are 4 pixels per stamp and 4 samples per pixel), then 16 samples are processed per clock cycle.
  • a "stamp" defines the number of pixels and samples processed at one time. This per-stamp processing is generally pipelined, with pipeline stalls injected if a stamp needs to be processed again before the same stamp (from a previous primitive) has completed (that is, unless out-of-order stamp processing can be handled).
  • the primitive information in each SFSM can be replaced by a pointer into a memory where all the primitive information is stored.
  • the Color Pointer is used to point to a primitive's information in Polygon Memory.
  • Stamps are also used to reduce the number of data packets transmitted down the pipeline. That is, when one sample within a stamp is dispatched (either early dispatch or end-of-tile dispatch), other samples within the same stamp and the same primitive are also dispatched (such a joint dispatch is hereinafter called a Visible Stamp Portion, or VSP).
  • VSP Visible Stamp Portion
  • alpha test if alpha values for a primitive arise only from the alpha values at the vertices (not from other places such as texturing), then a simplified alpha test can be done for entire primitives. That is, the vertex processing block (called GEO in later sections) can determine when any interpolation of the vertex alpha values would be guaranteed to pass the alpha test, and for that primitive, disable the alpha test. This can not be done if the alpha values can not be determined before CHSR is performed.
  • GEO vertex processing block
  • the SFSMs are set to their most conservative state (with near z-values at the minimum and far z-values at the maximum).
  • the CHSR process is performed in the Cull Block.
  • time-order is preserved within each tile, including preserving time-order of pipeline state information. Clear packets are also used.
  • the sorting is performed in hardware and RAMBUS memories advantageously permit dualoct storage of one vertex.
  • guaranteed opaque geometry that is, geometry that is known to obscure more distant geometry
  • the tile sorting method is performed in the Sort Block.
  • All vertices and relevant mode packets or state information packets are stored as a time order linear list. For each tile that's touched by a primitive, a pointer is added to the vertex in that linear list that completes the primitive. For example, a triangle primitive is defined by 3 vertices, and a pointer would be added to the (third) vertex in the linear list to complete the triangle primitive. Other schemes that use the first vertex rather than the third vertex may alternatively be implemented.
  • a pointer is used to point to one of the vertices in the primitive, with adequate information for finding the other vertices in the primitive.
  • the entire primitive can be reconstructed from the vertices and pointers ' .
  • Each tile is a list of pointers that point to vertices and permit recreation of the primitive from the list. This approach permits all of the primitives to be stored, even those sharing a vertex with another primitive, yet only storing each vertex once.
  • one list per tile is maintained. We do not store the primitive in the list, but instead the list stores pointers to the primitives. These pointers are actually pointing to one of the primitives, and is a pointer into one of the vertices in the primitive, and the pointer also includes information adequate to find the other vertices in the same primitive.
  • This sorting structure is advantageously implemented in hardware using the structure comprising three storage structures, a data storage, a tile pointer storage, and a mode pointer storage. For a given tile, the goal is to recreate the time-order sequence of primitives that touch the particular tile being processed, but ignore the primitives that don't touch the tile.
  • the DSGP can operate in two distinct modes: 1 ) Time Order Mode, and 2) Sorted Transparency Mode.
  • Time Order Mode is described above, and is designed to preserve, within any particular tile, the same temporal sequence of primitives.
  • the Sorted Transparency mode is described immediately below.
  • the control of the pipeline operating mode is done in the Sort Block.
  • Sort Block is located in the pipeline between a Mode Extraction Unit (MEX) and Setup (STP) unit.
  • Sort Block operates primarily to take geometry scattered around the display window and sort it into tiles.
  • Sort Block also manages the Sort Memory, which stores all the geometry from the entire scene before it is rasterized, along with some mode information.
  • Sort memory comprises a double-buffered list of vertices and modes. One page collects a scene's geometry (vertex by vertex and mode by mode), while the other page is sending its geometry (primitive by primitive and mode by mode) down the rest of the pipeline.
  • Time-Ordered Mode In time ordered mode, time order of vertices and modes are preserved within each tile, where a tile is a portion of the display window bounded horizontally and vertically. By time order preserved, we mean that for a given tile, vertices and modes are read in the same order as they are written. 3.2.6 Sorted Transparency Mode
  • sorted transparency mode reading of each tile is divided into multiple passes, where, in the first pass, guaranteed opaque geometry is output from the sort block, and in subsequent passes, potentially transparent geometry is output from the sort block.
  • time ordering is preserved, and mode date is inserted in its correct time-order location.
  • Sorted transparency mode by be performed in either back-to-front or front-to- back order. In the preferred embodiment, the sorted transparency method is performed jointly by the Sort Block and the Cull Block.
  • Each vertex includes a color pointer, and as vertices are received, the vertices including the color pointer are stored in sort memory data storage.
  • the color pointer is a pointer to a location in the polygon memory vertex storage that includes a color portion of the vertex data.
  • MLM Material-Lighting-Mode
  • MLM includes six main pointers plus two other pointers as described below.
  • Each of the six main pointers comprises an address to the polygon memory state storage, which is a sequential storage of all of the state that has changed in the pipeline, for example, changes in the texture, the pixel, lighting and so forth, so that as a need arises any time in the future, one can recreate the state needed to render a vertex (or the object formed from one or more vertices) from the MLM pointer associated with the vertex, by looking up the MLM pointers and going back into the polygon memory state storage and finding the state that existed at the time.
  • the Mode Extraction Block is a logic block between Geometry and Sort that collects temporally ordered state change data, stores the state in Polygon memory, and attaches appropriate pointers to the vertex data it passes to Sort Memory.
  • Geometry and Sort In the normal OpenGL pipeline, and in embodiments of the inventive pipeline up to the Sort block, geometry and state data is processed in the order in which it was sent down the pipeline. State changes for material type, lighting, texture, modes, and stipple affect the primitives that follow them. For example, each new object will be preceded by a state change to set the material parameters for that object.
  • Mode Injection Block figures out how to preserve state in the portion of the pipeline that processes data in spatial (Tile) order instead of time order.
  • Mode Extraction Block sends a subset of the Mode data (culljnode) down the pipeline for use by Cull.
  • Cull_mode packets are produced in Geometry Block.
  • Mode Extraction Block inserts the appropriate color pointer in the Geometry packets.
  • Pipeline state is broken down into several categories to minimize storage as follows: (1 ) Spatial pipeline state includes data headed for Sort that changes every vertex; (2) Culljnode state includes data headed for Cull (via Sort) that changes infrequently; (3) Color includes data headed for Polygon memory that changes every vertex; (4) Material includes data that changes for each object; (5) TextureA includes a first set of state for the Texture Block for textures 0&1 ; (6) TextureB includes a second set of state for the Texture Block for textures 2 through 7; (7) Mode includes data that hardly ever changes; (8) Light includes data for Phong; (9) Stipple includes data for polygon stipple patterns. Material, Texture, Mode, Light, and Stipple data are collectively referred to as MLM data (for Material, Light and Mode). We are particularly concerned with the MLM pointers fir state preservation.
  • MLM data for Material, Light and Mode
  • State change information is accumulated in the MEX until a primitive (Spatial and Color packets) appears. At that time, any MLM data that has changed since the last primitive, is written to Polygon Memory. The Color data, along with the appropriate pointers to MLM data, is also written to Polygon Memory. The spatial data is sent to Sort, along with a pointer into Polygon Memory (the color pointer). Color and MLM data are all stored in Polygon memory. Allocation of space for these records can be optimized in the micro-architecture definition to improve performance.
  • Each primitive entry in Sort Memory contains a Color Pointer to the corresponding Color entry in Polygon Memory.
  • the Color Pointer includes a Color Address, Color Offset and Color Type that allows us to construct a point, line, or triangle and locate the MLM pointers.
  • the Color Address points to the final vertex in the primitive. Vertices are stored in order, so the vertices in a primitive are adjacent, except in the case of triangle fans.
  • the Color Offset points back from the Color Address to the first dualoct for this vertex list.
  • This first dualoct contains pointers to the MLM data for the points, lines, strip, or fan in the vertex list.
  • the subsequent dualocts in the vertex list contain Color data entries.
  • the three vertices for the triangle are at Color Address, (Color Address-1 ), and (Color Address - Color Offset
  • State is a time varying entity, and MEX accumulates changes in state so that state can be recreated for any vertex or set of vertices.
  • the MIJ block is responsible for matching state with vertices down stream. Whenever a vertex comes into MEX and certain indicator bits are set, then a subset of the pipeline state information needs to be saved. Only the states that have changed are stored, not all states, since the complete state can be created from the cumulative changes to state.
  • the six MLM pointers for Material, TextureA, TextureB, Mode, Light, and Stipple identify address locations where the most recent changes to the respective state information is stored. Each change in one of these state is identified by an additional entry at the end of a sequentially ordered state storage list stored in a memory. Effectively, all state changes are stored and when particular state corresponding to a point in time (or receipt of a vertex) is needed, the state is reconstructed from the pointers.
  • mode packets This packet of mode that are saved are referred to as mode packets, although the phrase is used to refer to the mode data changes that are stored, as well as to larger sets of mode data that are retrieved or reconstructed by MIJ prior to rendering.
  • Polygon memory vertex storage stores just the color portion.
  • Polygon memory stores the part of pipeline stat that is not needed for hidden surface removal, and it also stores the part of the vertex data which is not needed for hidden surface removal (predominantly the items needed to make colors.)
  • the inventive structure and method may advantageously make use of trilinear mapping of multiple layers (resolutions) of texture maps.
  • Texture maps are stored in a Texture Memory which may generally comprise a single- buffered memory loaded from the host computer's memory using the AGP interface.
  • a single polygon can use up to four textures.
  • Textures are MlP-mapped. That is, each texture comprises a series of texture maps at different levels of detail or resolution, each map representing the appearance of the texture at a given distance from the eye point.
  • the Texture block performs tri-linear interpolation from the texture maps, to approximate the correct level of detail.
  • the Texture block can alternatively performs other interpolation methods, such as anisotropic interpolation.
  • the Texture block supplies interpolated texture values (generally as RGBA color values) to the Phong block on a per-fragment basis.
  • Bump maps represent a special kind of texture map.
  • each texel of a bump map contains a height field gradient.
  • the multiple layers are MIP layers, and interpolation is within and between the MIP layers.
  • the first interpolation ii within each layer then you interpolate between the two adjacent layers, one nominally having resolution greater than required and the other layer having less resolution than required, so that it is done 3-dimensionally to generate an optimum resolution.
  • the inventive pipeline includes a texture memory which includes a texture cache really a textured reuse register because the structure and operation are different from conventional caches.
  • the host also includes storage for texture, which may typically be very large, but in order to render a texture, it must be loaded into the texture cache which is also referred to as texture memory.
  • texture memory which is also referred to as texture memory.
  • S and T's Associated with each VSP.
  • the inventive structure provides a set of eight content addressable (memory) caches running in parallel, n one embodiment, the cache identifier is one of the content addressable tags, and that's the reason the tag part of the cache and the data part of the cache is located are located separate from the tag or index. Conventionally, the tag and data are co-located so that a query on the tag gives the data.
  • the tags and data are split up and indices are sent down the pipeline.
  • the data and tags are stored in different blocks and the content addressable lookup is a lookup or query of an address, and even the "data" stored at that address in itself and index that references the actual data which is stored in a different block.
  • the indices are determined, and sent down the pipeline so that the data referenced by the index can be determined.
  • the tag is in one location
  • the texture data is in a second location
  • the indices provide a link between the two storage structures.
  • Texel Reuse Detection Registers comprise a multiplicity of associate memories, generally located on the same integrated circuit as the texel interpolator.
  • the texel reuse detection method is performed in the Texture Block.
  • an object in some orientation in space is rendered.
  • the object has a texture map on it, and its represented by many triangle primitives.
  • the procedure implemented in software will instruct the hardware to load the particular object texture into a D.R V1.
  • all of the triangles that are common to the particular object and therefore have the same texture map are fed into the unit and texture interpolation is performed to generate all of the colored pixels need to represent that particular object.
  • the texture map in DRAM can be destroyed since the object has been rendered. If there are more than one object that have the same texture map, such as a plurality of identical objects (possibly at different orientations or locations), then all of that type of object may desirably be textured before the texture map in DRAM is discarded.
  • Different geometry may be fed in, but the same texture map could be used for all, thereby eliminating any need to repeatedly retrieve the texture map from host memory and place it temporarily in one or more pipeline structures.
  • more than one texture map may be retrieved and stored in the memory, for example two or several maps may be stored depending on the available memory, the size of the texture maps, the need to store or retain multiple texture maps, and the sophistication of the management scheme.
  • spatial object coherence is of primary importance. At least for an entire single object, and typically for groups of objects using the same texture map, all of the triangles making up the object are processed together. The phrase spatial coherency is applied to such a scheme because the triangles form the object and are connected in space, and therefore spatially coherent.
  • inventive deferred shader structure and method we do not necessarily rely on or derive appreciable benefit from this type of spatial object coherence.
  • Embodiments of the inventive deferred shader operate on tiles instead. Any given tile might have an entire object, a plurality of objects, some entire objects, or portions of several objects, so that spatial object coherence over the entire tile is typically absent.
  • the pipeline and texture block are advantageously capable of changing the texture map on the fly in real-time and in response to the texture required for the object primitive (e.g. triangle) received.
  • a sizable memory is supported on the card.
  • 128 megabytes are provided, but more or fewer megabytes may be provided.
  • 34 Mb, 64 Mb, 256 Mb, 512 Mb, or more may be provided, depending upon the needs of the user, the real estate available on the card for memory, and the density of memory available.
  • the inventive structure and method stores and reuses them when there is a reasonable chance they will be needed again.
  • the invention uses the textels that have been read over and over, so when we need one, we read it, and we know that chances are good that once we have seem one fragment requiring a particular texture map, chances are good that for some period of time afterward while we are in the same tile, we will encounter another fragment from the same object that will need the same texture. So we save those things in this cache, and then on the fly we look up from the cache (texture reuse register) which ones we need. If there is a cache miss, for example, when a fragment and texture map are encountered for the first time, that texture map is retrieved and stored in the cache.
  • Texture Map retrieval latency is another concern, but is handled through the use of First- In-First-Out (FIFO) data structures and a look-ahead or predictive retrieval procedure.
  • FIFO First- In-First-Out
  • the FIFO's are large and work in association with the CAM.
  • a designator is also placed in the FIFO so that if there is a cache miss, it is still possible to go out to the relatively slow memory to retrieve the information and store it. In either event, that is if the data was in the cache or it was retrieved from the host memory, it is placed in the unit memory (and also into the cache if newly retrieved).
  • the FIFO acts as a sort of delay so that once the need for the texture is identified (prior to its actual use) the data can be retrieved and reassociated, before it is needed, such that the retrieval does not typically slow down the processing.
  • the FIFO queues provide and take up the slack in the pipeline so that it always predicts and looks ahead.
  • non-cached texture can be identified, retrieved from host memory, placed in the cache and in a special unit memory, so that it is ready for use when a read is executed.
  • FIFO and other structures that provide the look-ahead and predictive retrieval are provided in some sense to get around the problem created when the spatial object coherence typically used in per-object processing is lost in our per-tile processing.
  • inventive structure and method makes use of any spatial coherence within an object, so that if all the pixels in one object are done sequentially, the invention does take advantage of the fact that there's temporal and spatial coherence.
  • the inventive structure and method advantageously transfer information (such as data and control) from block to block in packets.
  • information such as data and control
  • packetized data transfer and the format and/or content of the packetized data as the packetized data transfer protocol (PDTP).
  • PDTP packetized data transfer protocol
  • the protocol includes a header portion and a data portion.
  • PDTP One benefit of the PDTP is that all of the data can be sent over one bus from block to block thereby alleviating any need for separate busses for different data types. Another advantage of PDTP is that packetizing the information assists in keeping the ordering, which is important for proper rendering. Recall that rendering is sensitive to changes in pipeline state and the like so that maintaining the time order sequence is important generally, and with respect to the MIJ cache for example, management of the flow of packets down the pipeline is especially important.
  • the transfer of packets is sequential, since the bus is effectively a sequential link wherein packets arrive sequentially in some time order. If for example, a "fill packet" arrives in a block, it goes into the block's FIFO, and if a VSP arrives, it also goes into the block's FIFO.
  • Each processor block waits for packets to arrive at its input, and when a packet arrives looks at the packet header to determine what action to take if any. The action may be to send the packet to the output (that is just pass it on without any other action or processing) or to do something with it.
  • the packetized data structure and use of the packetized data structure alone and in conjunction with a bus, FIFO or other buffer or register scheme have applications broader than 3D graphics systems and may be applied to any pipeline structure where a plurality of functional or processing blocks or units are interconnected and communicate with each other. Use of packetized transfer is particularly beneficial where maintain sequential or time order is important.
  • each packet has a packet identifier or ID and other information.
  • packet identifier or ID There are many different types of packets, and every different packet type has a standard length, and includes a header that identifies the type of packet.
  • the different packets have different forms and variable lengths, but each particular packet type has a standard length.
  • each block includes a FIFO at the input, and the packets flow through the FIFOs where relevant information is accumulated in the FIFO by the block.
  • the packet continues to flow through other or all of the blocks so that information relevant to that blocks function may be extracted.
  • the storage cells or registers within the FIFO's has some predetermined width such that small packets may require only one FIFO register and bigger packets require a larger number of registers, for example 2, 3, 5, 10, 20, 50 or more registers.
  • variable packet length and the possibility that a single packet may consume several FIFO storage registers do not present any problem as the first portion of the packet identifies the type of packet and either directly, or indirectly by virtue of knowing the packet type, the size of the packet and the number of FIFO entries it consumes.
  • the inventive structure and method provide and support numerous packet types which are described in other sections of this document.
  • Fragment coloring is performed for two-dimensional display space and involves an interpolation of the color from for example the three vertices of a triangle primitive, to the sampled coordinate of the displayed pixel.
  • fragment coloring involves applying an interpolation function to the colors at the three fragment vertices to determine a color for a location spatially located between or among the three vertices.
  • the interpolation coefficients are cached as are the perspective correction coefficients.
  • surface normals are interpolated based on linear interpolation of the two input normals .
  • linear interpolation of the composite surface normals may provide adequate accuracy; however, considering a two- dimensional interpolation example, when one vector (surface normal) has for example a larger magnitude that the other vector, but comparable angular change to the first vector, the resultant vector will be overly influenced by the larger magnitude vector in spite of the comparable angular difference between the two vectors. This may result in objectionable error, for example, some surface shading or lighting calculation may provide an anomalous result and detract from the output scene.
  • the Setup (STP) block receives a stream of packets from the Sort (SRT) block. These packets have spatial information about the primitives to be rendered.
  • the output of the STP block goes to the Cull (CUL) block.
  • the primitives received from SRT can be filled triangles, line triangles, lines, stippled lines, and points. Each of these primitives can be rendered in aliased or anti-aliased mode.
  • the SRT block sends primitives to STP (and other pipeline stages downstream) in tile order. Within each tile the data is organized in time order or in sorted transparency order.
  • the CUL block receives data from the STP block in tile order (in fact in the order that STP receives primitives from SRT), and culls out parts of the primitives that definitely do not contribute to the rendered images. This is accomplished in two stages. The first stage allows detection of those elements in a rectangular memory array whose content is greater than a given value. The second stage refines on this search by doing a sample by sample content comparison.
  • the STP block prepares the incoming primitives for processing by the CUL block. STP produces a tight bounding box and minimum depth value Zmin for the part of the primitive intersecting the tiie for first stage culling, which marks the stamps in the bounding box that may contain depth values less than Zmin.
  • the Z cull stage takes these candidate stamps, and if they are a part of the primitive, computes the actual depth value for samples in that stamp. This more accurate depth value is then used for comparison and possible discard on a sample by sample basis.
  • STP also computes the depth gradients, line slopes, and other reference parameters such as depth and primitive intersection points with the tile edge for the Z cull stage.
  • the CUL unit produces the VSPs used by the other pipeline stages.
  • the spatial setup procedure is performed in the Setup Block.
  • Important aspects of the inventive spatial setup structure and method include: (1 ) support for and generation of a unified primitive, (2) procedure for calculating a Z min within a tile for a primitive, (3) the use of tile-relative y-values and screen-relative x-values, and (4) performing a edge hop (actually performed in the Cull Block) in addition to a conventional edge walk which also simplifies the down-stream hardware,
  • VtxYmin, VtxYmax, VtxLeftC, VtxRightC, LeftCorner, RightCorner descriptors are obtained by sorting the triangle vertices by their y coordinates. For line segments these descriptors are assigned when the line quad vertices are generated.
  • VtxYmin is the vertex with the minimum y value.
  • VtxYmax is the vertex with the maximum y value.
  • VtxLeftC is the vertex that lies to the left of the long y-edge (the edge of the triangle formed by joining the vertices VtxYmin and VtxYmax) in the case of a triangle, and to the left of the diagonal formed by joining the vertices VtxYmin and VtxYmax for parallelograms. If the triangle is such that the long y-edge is also the left edge, then the flag LeftCorner is FALSE (0) indicating that the VtxLeftC is invalid.
  • VtxRightC is the vertex that lies to the right of the long y-edge in the case of a triangle, and to the right of the diagonal formed by joining the vertices VtxYmin and VtxYmax for parallelograms. If the triangle is such that the long edge is also the right edge, then the flag RightCorner is FALSE (0) indicating that the VtxRightC is invalid. These descriptors are used for clipping of primitives on top and bottom tile edge. Note that in practice VtxYmin, VtxYmax, VtxLeftC, and VtxRightC are indices into the original primitive vertices.
  • VtxXmin, VtxXmax, VtxTopC, VtxBotC, TopCorner, BottomComer descriptors are obtained by sorting the triangle vertices by their x coordinates. For line segments these descriptors are assigned when the line quad vertices are generated.
  • VtxXmin is the vertex with the minimum x value.
  • VtxXmax is the vertex with the maximum x value.
  • VtxTopC is the vertex that lies above the long xedge (edge joining vertices VtxXmin and VtxXmax) in the case of a triangle, and above the diagonal formed by joining the vertices VtxXmin and VtxXmax for parallelograms.
  • the flag TopCorner is FALSE (O) indicating that the VtxTopC is invalid.
  • VtxBotC is the vertex that lies below the long x-axis in the case of a triangle, and below the diagonal formed by joining the vertices VtxXmin and VtxXmax for parallelograms. If the triangle is such that the long x-edge is also the bottom edge, then the flag BottomComer is FALSE (0) indicating that the VtxBotC is invalid.
  • VtxXmin, VtxXmax, VtxTopC, and VtxBotC are indices into the original primitive vertices.
  • Treating lines as rectangles involves specifying two end points in space and a width. Treating triangles as rectangles involves specifying four points, one of which typically y-left or y-right in one particular embodiment, is degenerate and not specified. The goal is to find Zmin inside the tile.
  • the x-values can range over the entire window width while the y-values are tile relative, so that bits are saved in the calculations by making the y-vaiues tile relative coordinates.
  • a directed acyclical graph representation of 3D scenes typically assigns an identifier to each node in the scene graph.
  • This identifier (the object tag) can be useful in graphical operations such as picking an object in the scene, visibility determination, collision detection, and generation of other statistical parameters for rendering.
  • the pixel pipeline in rendering permits a number of pixel tests such as alpha test, color test, stencil test, and depth test. Alpha and color test are useful in determining if an object has transparent pixels and discarding those values. Stencil test can be used for various special effects and for determination of object intersections in CSG. Depth test is typically used for hidden surface removal.
  • the object identifier consists if two parts a group (g) and a member tag (t).
  • the group "g” is a 4 bit identifier (but, more bits could be used), and can be used to encode scene graph branch, node level, or any other parameter that may be used grouping the objects.
  • the member tag (t) is a 5 bit value (once again, more bits could be used). In this scheme, each group can thus have up to 32 members.
  • a 32-bit status word is used for each group. The bits of this status word indicate the member that passed the test criteria.
  • the state thus consists of: Object group; Object Tag; and TagTestlD ⁇ DepthTest, AlphaTest, ColorTest, StencilTest ⁇ .
  • the object tags are passed down the pipeline, and are used in the z- buffered blend (or Pixel Block in the preferred embodiment). If the sample is visible, then the object tag is used to set a particular bit in a particular CPU-readable register. This allows objects to be fed into the pipeline and, once rendering is completed, the host CPU (that CPU or CPUs which are running the application program) can determine which objects were at least partially visible.
  • Object tags can be used for picking, transparency determination, early object discard, and collision detection.
  • early object discard an object can be tested for visibility by having its bounding volume input into the rendering pipeline and tested for "visibility" as described above.
  • the color, depth, and stencil masks should be cleared (see OpenGL specification for a description of these mask bits).
  • a single bit can be used as feedback to the host CPU.
  • the object being tested for "visibility” i.e., for picking, transparency determination, early object discard, collision detection, etc
  • the single "visibility bit” is set, otherwise it is cleared. This bit is readable by the host CPU.
  • the advantage of this method is its simplicity. The disadvantage is the need to use individual frames for each separate object (or set of objects) that needs to be tested, thereby possibly introducing latency into the "visibility" determination.
  • Normalization during output is an inventive procedure in which either consideration is taken of the prior processing history to determine the values in the frame buffer, or the values in the frame buffer are otherwise determined, and the range of values in the screen are scaled or normalized to that the range of values can be displayed and provide the desired viewing characteristic. Linear and non-linear scalings may be applied, and clipping may also be permitted so that dynamic range is not unduly taken up by a few relatively bright or dark pixels, and the dynamic range fits the conversion range of the digital-to-analog converter.
  • pixel colors are represented by floating point number so that they can span a very large dynamic range. Integer values though suitable once scaled to the display may not provide sufficient range given the manner the output intensities are computed to permit rescaling afterward.
  • the lights are represented as floating point values, as are the coordinate distances. Therefore, with conventional representations it is relatively easy for a scene to come out all black (dark) or all white (light) or skewed toward a particular brightness range with usable display dynamic range thrown away or wasted.
  • the computations are desirable maintained in floating point representations throughout, and the final scene is mapped using some scaling routine to bring the pixel intensity values in line with the output display and D/A converter capability.
  • Such scaling or normalization to the display device may involve operations such as an offset or shift of a range of values to a different range of values without compression or expansion of the range, a linear compress or expansion, a logarithmic compression, an exponential or power expansion, other algebraic or polynomial mapping functions, or combinations of these.
  • a look-up table having arbitrary mapping transfer function may be implemented to perform the output value intensity transformation.
  • the transformation is performed automatically under a set of predetermined rules.
  • a rule specifying pixel histogram based normalization may be implemented, or a rule specifying a Gaussian distribution of pixels, or a rule that linearly scales the output intensities with or without some optional intensity clipping.
  • mapping functions are merely examples, of the many input/output pixel intensity transformations known in the computer graphics and digital image processing arts.
  • VSP When a VSP is dispatched, it corresponds to a single primitive, and the z-buffered blend
  • the VSP (i.e., the Pixel Block) needs separate z-values for every sample in the VSP.
  • the VSP could include a z-reference-value and the partial derivatives of z with respect to x and y (mathematically, a plane equation for the z-values of the primitive). Then, this information is used in the z-buffered blend (i.e., the Pixel Block) to reconstruct the per-sample z-values, thereby saving bandwidth.
  • the stamp-based z-value description method is performed in the Cull Block, and per-sample z-values are generated from this description in the Pixel Block.
  • the Phong Lighting Block advantageously includes a plurality of processors or processing elements. During fragment color generation a lot of state is needed, fragments from a common object use the same state, and therefore desirably for at least reasons of efficiency a minimizing caching requirements, fragments from the same object should be processed by the same processor.
  • the Phong block cache will therefore typically store state for more than one object, and send appropriate state to the processor which is handling fragments from a common object. Once state for a fragment from a particular object is sent to a particular processor, it is desirable that all other fragments from that object also be directed to that processor.
  • the Mode Injection Unit assigns an object or material, and MIJ allocates cache in all down stream blocks.
  • the Phong unit keeps track of which object data has been cached in which Phong unit processor, and attempts to funnel all fragments belonging that same object to the same processor. The only optional exception to this occurs if there is a local imbalance, in which case the fragments will be allocated to another processor.
  • This object-tag-based resource allocation (alternatively referred to as material-tag-based resource allocation in other portions of the description) occurs relative to the fragment processors or fragment engines in the Phong unit.
  • the Phong unit is responsible for performing texture environment calculations and for selecting a particular processing element for processing fragments from an object. As described earlier, attempts are made to direct fragments from a common object to the same phong processor or engine. Independent of the particular texture to be applied, properties of the surfaces, colors, or the like, there are a number of choices and as a result changes in the processing environment. While dynamic microcode generation is described here relative to the texture environment and lighting, the incentive structure and procedure may more widely be applied to other types of microcode, machine state, and processing generally.
  • a microcode engine in the phong unit each time processing of a triangle strip is initiated, a change material parameters occurs, or a change almost anything that touches the texture environment happens, a microcode engine in the phong unit generates microcode and this microcode is treats as a component of pipeline state.
  • the microcode component of state is an attribute that gets cached just like other pipeline state. Treatment of microcode generated in this manner as machine state generally, and as pipeline state in a 3D graphics processor particularly, as substantial advantages.
  • the Phong unit includes multiple processors or fragment engines .
  • fragment engines here describes components in the Phong unit responsible for texture processing of the fragments, a different process than the interpolation occurring in the
  • the microcode is downloaded into the fragment engines so that any other fragment that would come into the fragment engine and needs the same microcode (state) has it when needed.
  • Different microcode may be downloaded into each one dependent on how the MIJ caching mechanism is operating. Dynamic microcode generation is therefore provided for texture environment and lighting
  • Generating variable scale bump maps involves one or both of two separate procedures: automatic basis generation and automatic gradient field generation.
  • Automatic gradient filed takes a derivative, relative to gray scale intensity, of a gray scale image, and uses that derivative as a surface normal perturbation to generate a bump for a bump map.
  • Automatic basis generation saves computation, memory storage in polygon memory, and input bandwidth in the process.
  • an s,t and surface normal are specified. But the s and t aren't color, rather they are two-dimensional surface normal perturbations to the texture map, and therefore a texture bump map.
  • the s and t are used to specify the directions in which to perturb the surface normals in order to create a usable bump map.
  • the s,t give us an implied coordinate system and reference from which we can specify perturbation direction.
  • Use of the s,t coordinate system at each pixel eliminates any need to specify the surface tangent and the bi-normal at the pixel location. As a result, the inventive structure and method save computation, memory storage and input bandwidth.
  • a set of per-pixel tile staging buffers exists between the PixelOut and the BKE block.
  • Each of these buffers has three state bits Empty, BkeDoneForPix, and PixcDoneForBke associated with it. These bits regulate (or simulate) the handshake between the PixelOut and Backend for the usage of these buffer. Both the backend and the PixelOut unit maintain current InputBuffer and OutputBuffer pointers which indicate the staging buffer that the unit is reading from or writing to.
  • the BKE block takes the next Empty buffer and reads in the data from the frame buffer memory (if needed, as determined by the RGBACIearMask, DepthMask, and StencilMask - if a set of bit planes is not cleared it is read into). After Backend is done with reading in the tile, it sets the BkeDoneForPix bit. PixelOut looks at the
  • BkeDoneForPix bit of the InputTile If this bit is not set, then pixelOut stalls, else it clears the BkeDoneForPix bit, and the color, depth, and/or stencil bit planes (as needed) in the pixel tile buffer and transfers it to the tile sample buffers appropriately.
  • the PixelOut unit resolves the samples in the rendered tile into pixels in the pixel tile buffers.
  • the backend unit (BKE) block transfers these buffers to the frame buffer memory.
  • Pixel buffers are traversed in order by the PixelOut unit.
  • PixelOut emits the rendered sample tile to the same pixel buffer that it came from.
  • the PixelOut unit sets the PixDoneForBke bit.
  • the BKE block can then take the pixel tile buffer with PixDoneForBke set, clears that bit and transfer it to the frame buffer memory. After the transfer is complete, the Empty bit is set on the buffer.
  • the Backend Unit is responsible for sending data and or signals to the CRT or other display device and includes a Digital-to-Analog (D/A) converter for converting the digital information to analog signals suitable for driving the display.
  • the backend also includes a bilinear interpolator, so that pixels from the frame buffer can be interpolated to change the spatial scale of the pixels as they are sent to the CRT display.
  • the pixel zooming during scanout does not involve rerendering it just scales or zooms (in or out) resolution on the fly. In one embodiment, the pixel zooming is performed selectively on a per window basis, where a window is a portion of the overall desktop or display area.
  • Conventional structures and methods provide an on-screen memory storage and an offscreen memory storage, each having for example, a color buffer, a z-buffer, and some stencil.
  • the 3D rendering process renders to these off-screen buffers.
  • the one screen memory corresponds to the data that is shown on the display.
  • the content of the off-screen memory is copied to the on-screen memory in what is referred to as a block transfer (BLT).
  • BLT block transfer
  • the inventive structure and method perform a "virtual" block transfer or virtual BLT by splicing the data in or reading the data from an alternate location.
  • a token in this context is an information item interposed between other items fed down the pipeline that tell the pipeline what the entries that follow correspond to. For example, if the x.y.z coordinates of a vertex are fed into the pipeline and they are 32-bit quantities, the tokens are inserted to inform the pipeline that the numbers that follow are vertex x,y,z values since there are no extra bits in the entry itself for identification. The tokens that tell the pipeline hardware how to interpret the data that's being sent in.
  • Figure 1 is a diagrammatic illustration showing a tetrahedron, with its own coordinate axes, a viewing point's coordinate system, and screen coordinates
  • Figure 2 is a diagrammatic illustration showing a conventional generic renderer for a 3D graphics pipeline.
  • Figure 3 is a diagrammatic illustration showing an embodiment of the inventive 3- Dimensional graphics pipeline, particularly showing th relationship of the Geometry Engine 3000 with other functional blocks and the Application executing on the host and the Host Memory.
  • Figure 4 is a diagrammatic illustration showing a first embodiment of the inventive 3- Dimensional Deferred Shading Graphics Pipeline.
  • Figure 5 is a diagrammatic illustration showing a second embodiment of the inventive 3- Dimensional Deferred Shading Graphics Pipeline.
  • Figure 6 is a diagrammatic illustration showing a third embodiment of the inventive 3- Dimensional Deferred Shading Graphics Pipeline.
  • Figure 7 is a diagrammatic illustration showing a fourth embodiment of the inventive 3- Dimensional Deferred Shading Graphics Pipeline.
  • Figure 8 is a diagrammatic illustration showing a fifth embodiment of the inventive 3-
  • Figure 9 is a diagrammatic illustration showing a sixth embodiment of the inventive 3- Dimensional Deferred Shading Graphics Pipeline.
  • Figure 10 is a diagrammatic illustration showing considerations for an embodiment of conservative hidden surface removal.
  • Figure 11 is a diagrammatic illustration showing considerations for alpha-test and depth- test in an embodiment of conservative hidden surface removal.
  • Figure 12 is a diagrammatic illustration showing considerations for stencil-test in an embodiment of conservative hidden surface removal.
  • Figure 13 is a diagrammatic illustration showing considerations for alpha-blending in an embodiment of conservative hidden surface removal.
  • Figure 14 is a diagrammatic illustration showing additional considerations for an embodiment of conservative hidden surface removal.
  • Figure 15 is a diagramatic illustration showing an exemplary flow of data through blocks of an embodiment of the pipeline.
  • Figure 16 is a diagramatic illustration showing the manner in which an embodiment of the Cull block produces fragments from a partially obscured triangle.
  • Figure 17 is a diagramatic illustration showing the manner in which an embodiment of the Pixel block processes a stamp's worth of fragments.
  • Figure 18 is a diagramatic illustration showing an exemplary block diagram of an embodiment of the pipeline showing the major functional units in the front-end Command Fetch and Decode Block (CFD) 2000.
  • Figure 19 is a diagramatic illustration hightlighting the manner in which one embodiment of the Deferred Shading Graphics Processor (DSGP) transforms vertex coordinates.
  • DSGP Deferred Shading Graphics Processor
  • Figure 20 is a diagramatic illustration hightlighting the manner in which one embodiment of the Deferred Shading Graphics Processor (DSGP) transforms normals, tangents, and binormals.
  • DSGP Deferred Shading Graphics Processor
  • FIG 21 is a diagrammatic illustration showing a functional block diagram of the Geometry Block (GEO).
  • GEO Geometry Block
  • Figure 22 is a diagrammatic illustration showing relationships between functional blocks on semiconductor chips in a three-chip embodiment of the inventive structure.
  • Figure 23 is a diagramatic illustration exemplary data flow in one embodiment of the Mode
  • Figure 24 is a diagramatic illustration showing packets sent to and exemplary Mode Extraction Block.
  • Figure 25 is a diagramatic illustration showing an embodiment of the on-chip state vector partitioning of the exemplary Mode Extraction Block.
  • Figure 26 is a diagrammatic illustration showing aspects of a process for saving information to polygon memory.
  • Figure 27 is a diagrammatic illustration showing an exemplary configuration for polygon memory relative to MEX.
  • Figure 28 is a diagrammatic illustration showing exemplary bit configuration for color information relative to Color Pointer Generation in the MEX Block.
  • Figure 29 is a diagrammatic illustration showing exemplary configuration for the color type field in the MEX Block.
  • Figure 30 is a diagrammatic illustration showing the contents of the MLM Pointer packet stored in the first dual-oct of a list of point list, line strip, triangle strip, or triangle fan.
  • Figure 31 shows a exemplary embodiment of the manner in which data is stored into a Sort Memory Page including the manner in which it is divided into Data Storage and Pointer Storage.
  • Figure 32 shows a simplified block diagram of an exemplary embodiment of the Sort Block.
  • Figure 33 is a diagrammatic illustration showing aspects of the Touched Tile calculation procedure for a tile ABC and a tile ceneterd at ( ⁇ , y T ⁇ e ).
  • Figure 34 is a diagrammatic illustration showing aspects of the touched tile calculation procedure.
  • Figures 35A and 35B are diagrammatic illustrations showing aspects of the threshold distance calculation in the touched tile procedure.
  • Figure 36A is a diagrammatic illustration showing a first relationship between positions of the tile and the triangle for particular relationships between the perpendicular vector and the threshold distance.
  • Figure 36B is a diagrammatic illustration showing a second relationship between positions of the tile and the triangle for particular relationships between the perpendicular vector and the threshold distance.
  • Figure 36C is a diagrammatic illustration showing a third relationship between positions of the tile and the triangle for particular relationships between the perpendicular vector and the threshold distance.
  • Figure 37 is a diagrammatic illustration showing elements of the threshold distance determination including the relationship between the angle of the line with respect to one of the sides of the tile.
  • Figure 38A is a diagrammatic illustration showing an exemplary embodiment of the SuperTile Hop procedure sequence for a window having 252 tiles in an 18x14 array.
  • Figure 39 is a diagrammatic illustration showing DSGP triangles arriving at the STP Block and which can be rendered in the aliased or anti-aliased mode
  • Figure 40 is a diagrammatic illustration showing the manner in which DSGP renders lines by converting them into quads and various quads generated for the drawing of aliased and anti- aliased lines of various orientations.
  • Figure 41 is a diagrammatic illustration showing the manner in which the user specified point is adjusted to the rendered point in the Geometry Unit.
  • Figure 42 is a diagrammatic illustration showing the manner in which anti-aliased line segments are converted into a rectangle in the CUL unit scan converter that rasterizes the parallelograms and triangles uniformly.
  • Figure 43 is a diagrammatic illustration showing the manner in which the end points of aliased lines are computed using a parallelogram, as compared to a rectangle in the case of antialiased lines.
  • Figure 44 is a diagrammatic illustration showing the manner in which rectangles represent visible portions of lines.
  • Figure 45 is a diagrammatic illustration showing the manner in which a new line start-point as well as stipple offset stplStartBit is generated for a clipped point.
  • Figure 46 is a diagrammatic illustration showing the geometry of line mode triangles
  • Figure 47 is a diagrammatic illustration showing an aspect of how Setup represents lines and triangles, including the vertex assignment.
  • Figure 48 is a diagrammatic illustration showing an aspect of how Setup represents lines and triangles, including the slope assignments.
  • Figure 49 is a diagrammatic illustration showing an aspect of how Setup represents lines and triangles, including the quadrant assignment based on the orientation of the line.
  • Figure 50 is a diagrammatic illustration showing how Setup represents lines and triangles, including the naming of the clip descriptors and the assignment of clip codes to verticies.
  • Figure 51 is a diagrammatic illustration showing an aspect of how Setup represents lines and triangles, including aspects of how Setup passes particular values to CUL.
  • Figure 52 is a diagrammatic illustration showing determination of tile coordinates in conjunction with point processing.
  • Figure 53 is a diagrammatic illustration of an exemplary embodiment of the Cull Block.
  • Figure 54 is a diagrammatic illustration of exemplary embodiments of the Cull Block sub- units.
  • Figure 55 is a diagrammatic illustration of exemplary embodiments of tag caches which are fully associative and use Content Addressible Memories (CAMs) for cache tag lookup.
  • CAMs Content Addressible Memories
  • Figure 56 is a diagrammatic illustration showing the manner in which mde data flows and is cached in portions of the DSGP pipeline.
  • Figure 57 is a diagrammatic illustration of an exemplary embodiment of the Fragment
  • Figure 58 is a diagrammatic illustration showing examples of VSPs with the pixel fragments formed by various primitives.
  • Figure 59 is a diagrammatic illustration showing aspects of Fragment Block interpolation using perspective corrected barycentric interpolation for triangles.
  • Figure 60 shows an example of how interpolating between vectors of unequal magnitude may result in uneven angular granularity and why the inventive structure and method does not interpolate normals and tangents this way.
  • Figure 61 is a diagrammatic illustration showing how the fragment x and y coordinates used to form the interpolation coefficients in the Fragment Block are formed
  • Figure 62 is a diagrammatic illustration showing an overview of texture array addressing.
  • Figure 63 is a diagrammatic illustration showing the Phong unit position in the pipeline and relationship to adjacent blocks.
  • Figure 64 is a diagrammatic illustration showing a block diagram of Phong comprised of several sub-units.
  • Figure 65 is a diagrammatic illustration showing a block diagram of the PIX block.
  • Figure 66 is a diagrammatic illustration showing the BackEnd Block (BKE) and units interfacing to it.
  • BKE BackEnd Block
  • Figure 67 is a diagrammatic illustration showing external client units that perform memory read and write through the BKE.
  • the pipeline takes data from the host computer's I/O bus, processes it, and sends it to the computer's display.
  • the pipeline is divided into twelve blocks, plus three memory stores and the frame buffer.
  • Figure 15 shows the flow of data through the pipeline 1000. The blocks that make up the pipeline are discussed below.
  • Command Fetch and Decode (CFD) 2000 handles communication with the host computer through the I/O bus. It converts its input into a series of packets, which it passes to the Geometry block. Most of the input stream consists of geometrical data — lines, points, and polygons. The descriptions of these geometrical objects can include colors, surface normals, texture coordinates, and so on. The input stream also contains rendering information, such as lighting, blending modes, and buffer functions.
  • the Geometry block 3000 handles four major tasks: transforms, decomposition of all polygons into triangles, clipping, and per-vertex lighting calculations needed for Gouraud shading.
  • the Geometry block transforms incoming graphics primitives into a uniform coordinate space ("world space"). Then it clips the primitives to the viewing volume, or frustum.
  • the DSGP pipeline provides six user-definable clipping planes. After clipping, the Geometry block breaks polygons with more than three vertices into sets of triangles, to simplify processing.
  • the Geometry block calculates the vertex colors that the Fragment block uses to perform the shading.
  • the Mode Extraction block 4000 separates the data stream into two parts: 1 ) vertices, and 2) everything else. Vertices are sent to the Sort block.
  • the "everything else” lights, colors, texture coordinates, and so on — is stored in a special buffer called the Polygon Memory, where it can be retrieved by the Mode Injection block.
  • the Polygon Memory is double buffered, so the Mode Injection block can read data for one frame, while the Mode Extraction block is storing data for the next frame.
  • the mode data stored in the Polygon Memory falls into three major categories: per- frame data (such as lighting), per-primitive data (such as material properties) and per-vertex data (such as color). The Mode Extraction and Mode Injection blocks further divide these categories to optimize efficiency.
  • the Mode Extraction block sends the Sort block a packet containing the vertex data and a pointer into the Polygon Memory.
  • the pointer is called the color pointer, which is somewhat misleading, since it is used to retrieve all sorts of other information besides color.
  • the packet also contains fields indicating whether the vertex represents a point, the endpoint of a line, or the corner of a triangle.
  • the vertices are sent in a strict time sequential order, the same order in which they were fed into the pipeline.
  • the packet also specifies whether the current vertex forms the last one in a given primitive (i.e., "completes" the primitive). In the case of triangle strips or fans, and line strips or loops, the vertices are shared between adjacent primitives. In this case, the packets indicate how to identify the other vertices in each primitive.
  • the Sort block 6000 receives vertices from the Mode Extraction block and sorts the resulting points, lines, and triangles by tile.
  • the double-buffered Sort Memory 7000 it maintains a list of vertices representing the graphic primitives, and a set of Tile Pointer Lists-one list for each tile in the frame.
  • the Sort block adds a pointer to the vertex to that tile's Tile Pointer List.
  • Sort block When the Sort block has finished sorting all the geometry in a frame, it sends the data to Setup.
  • Each Sort block output packet represents a complete primitive. Sort sends its output in tile- by-tile order: all of the primitives that touch a given tile, then all of the primitives that touch the next tile, and so on. Note that this means that Sort may send the same primitive many times, once for each tile it touches.
  • the Setup block 8000 calculates spatial derivatives for lines and triangles. It processes one tile's worth of data, one primitive at a time. When it's done with a primitive, it sends the data on to the Cull block.
  • the Setup block also breaks stippled lines into separate line segments (each a rectangular region), and computes the minimum z value for each primitive within the tile.
  • Each primitive packet output from Setup represents one primitive: a triangle, line segment or point.
  • the Cull block 9000 is one of the more complex blocks, and processing is divided into two steps: Magnitude Comparison Content Addressable Memory (MCCAM) Cull, and Subpixel Cull.
  • MCCAM Magnitude Comparison Content Addressable Memory
  • Subpixel Cull The Cull block accepts data one tile's worth at a time.
  • the MCCAM Cull discards primitives that are hidden completely by previously processed geometry.
  • the Subpixel Cull takes the remaining primitives (which are partly or entirely visible), and determines the visible fragments.
  • the Subpixel Cull outputs one stamp's worth of fragments at a time, called a Visible Stamp Portion (VSP).
  • VSP Visible Stamp Portion
  • Figure 16 shows an example of how the Cull block produces fragments from a partially obscured triangle.
  • a Visible Stamp Portion produced by the Cull block contains fragments from only a single primitive, even if multiple primitives touch the stamp. Therefore, in the diagram, the output VSP contains fragments from only the gray triangle.
  • the fragment formed by the tip of the white triangle is sent in a separate VSP, and the colors of the two VSPs are combined later, in the Pixel block.
  • Each pixel in a VSP is divided up into a number of samples to determine how much of the pixel is covered by a given fragment. The Pixel block uses this information when it blends the fragments to produce the final color for the pixel.
  • MIJ Mode Injection
  • the Mode Injection block 10000 retrieves mode information —such as colors, material properties, and so on — from the Polygon Memory 5000 and passes it downstream as required.
  • mode information such as colors, material properties, and so on — from the Polygon Memory 5000 and passes it downstream as required.
  • the individual downstream blocks cache recently used mode information.
  • Mode Injection block keeps track of what information is cached downstream, and only sends information as necessary.
  • the Fragment block 11000 is somewhat misleadingly named, since its main work is interpolation. It interpolates color values for Gouraud shading, surface normals for Phong shading and texture coordinates for texture mapping. It also interpolates surface tangents for use in the bump mapping algorithm, if bump maps are in use.
  • the Fragment block performs perspective corrected interpolation using barycentric coefficients.
  • the Texture block 12000 applies texture maps to the pixel fragments. Texture maps are stored in the Texture Memory 13000. Unlike the other memory stores described previously, the Texture Memory is single-buffered. It is loaded from the host computer's memory using the AGP interface. A single polygon can use up to four textures. Textures are mip-mapped. That is, each texture comprises a series of texture maps at different levels of detail, each map representing the appearance of the texture at a given distance from the eye point. To produce a texture value for a given pixel fragment, the Texture block performs tri-linear interpolation from the texture maps, to approximate the correct level of detail. The Texture block also performs other interpolation methods, such as anisotropic interpolation.
  • the Texture block supplies interpolated texture values (generally as RGBA color values) to the Phong block on a per-fragment basis.
  • Bump maps represent a special kind of texture map. Instead of a color, each texel of a bump map contains a height field gradient.
  • Phong block 14000 performs Phong shading for each pixel fragment. It uses the material and lighting information supplied by the Mode Injection block, the texture colors from the Texture block, and the surface normal generated by the Fragment block to determine the fragment's apparent color. If bump mapping is in use, the Phong block uses the interpolated height field gradient from the Texture block to perturb the fragment's surface normal before shading. 4.11 Pixel (PIX)
  • the Pixel block 15000 receives VSPs, where each fragment has an independent color value.
  • the Pixel block performs pixel ownership test, scissor test, alpha test, stencil operations, depth test, blending, dithering and logic operations on each sample in each pixel (see OpenGL Spec 1.1 , Section 4.1 , "Per-Fragment Operations," p. 109).
  • the Pixel block When the Pixel block has accumulated a tile's worth of finished pixels, it blends the samples within each pixel (thereby performing antialiasing of pixels) and sends them to the Backend, to be stored in the framebuffer.
  • Figure 17 demonstrates how the Pixel block processes a stamp's worth of fragments.
  • the Pixel block receives two VSPs, one from a gray triangle and one from a white triangle. It then blends the fragments and the background color to produce the final pixels. It weights each fragment according to how much of the pixel it covers-or to be more precise, by the number of samples it covers.
  • the Pixel Processing block performs stencil testing, alpha blending, and antialiasing of pixels. When it accumulates a tile's worth of finished pixels, it sends them to the Backend, to be stored in the framebuffer.
  • the Backend 16000 receives a Tile's worth of pixels at a time from the Pixel block, and stores them into the framebuffer 17000.
  • the Backend also sends a Tile's worth of pixels back to the Pixel block, because specific framebuffer values can survive from frame to frame. For example, stencil bit values can constant over many frames, but can be used in all those frames.
  • the Backend performs 2D drawing and sends the finished frame to the output devices. It provides the interface between the framebuffer and the computer monitor and video output.
  • the AGI block is responsible for implementing all the functionality mandated by the AGP and/or PCI specifications in order to send and receive data to host memory or the CPU. This block should completely encapsulate the asynchronous boundary between the AGP bus and the rest of the chip.
  • the AGI block should implement the optional Fast Write capability in the AGP 2.0 spec in order to allow fast transfer of commands by PIO.
  • the AGI block is connected to the Read/Write Controller, the DMA Controller and the Interrupt Control Registers on CFD.
  • the CFD block is the unit between the AGP interface and the hardware that actually draws pictures. There is a lot of control and data movement units, with little to no math. Most of what the CFD block does is to route data for other blocks. Commands and textures for the 2D, 3D, Backend, and Ring come across the AGP bus and are routed by the front end to the units which consume them. CFD does some decoding and unpacking of commands, manages the AGP interface, and gets involved in DMA transfers and retains some state for context switches. It is one of the leastsimilar, but most essential components of the DSGP system.
  • Figure 18 shows a block diagram of the pipeline showing the major functional units in the CFD block 2000.
  • the front end of the DSGP graphics system is broken into two sub-units, the
  • AGI block and the CFD block The rest of this section will be concerned with describing the architecture of the CFD block. References will be made to AGI, but they will be in the context of requirements which CFD has in dealing with AGI.
  • this functional unit uses the address that it receives to multiplex the data into the register or queue corresponding to that physical address
  • the decoder multiplexes data from the appropriate register to the AGI Block so that the read transaction can be completed.
  • the Read/Write Control can read or write into all the visible registers in the CFD address space, can write into the 2D and 3D Command Queues 2022, 2026 and can also transfer reads and writes across the Backend Input Bus 2036.
  • the Read/Write Decoder If the Read/Write Decoder receives a write for a register that is read only or does not exist, it must send a message to the Interrupt Generator 2016 which requests that it trigger an access violation interrupt. It has no further responsibilities for that write, but should continue to accept further reads and writes.
  • the Read/Write Decoder If the Read/Write Decoder receives a read for a register which is write only or does not exist, it must gracefully cancel the read transaction. It should then send a message to the Interrupt Generator to request an access violation interrupt be generated. It has no further responsibilities for that read, but should continue to accept reads and writes.
  • commands for the DSGP graphics hardware have variable latencies and are delivered in bursts from the host, several kilobytes of buffering are required between AGI and 2D.
  • This buffer can be several times smaller than the command buffer for 3D. It should be sized such that it smooths out inequalities between command delivery rate across AGI and performance mode command execution rate by 2D.
  • a 2D High water mark register exists which is programmed by the host with the number of entries to allow in the queue. When this number of entries is met or exceeded, a 2D high water interrupt is generated. As soon as the host gets this interrupt, it disables the high water interrupt and enables the low water interrupt. When there are fewer entries in the queue than are in the 2D low water mark register, a low water interrupt is generated. From the time that the high water interrupt is received to the time that the low water is received, the driver is responsible for preventing writes from occurring to the command buffer which is nearly full.
  • a 3D High water mark register exists which is programmed by the host with the number of entries to allow in the queue. When this number of entries is met or exceeded, a 3D high water interrupt is generated. As soon as the host gets this interrupt, it disables the high water interrupt and enables the low water interrupt. When there are fewer entries in the queue than are in the 3D low water mark register, a low water interrupt is generated. From the time that the high water interrupt is received to the time that the low water is received, the driver is responsible for preventing writes from occurring to the command buffer which is nearly full.
  • the command decoder 2034 is responsible for reading and interpreting commands from the 3D Cmd Queue 2026 and 3D Response Queue 2028 and sending them as reformatted packets to the GEO block.
  • the decoder performs data conversions for "fast" commands prior to feeding them to the GEO block or shadowing the state they change.
  • the 3D Command Decode must be able to perform format conversions.
  • the input data formats include all those allowed by the API (generally, al those allowed in the C language, or other programming language).
  • the output formats from the 3D Command Decode are limited to those that can be processed by the hardware, and are generally either floating point or "color" formats. The exact bit definition of the color data format depends on how colors are represented through the rest of the pipeline.
  • the Command Decode starts at power up reading from the 3D Command Queue.
  • the command decoder sends the command and data to the DMA controller 2018.
  • the DMA controller will begin transferring the data requested into the 3D response queue.
  • the 3D Command Decoder then reads as many bytes as are specified in the DMA command from the 3D Response Queue, interpreting the data in the response queue as a normal command stream. When it has read the number of bytes specified in the DMA command, it switches back to reading from the regular command queue. While reading from the 3D
  • This 3D command decoder is responsible for detecting invalid commands. Any invalid command should result in the generation of an Invalid Command Interrupt (see Interrupt Control for more details).
  • the 3D Command Decode also interprets and saves the current state vector required to send a vertex packet when a vertex command is detected in the queue. It also remembers the last 3 completed vertices inside the current "begin” (see OpenGL specification) and their associated states, as well as the kind of "begin” which was last encountered. When a context switch occurs, the 3D Command Decode must make these shadowed values available to the host for readout, so that the host can "re-prime the pipe” restarting the context later.
  • the CFD DMA Controller 2018 is responsible for starting and maintaining all DMA transactions to or from the DSGP card.
  • DSGP is always the master of any DMA transfer, there is no need for the DMA controller to be a slave.
  • the 2D Engine and the 3D Command Decode contend to be master of the DMA Controller. Both DMA writes and DMA reads are supported, although only the 2D block can initiate a DMA write.
  • DSGP is always master of a DMA.
  • a DMA transfer is initiated as follows.
  • a DMA command along with the physical address of the starting location, and the number of bytes to transfer is written into either the 2D or 3D command queue.
  • a DMA request with the data is sent to the DMA Controller.
  • the 2D unit begins to put data in the Write To Host Queue 2020.
  • the DMA controller finishes up any previous DMA, it acknowledges the DMA request and begins transferring data. If the DMA is a DMA write, the controller moves data from the Write To Host Queue either through AGI to system memory or through the Backend Input Bus to the framebuffer. If the DMA is a DMA read, the controller pulls data either from system memory through AGI or from the backend through the
  • the DMA Controller should try to maximize the performance of the AGP Logic by doing non-cache line aligned read/write to start the transaction (if necessary) followed by cache line transfers until the remainder of the transfer is less than a cache line (as recommended by the Maximizing AGP Performance white paper).
  • the 2D Response queue is the repository for data from a DMA read initiated by the 2D block. After the DMA request is sent, the 2D Engine reads from the 2D Response Queue, treating the contents the same as commands in the 2D Command Queue. The only restriction is if a DMA command is encountered in the response queue, it must be treated as an invalid command. After the number of bytes specified in the current DMA command are read from the response queue, the 2D Engine returns to reading commands from the 2D Command Queue. 5.2.2.7 3D Response Queue
  • the 3D Response queue is the repository for data from a DMA read initiated by 3D Command Decode. After the DMA request is sent, the command decode reads from the 3D Response Queue, treating the contents the same as commands in the 3D Command Queue. The only restriction is if a DMA command is encountered in the response queue, it must be treated as an invalid command. After the number of bytes specified in the current DMA command are read from the response queue, the 3D Command Decode returns to reading commands from the 3D Command Queue.
  • the write to host queue contains data which 2D wants to write to the host through DMA. After 2D requests a DMA transfer that is to go out to system memory, it fills the host queue with the data, which may come from the ring or Backend. Having this small buffer allows the DMA engine to achieve peak AGP performance moving the data.
  • Interrupts are generally used to indicate infrequently occurring events and exceptions to normal operation.
  • One of the Cause Registers is reserved for dedicated interrupts like retrace, and the other is for generic interrupts that are allocated by the kernel.
  • Interrupt Cause Registers there is an Interrupt Mask Register which determines whether an interrupt is generated when that bit in the Cause makes a 0 p 1 transition.
  • DSGP supports up to 64 different causes for an interrupt, a few of which are fixed, and a few of which are generic. Listed below are brief descriptions of each.
  • the retrace interrupt happens approximately 85-120 times per second and is raised by the Backend hardware at some point in the vertical blanking period of the monitor. The precise timing is programmed into the Backend unit via register writes over the Backend Input Bus.
  • the 3D FIFO high water interrupt rarely happens when the pipe is running in performance mode but may occur frequently when the 3D pipeline is running at lower performance.
  • the kernel mode driver programs the 3D High Water Entries register that indicates the number of entries which are allowed in the 3D Cmd Buffer. Whenever there are more entries than this are in the buffer, the high water interrupt is triggered. The kernel mode driver is then required to field the interrupt and prevent writes from occurring which might overflow the 3D buffer. In the interrupt handler, the kernel will check to see whether the pipe is close to draining below the high water mark. If it is not, it will disable the high water interrupt and enable the low water interrupt.
  • an interrupt is generated if the number of entries in the 3D FIFO is less than the number in the 3D Low Water Entries register. This signals to the kernel that the 3D FIFO has cleared out enough that it is safe to allow programs to write to the 3D FIFO again.
  • the kernel mode driver programs the 2D High Water Entries register that indicates the number of entries which are allowed in the 2D Cmd Buffer. Whenever there are more entries than this are in the buffer, the high water interrupt is triggered. The kernel mode driver is then required to field the interrupt and prevent writes from occurring which might overflow the 2D buffer. In the interrupt handler, the kernel will check to see whether the pipe is close to draining below the high water mark. If it is not, it will disable the high water interrupt and enable the low water interrupt.
  • Texture miss This interrupt is generated when the texture unit tries to access a texture that is not loaded into texture memory.
  • the texture unit sends the write to the Interrupt Cause Register across the ring, and precedes this write with a ring write to the Texture Miss ID register.
  • the kernel fields the interrupt and reads the Texture Miss ID register to determine which texture is missing, sets up a texture DMA to download the texture and update the texture TLB, and then clears the interrupt.
  • the GEO block is the first computation unit at the front end of the graphical pipeline. It deals mainly with per-vertex operations, like the transformation of vertex coordinates and normals.
  • the Frontend (i.e., AGI and CFD Blocks) deals with fetching and decoding the Graphics Hardware Commands.
  • the Frontend loads the necessary transform matrices, material and light parameters and other mode settings into the input registers of the GEO block.
  • the GEO block sends transformed vertex coordinates, normals, generated and/or transformed texture coordinates, and per-vertex colors, to the Mode Extraction and Sort blocks.
  • Mode Extraction stores the "color" data and modes in the Polygon memory.
  • Sort organizes the per-vertex "spatial" data by Tile and writes it into the Sort Memory.
  • the pipeline can operate in maximum performance mode when only a certain subset of its features is in use. In this mode, the GEO block carries out only a subset of all possible operations for each primitive. As more features are enabled, the pipeline moves through a series of lower-performance modes.
  • the Geometry engine reuses the available computational elements to process primitives at a slower rate for the non-performance mode settings. The mapping of features to performance modes is described in the following sections. 5.3.3 Functional Overview of the GEO Block
  • the GEO block operates on vertices that define geometric primitives: points, lines, triangles, quads, and polygons. It performs coordinate transformations and Gouraud shading operations on a per-vertex basis. Only during the Primitive Assembly phase does it group vertices together into lines and triangles (in the process, it breaks down quads and polygons into sets of triangles). It performs clipping and surface tangent generation for each primitive.
  • Each vertex is specified by a set of object coordinates (Xo, Yo, Zo, Wo).
  • the addition of the fourth coordinate enables the vertices to be expressed in homogeneous coordinates.
  • a series of transformations involving rotation, scaling and translation can be combined in a single transform matrix called the Model-View matrix.
  • the vertex object coordinates are transformed to vertex eye coordinates by multiplying them with the 4x4 Model- View matrix:
  • Figure 19 summarizes how the DSGP transforms vertex coordinates.
  • the GEO block may have to process a current normal, current texture coordinates, and current color for each vertex. Normals affect the lighting calculations.
  • the current normal is a three-dimensional vector (Nxo, Nyo, Nz ⁇ ). Texture coordinates determine how a texture image is mapped onto a primitive.
  • the GEO block transforms and renormalizes these as it does the normal. It can also generate these vectors if the user doesn't supply them.
  • the GEO block generates the tangent using the texture coordinates and the vertex eye coordinates, and the binormal from a cross product of the normal and the tangent.
  • the GEO block produces tangents and binormals needed for bump mapping at half rate.
  • Figure 20 summarizes how DSGP transforms normals, tangents, and binormals.
  • An overview of the Geometry Block (GEO) is provided in Figure 21.
  • Figure 22 is a diagrammatic illustration showing relationships between functional blocks on semiconductor chips in a three-chip embodiment of the inventive structure.
  • Vertex Colors When lighting is disabled, the current color determines the vertex color. When lighting is enabled, the GEO block uses the vertex normal, lighting and material parameters to evaluate the vertex color. The material colors can also be derived optionally from the current color. Colors are specified as four values: R, G, B, and A; or a single color index value. Colors are converted by CFD to floating point numbers before they are used in the GEO block. At the end of the vertex lighting evaluation, the resulting colors are clamped back into eight-bit fixed point representing a range of 0.0 to 1.0, inclusive.
  • Texture coordinates can also be generated using vertex coordinates or the normal instead of being provided by the user.
  • a transformation matrix can be optionally applied to the texture coordinates. Texture coordinates are specified using the homogeneous coordinates named s, f, r, and q.
  • the transformation matrix is a 4x4 matrix. In the performance case, the resulting q is 1 , r is ignored and s and t are used to access the texture map. At reduced performance, q is used to divide the texture coordinates for perspective scaling.
  • the texture coordinate r is used for three dimensional textures and shadows. Up to eight sets of texture coordinates are supported in the
  • GEO block Two texture coordinates can be transformed and transformed at half performance. Five texture coordinates can be handled at one-third of the full performance rate. Finally, all eight texture coordinates can be generated and transformed at quarter performance rate.
  • the GEO block compares vertex clip coordinates to the clip planes generate outcodes. It uses these outcodes to reject primitives that are outside the view volume (for example, if all of the vertices in a primitive are above the top clipping plane, the primitive is rejected). Some primitives can not be trivially rejected even if they are completely outside of the view volume. If the outcodes indicate that the primitive is entirely inside the view volume and doesn't intersect any clipping planes, the primitive is accepted and no further clipping calculations are required.
  • the window coordinates of the current vertex and previous vertices are used to determine the face direction of polygons and optionally perform back face culling.
  • the primary color includes the Ambient, the Emissive and the Diffuse components of the color, attenuated and highlighted by spotlights. It has Red, Green, Blue, and Alpha components (RGBA). All lights and the current material settings contribute to the primary color.
  • the Fragment block interpolates the primary and secondary colors separately.
  • the primary color is blended with the texture color before the secondary color is applied for a given fragment to determine the final pixel color.
  • the GEO block does not do any extra work.
  • the DSGP pipeline supports both Phong and Gouraud shading simultaneously for separate lights. This increases the total number of lights significantly using Gouraud and the quality of the lighting using up to eight Phong lights.
  • Phong uses the GEO block Primary and Secondary color output as the "current" colors for color material .
  • the Mode Extraction block (MEX) in conjunction with the Mode Injection (MIJ) block is responsible for the management of graphics state related information.
  • the state changes are incremental; that is, the value of a state parameter remains in effect until it is changed. Therefore, the applications only need to update the parameters that change.
  • the rendering is linear; that is, primitives are rendered in the order received. Points, lines, triangle strips, triangle fans, polygons, quads, and quad strips are examples of graphical primitives.
  • state changes are accumulated until the spatial information for a primitive is received, and those accumulated states are in effect during the rendering of that primitive.
  • rendering is deferred until after hidden surface removal.
  • Geometry (GEO) block receives the primitives in order, performs all vertex operations (transformations, vertex lighting, clipping, and primitive assembly), and sends the data down the pipeline.
  • the Sort block receives the time ordered data and bins it by the tiles it touches. (Within each tile, the list is in time order.)
  • the CUL block receives the data from the SRT block in tile order, and culls out parts of the primitives that definitely do not contribute to the rendered images.
  • the CUL block generates the VSPs.
  • a VSP corresponds to the visible portion of a polygon on the stamp.
  • the TEX and PHG units receive the VSPs and are responsible for the texturing and lighting of the fragments respectively.
  • the last block, i.e. the Pixel block consumes the VSPs and the fragment colors to generate the final picture.
  • a primitive may touch many tiles and therefore, unlike traditional rendering pipelines, may be visited many times (once for each tile it touches) during the course of rendering the frame.
  • the pipeline must remember the graphics state in effect at the time the primitive entered the pipeline, and recall it every time it is visited by the pipeline stages downstream from SRT.
  • MEX is a logic block between Geometry and Sort blocks that collects and saves the temporally ordered state change data, and attaches appropriate pointers to the primitive vertices in order to associate the correct state with the primitive when it is rendered.
  • the Mode Injection (MIJ) block is responsible for the retrieval of the state and any other information associated with the state pointer (in this document, generally called the MLM Pointer) when it is needed. It is also responsible for the repackaging of the information as appropriate. An example of the repackaging occurs when the vertex data in polygon memory is retrieved and bundled into triangle input packets for fragment.
  • MIJ Mode Injection
  • the graphics state affects the appearance of the rendered primitives. Different parts of the DSGP pipeline use different state information. Here, we are only concerned with the pipeline stages downstream from the GEO block. DSGP breaks up the graphics state into several categories based on how that state information is used by the various pipeline stages. The proper partitioning of the state is very important. It can affect the performance (by becoming bandwidth and access limited), size of the chips (larger caches and/or logic complications), and the pin count.
  • the MEX block is responsible for the following: 1. Receiving the data packets from Geometry.
  • the state saved in Polygon memory is the one used by the blocks downstream from MIJ, e.g. Fragment, Texture, Phong and Pixel blocks. This state is partitioned as described elsewhere in this description.
  • the MIJ is responsible for the following:
  • Polygon memory stores per-vertex data.
  • MIJ retrieves the required vertices (3 for triangle, 2 for line, and 1 for point primitives) from the polygon memory.
  • DSGP partitions the graphics state into a plurality of parts, and hereinafter seven parts is assumed. This is in addition to the per-vertex information stored for each primitive. This section provides an overview of the state information. 5.4.1.3.1 State and Spatial Data needed by Sort, Setup, and Cull
  • the VertexModes packet contains the mode information generated by the host computer (i.e., software) that MEX attaches to each spatial packet before it is passed on to the Sort block.
  • the VertexModes packet includes: line width, point size, line stipple information, and depth test operation control bits.
  • the Spatial packet contains the window coordinates of the vertex and other per-vertex information generated by the Geometry block such as the start bit for the stipple pattern for line primitives.
  • the spatial packet includes: window coordinates of the vertex, polygon winding, vertex reuse in polygon fans and strips, edge flags, and blending operation control bits (such as alpha test and alpha blending).
  • the vertex modes are generated by software.
  • Geometry block receives the cull modes and vertex modes from software. It sends cull and vertex modes to MEX as described above.
  • MEX construct a spatial packet for sort by attaching the vertex modes to the spatial packet.
  • Mf ⁇ X block also attaches state MLM Pointers to this packet before passing it on to the Sort block.
  • the MEX block collapses the line width and point width parameters into one parameter, since the primitive can not be both a point and a line at the same time. It uses the Sort primitive type to determine if the primitive is a point, a line or a polygon. If the primitive is a point it sends the point width down to Sort otherwise it sends the line width. Other fields are left untouched. 5.4.1.3.2 Texture parameters
  • Texturing has many parameters, especially when multiple textures are included, it is advantageous to have a multiplicity of texture packets.
  • the texture parameter packets contain information needed for retrieval and filtering of texels. This document assumes there are eight possible textures assigned to each vertex.
  • TexA parameter packet contains parameters for the first two textures and TexB parameter packet contains the same (per-texture) information for up to 6 additional textures.
  • This non- symmetrical partition is chosen because, in most cases, there will be only one or two textures active at a time. In some rare cases, more than two textures may be used. This helps keep the size of the texture parameter cache on-chip small.
  • the TexA and TexB packets are received from the Geometry unit.
  • Per-texture information includes: texture ID, number of texture dimensions (i.e., 1D, 2D, or 3D), texture size (i.e., width, height, and depth), texture boarder information, texture format, texture filter control bits, texture wrapping control bits, texture clamping control bits, level of detail control bits, and texture comparison operation control bits.
  • the TexA packet contains one or two of these entries and the TexB packet can contain up to 6 entries.
  • TexA and TexB packets are generated by the software and sent to MEX via the GEO block.
  • MEX manages TexA and TexB as two state partitions, and saves them in the Polygon memory. Each TexA and TexB state partition has a pointer associated with it. Mode Injection block retrieves these packets as needed later on. Geometry block does not use any of this information.
  • the Texture block Given the texture id, its (s, t, r) coordinates, and the mipmap level, the Texture block is responsible for retrieving the texels, unpacking and filtering the texel data as needed. Fragment block sends texture id, s, t, r, mip level, as well as the texture mode information to Texture block. Note that s, t, r, and mip level coming from Fragment are floating point values. For each texture, TEX block outputs one 36 bit texel value to PHG. Texture block does not combine the fragment and texture colors; that happens in the Phong block. Texture block needs the texture parameters and the texture coordinates. Texture parameters are obtained from the two texture parameter caches in the Texture block.
  • Fragment block uses the texture width and height parameters in the miplevel computation. Fragment uses the TextureDimension field to determine if the texture dimension and if it is enabled (0 means that the texture is disabled) and TexCoordSet to associate a coordinate set with it. 5.4.1.3.3 Lighting parameters
  • the "lighting" partition of the state contains information for a multiplicity of lights (hereinafter, this document assumes a maximum of 8 lights) used in fragment lighting computations as well as the global state affecting the lighting of a fragment such as the fog parameters etc.
  • Light cache packet includes the following per-light information: light type, attenuation constants, spotlight parameters, light positional information, and light color information (including ambient, diffuse, and specular colors).
  • the light cache packet also includes the following global lighting information: global ambient lighting, fog parameters, and number of lights in use.
  • a light cache entry is about 300 bytes, (approximately 300 bits for each of the eight lights plus 120 bits of global light modes).
  • the LightCache packet is generated by the software and sent to MEX via the GEO block.
  • MEX manages the LightCache packet as one of the state partitions, and saves it in the Polygon memory when necessary.
  • the LightCache state partition has a pointer associated with it.
  • Mode Injection block retrieves this packet from polygon memory as needed later on. Geometry block does not use any of this information.
  • per-light cache entries could be used rather than caching the entire lighting state. This would allow less data to be transmitted down the pipeline when there is a light parameter cache miss.
  • application programs would be provided "lighter weight" switching of lighting parameters when a single light is changed. This would, however, require additional complexity in management of the lighting state.
  • the material partition of the graphics state contains all the information about the material used in fragment lighting computation. Note that the fragment material state is different from the material state attached to the vertex of a primitive. The fragment-material state information is not used during the vertex lighting computations performed in the GEO block.
  • This packet includes: texture enable control bits (selection of active textures), texture environment parameters, material color parameters (emissive, ambient, diffuse, and specular colors, and shininess), shininess cutoff value, and color material parameters.
  • up to eight texels for each fragment can be received by the PHG from TEX.
  • the texels are received in the same order as the texture entries in the material state packet.
  • Pixel modes affect the per-fragment operations in the PIX block.
  • Software creates the pixel mode packet and it is sent to MEX via GEO.
  • MEX saves the packet in Polygon memory.
  • MIJ retrieves the packet, and sends it to the PIX block.
  • Pixel modes include the following information: frame buffer write masks (depth, color, and stencil masks), blending operations, depth function, stencil function, and scissor operations. Note that some of the information in this packet is the same as that included in the
  • VertexModes destined for SRT Software is responsible for duplicating the state information as needed in various mode packets.
  • the stipple packet specifies the polygon stipple pattern. It is efficient for the stipple pattern to be cached separately because it is not used often, and when used, does not change often. It is a large number of bytes (usually 128 bytes due to the need for 32 x 32 bit pattern), so to include it in any other parameter cache would add a large additional overhead to the associated packet.
  • the fragment block interpolates the supplied per-vertex data and generates the information needed for the blocks downstream from the Fragment block.
  • the interpolated parameters may consist of some or all of the possible parameters depending on the state pointer attached to the VSP.
  • the packet size stored into Polygon Memory is variable, depending on the number and type of parameters used for a particular vertex.
  • These parameters include: primitive type, vertex reuse to construct polygon fans and strips, undipped vertex x, y, and 1/w values, vertex eye coordinates (x eye , y eye , Z eye ), inverse perspective term, vertex primary and secondary colors, vertex normal vector, tangent vector, binormal vectors, and up to 8 sets of texture coordinates.
  • the normal, tangent, and binormal vectors can each be represented as either a single vector or as a unit vector (i.e., the vector's direction) and a corresponding magnitude.
  • Unclipped vertex x, y, and 1/w values are particularly useful because interpolated primitive parameters (such as colors, normals, texture coordinates, etc.) can be generated from the original vertex parameters of the primitive, even if the primitive gets clipped to the display screen.
  • interpolated primitive parameters such as colors, normals, texture coordinates, etc.
  • new vertices are created in order to keep all primitives on-screen. This would usually require all vertex parameters to be interpolated at these new vertex locations (along the display screen edges), which is an expensive set of operations.
  • the interpolation of these parameters at clip-generated vertices is avoided by storing clipped values into Sort Memory (i.e., the spatial x, y, and z values), but storing undipped vertex parameters into Polygon Memory.
  • Sort Memory i.e., the spatial x, y, and z values
  • the Geo block separates the normal, tangent, and binormal vectors into separate direction and magnitude makes it easy to interpolate the direction separately from the magnitude. Interpolating the direction separately from the magnitude provides a truer angular interpolation, especially when the magnitudes of the original vectors (i.e., the vectors at the vertices) differ by a large factor.
  • the Geo block generates per-vertex information that is stored in polygon memory.
  • MIJ block is responsible for retrieving the needed state and vertices from the polygon memory in order to reconstruct the primitive that includes the VSP.
  • triangle vertex texture coordinates are sent to Fragment unit and not the texture unit.
  • the texture unit receives the interpolated and perspective corrected texture coordinates for each fragment from the Fragment block.
  • MEX receives a sequence of packets from GEO. For each primitive, MEX first receives the relevant state packets and then it receives the geometry packets. (Color vertex information is received before the sort vertex information.)
  • the sort vertex data consists of the information needed for sorting and culling of primitives such as the clipped window coordinates.
  • the VtxMode packet contains information about depth test etc. The information in CullMode, VtxMode and sort vertex packets is sent to the Sort-Setup-Cull part of the pipeline.
  • the "color" vertex data consists of information needed for lighting and texturing of primitive fragments such as the vertex eye- coordinates, vertex normals, texture coordinates etc and is saved in polygon memory to be retrieved later.
  • the Sort-Setup-Cull part of the pipeline converts the primitives into VSPs. These VSPs are then textured and lit by the Fragment-Texture-Phong part of the pipeline.
  • the VSPs output from the Cull block to MIJ block are not necessarily ordered by primitives. In most cases, they will be in the VSP scan order on the tile, i.e. the VSPs for different primitives may be interleaved.
  • Fragment-Texture-Phong part of the pipeline needs to know which primitive a particular VSP belongs to; as well as the graphics state at the time that primitive was first introduced. MEX associates a "color pointer" with each Sort Vertex (which is then passed on to each VSP in this primitive).
  • MIJ decodes the pointer, and retrieves needed information from the Polygon memory.
  • MEX thus needs to accumulate any state changes that have happened since the last state save. The state changes become effective as soon as a vertex is encountered.
  • MEX keeps a state vector on chip. This state vector has 10 partitions as shown in Figure 25. MEX needs nearly 1170 bytes of on-chip memory to store the state vector.
  • the VertexModes are held in a register in MEX and are appended to the vertices passed on to the Sort-Setup-Cull part of the pipeline.
  • the CullModes are sent to Sort as Mex2SrtCullModePkt.
  • MEX keeps a dirty bit and a pointer (in polygon memory) for each partition in the state vector. Thus there are 10 dirty bits and 9 mode pointers, since cull modes do not get saved in the polygon memory and therefore do not require a pointer. Every time MEX receives an input packet corresponding to a state partition from the Geo block, it updates that partition in the state vector. MEX also sets the dirty bit corresponding to that partition.
  • MEX When MEX receives a color vertex, it examines the dirty bits to see if any part of the state has been updated since the last save. All state partitions that have been updated and are relevant to the rendering of the current primitive are saved to the polygon memory and their pointers updated. Their dirty bits are also cleared. Note that the dirty bits are only cleared for the primitives that are saved to the polygon memory. Which TextureA, TextureB, and Material gets saved to the polygon memory depends on the "face" of the primitive and the dirty bits. This is schematically outlined in Figure 26.
  • MEX constructs a composite color pointer called the MLM Pointer containing the pointer to the last saved location of the applicable TextureA, TextureB, Material, Light, Stipple, and PixelMode. This pointer is attached to the vertices passed on to the Sort block.
  • PixelModes are dirty. If PixelMode dirty bit is set, then MEX saves the PixModes to polygon memory, updates the PixModePtr, clears the PixMode dirty bit, creates a new MLM Pointer and attaches that pointer to the clear packet before passing it on to the Sort block.
  • Geometry block are illustrated in the figures. Note that, we use “mesh” to indicate a new sequence of points following a change in state. A “mesh” can thus be a sequence of points, line strip, line segments, or a triangle list or fan.
  • the polygon memory can be viewed as a linear array of dual-octs.
  • the primitive data is filled in from the top of the memory heap and the mode data from the bottom of the heap. All writes to the memory are in 144-bit words (or 1 dual-oct).
  • the polygon memory layout would look something like the Figure 27. Some things to note are that 1.
  • the partitions in the state vector undergo a lazy save in polygon memory. We only save what we need.
  • the color offset is 8 bits, therefore can be at most 256 vertices in a mesh.
  • MEX keeps current vertexPointer, vertexCount, and the previous (up to) two vertices needed to complete the primitive. It also keeps the modePointer.
  • the vertexPointer is the pointer to the current vertex entry in polygon memory.
  • VertexCount is the number of vertices saved in polygon memory since the last state change.
  • VertexCount is assigned to the ColorOffset.
  • VertexPointer is assigned to the colorPointer for the Sort primitives. Previous vertices are used during handling of memory overflow.
  • MIJ uses the colorPointer, ColorOffset and the vertex size information (encoded in the ColorType received from Geo) to retrieve the MLM Pointers and the primitive vertices from the polygon memory. 5.4.2.3.1 Memory double buffering and overflow
  • Polygon memory can overflow.
  • Polygon memory and/or Sort memory will overflow if a single user frame contains too much information. The overflow point depends on the size of Polygon memory; the frequency of material, mode, texture, and light changes in the frame; and the primitive features used. When memory fills up, all primitives will be flushed down the pipe and the user frame finished with another fill of the Polygon Memory buffer. Note that Sort memory overflow will trigger the same overflow mechanism. Polygon memory and Sort memory buffers must be kept consistent. Any skid in one memory due to overflow in the other must be backed out (or, better yet, avoided).
  • a frame break due to overflow may result due to a signal from Sort that a Sort memory overflow occurred or due to memory overflow in MEX itself.
  • a Sort memory overflow signal in MEX is handled in the same way as an overflow in MEX polygon memory itself.
  • the elapsed time before ME ⁇ X can start processing the next frame in the sequence is (time taken by MEX for the full frame + CUL tiie latency + MIJ frame processing for the full frame) and not (time taken by MEX for the full frame + time taken by MEX for the overflow frame).
  • the elapsed time is nearly twice the time for a normal frame.
  • the only way to reduce this cost is for software to get an estimate of the scene size, and break the frame in two roughly equally complex frames.
  • the hardware can implement a policy where we create an overflow only when we have to.
  • Mode Extraction needs to store the triangle (and its state) that caused the overflow in the next buffer.
  • Overflow is also handled. MIJ sends a signal to MEX when done. Since Setup and Cull can start processing the primitives on a tile only after MEX and Sort are done, MIJ may stall waiting for the VSPs to start arriving.
  • MEX attaches a "colorPointer", a "colorOffset", and a "colorType” with every primitive vertex sent to Sort.
  • the "colorPointer” points to a vertex entry in the Polygon memory. This vertex entry is the vertex that completes the triangle (line, or point) that the Sort primitive is associated with.
  • the sort vertices V a , V b , V 2 are all assigned the color pointer corresponding to the color vertex V 3 , as the vertex V completes DV y , that ⁇ V,V a V b and ⁇ V,V b V 2 are associated with.
  • the vertex parameters i.e.
  • the "colorOffset" is the number of vertices separating the vertex at the colorPointer to the dual-oct that is used to store the MLM Pointer applicable to this primitive.
  • the color offset associated with V a , V b , and V 2 is the number of vertices separating stO and cv3, i.e. 3.
  • the "colorType" tells the MIJ how to retrieve the complete primitive from the Polygon. Vertices are stored in order, so the vertices in a primitive are adjacent, except in the case of triangle fans. For points, we only need the vertex pointed to by the colorPointer. For lines we need the vertex pointed to by ColorPointer and the vertex before this in the color vertex array. For triangle strips, we need the vertex at colorPointer and two previous vertices. For triangle fans we need the vertex at colorPointer, the vertex before that and the first vertex in the array after the MLM Pointer. In the example above, the sort primitive defined by vertex V 8 , MIJ will need to retrieve vertices V 5 , V 7 , and V 8 . Thus, for a triangle fan, the three vertices for the triangle are at
  • ColorPointer (ColorPointer -1 ), and at (ColorPointer - ColorOffset). Bits used for "color" information are shown in Figure 28.
  • the Color Type field is constructed from the "vertexType" in input packet header and the vertex packet length. It specifies both the size of the packet and the type of primitive it belongs to.
  • the values for the color type field are listed in Figure 29.
  • Figure 30 shows the contents of the MLM Pointer packet stored in the first dual-oct of a list of point list, line strip, triangle strip, or triangle fan. 5.4.2.5 Processing of state
  • MEX does not need to know the contents of most of the packets received by it. It only needs to know their type and size. There are some exceptions to this rule.
  • MEX For "color" vertex packets, MEX needs to know the information about the primitive defined by the current vertex. In particular, MEX needs to know its type (point, line, triangle strip or fan) and if a triangle - whether it is front facing. This information is used in saving appropriate vertex entries on chip to be able to construct the primitive in case of an overflow. This information is encapsulated in the packet header by the Geometry block.
  • MEX accumulates Material and Texture data for both front and back faces of the triangle. Only one set of state is written to Polygon memory based on the "FrontFace" bit. Note that the front/back orientation does not change in a triangle strip or fan. The "FrontFace” is used to associate correct TextureA, TextureB parameters and the material objects with the primitive. If a mesh changes orientation in the middle, GEO will break it into two or more meshes such that each new mesh is either front facing or back facing.
  • MEX needs to be able to strip away one of the LineWidth and PointWidth attributes depending on the primitive type. If the vertex defines a point then LineWidth is thrown away and if the vertex defines a line, then PointWidth is thrown away. Mex passes down only one of the line or point width to the Sort unit.
  • the Sort Block is located in the pipeline between Mode Extraction (MEX) and Setup (STP).
  • the primary function of the Sort Block is to take geometry scattered around the display window and sort it into tiles.
  • the Sort Block manages the Sort Memory, which stores all the geometry for an entire scene before it is rasterized, along with a small amount of mode information.
  • the Sort Memory is a double buffered list of vertices and modes. One page collects a scene's geometry (vertex by vertex and mode by mode), while the other page is sending its geometry (primitive by primitive and mode by mode) down the rest of the pipeline.
  • the window (the display area on the screen) is divided horizontally and vertically into a set of tiles, and Sort keeps an ordered list for each tile.
  • Sort keeps an ordered list for each tile.
  • vertices and modes are written sequentially into the Sort Memory as they are received by the Sort Block.
  • a page of Sort Memory is read, it is done on a tile-by-tile basis.
  • the read process operates in two modes: 1 ) Time Order Mode; and 2) Sorted Transparency Mode.
  • Time Order Mode time order of vertices and modes are preserved within each tile. That is, for a given tile, vertices and modes are read in the same order as they are written.
  • Sorted Transparency Mode reading of each tile is divided into multiple passes, where, in the first pass, guaranteed opaque geometry is output from the Sort Block, and, in subsequent passes, potentially transparent geometry is output from the Sort Block.
  • the time ordering is preserved, and mode data is inserted in its correct time-order location.
  • the beginning of a frame is designated by the reception of a MEX Output Begin Frame Packet, and always corresponds to the start of a user frame (that is, the application is starting to draw a new picture). These begin frame packets are passed from Sort down the pipeline to Setup when Sort Memory Pages are swapped.
  • the ending of a frame is designated by the reception of a MEX Output End Frame Packet, but only corresponds to the end of a user frame if a memory overflow did not occur and software did not force the user frame to split.
  • a memory overflow occurs when either Sort Memory or Polygon Memory becomes full. Therefore, there are two kinds of end frame packets that come into the Sort Block: 1 ) end of a user frame; and 2) end of a frame caused by the need to split a user frame into multiple frames within the pipeline. The second half of the pipeline (Setup and beyond) will be asked to process a tile multiple times when a user frame is split into multiple frames. Because each frame is independent, and could be input from different contexts, all the pipeline state information must be stored into either Sort Memory (as mode packets) or Polygon Memory on a per-frame basis.
  • the Sort Block receives and outputs Sort Primitives, which are: points, lines, and triangles.
  • a Sort Primitive triangle can be either a filled triangle or a line mode triangle.
  • primitives are sorted according to Cull Primitives, which include: points, lines, filled triangles, and lines that are edges of triangles.
  • edges of line mode triangles are considered separate primitives. If a line mode triangle is received by the Sort Block, it is sorted according to the tiles its edges touch. Any edge of the triangle (that has its LineFlag TRUE) causes the entire triangle to be sorted into the tiles that the edge touches, but a triangle with multiple edges in the same tile only cause one Pointer Entry per tile. This reduces the number of primitives per tile, because, for example, if a large line mode triangle surrounds several tiles without any of its edges touching the tiles, no Cull Primitives are read for this triangle in these tiles.
  • the Cull Primitive is further described in the Setup Block document, but the CullType parameter is essentially the SortPrimitiveType parameter with an additional bit to choose amongst the three edges of a line mode triangle.
  • FIG 31 shows a simple example of data stored into a Sort Memory Page, including only six tiles and eight primitives.
  • each Sort Memory Page is divided in two: 1 ) Data Storage; and 2) Pointer Storage.
  • Data Storage stores its data in the received order, and stores two types of Storage Entries: 1) vertex packets and 2) mode packets.
  • Figure 31 shows thirteen (13) vertex packets and three mode packets.
  • Pointer Storage contains two types of lists: 1) Tile Pointer Lists, one for each tile; and 2) a Mode Pointer List.
  • the example in Figure 31 shows six Tiie Pointer Lists containing a total of 18 Vertex Pointers, and also shows the Mode Pointer List containing a Clear Pointer and three Cull Pointers.
  • the size of vertex packets and mode packets is always a single Rambus Dualoct.
  • the addresses shown in Figure 31 are Dualoct addresses.
  • each Vertex Pointer in a Tile Pointer List includes the address (i.e., pointer) in Data Storage of the last Sort Memory Vertex Packet of a Sort Primitive that includes a Cull Primitive that covers part of the corresponding tile.
  • the triangle completed by vertex 11 i.e., the Sort Memory Vertex Packet written into Dualoct address 11
  • touches three tiles, and a pointer to this vertex is added to the Tile Pointer List for the three touched tiles (tiles 2, 4, and 5).
  • each Vertex Pointer also includes an offset.
  • the Sort Primitive type is a point.
  • An example in Figure 31 is the point represented by vertex 16, forming the fourth Pointer Entry in Tile 5.
  • the primitive type is a line.
  • An example in Figure 31 is the line formed by vertex 14 and vertex 15, forming the first Pointer Entry in Tile 0 and the fourth Pointer Entry in Tile 2. In these two entries, the address field is 15, which points to the last vertex in the line. For lines, the other vertex is always the vertex at the immediately preceding address.
  • the Sort Primitive type is a triangle, and the offset is used to determine the location of the first vertex in the triangle.
  • vertex 12 is the third vertex of a triangle.
  • the second vertex is always the immediately prior address, in this example, vertex 11.
  • the first vertex is found by subtracting the offset from the address.
  • the offset is 4, and the first vertex is vertex 8 (i.e.,
  • each Vertex Pointer also includes a Transparent flag bit. This boolean variable is only used when the pipeline is in Sorted Transparency Mode.
  • the primitive When it is TRUE, the primitive is treated as possibly transparent; and when FALSE, indicates the primitive is guaranteed to be opaque.
  • "opaque” means the primitive completely obscures more distant geometry that occupies the same area in the window, in the example shown in Figure 31 , the triangles completed by vertices 9 through 11 have their Transparent bit set to TRUE, indicated by a T in the Vertex Pointers. These three triangles touch nine tiles, so there are nine entries with the "T indicator.
  • Mode Pointer List As mode packets are fed into the Sort Block and sequentially written into Data Storage, a single Mode Pointer List is constructed. Each entry in the Mode Pointer List is the address of a mode packet in Data Storage. There are two types of pointers, each with a corresponding mode packet type: 1 ) Clear Pointers, containing the address of a Sort Memory Clear Packet; and 2) Cull
  • Pointers containing the address of a Sort Memory Cull Packets.
  • Both Clear Pointers and Cull Pointers include the ModePktType parameter, indicating the type of mode packet.
  • Both pointer include is a boolean variable (SubFrameBreakOnClear and SubFrameBreakOnCull) that indicates the mode packet could cause a frame to be divided into SubFrames at that point. If the boolean variable is TRUE, and the current SubFrame already includes transparent geometry, then the frame is divided immediately prior to that mode packet. In the example shown in Figure 31 , one Cull Pointer has its SubFrameBreakOnCull bit set to TRUE, indicated by a "S" in that Cull Pointer. Clear Pointers also include another boolean, SendToPixel, indicating the buffer clear operation must occur in the Pixel block. During the reading of a Sort Memory Page, multiple vertices are assembled into Sort
  • Sort Memory In addition to vertex packets and mode packets, Sort Memory also stores data packets that are considered to be between user frames, called Tween Packets". Specifically, Tween Packets can only be input into the pipeline after software issues an end user frame and before software issues a begin user frame. From an architectural perspective, Tween Packets are not considered part of a Sort Memory Page. However, because there is no other place in Sort Memory to store data, Tween Packets are stored at the beginning of Data Storage within a Sort Memory Page by the Sort Write Process. Tween Packets are primarily used for 2D commands that need to be synchronized with a 3D frame. For example, if geometry is rendered to an offscreen buffer (a "p-buffer"), and then a stretch-Bit operation transfers the data to the frame buffer, this operation must occur between frames. Tween Packets are also used for all accumulation buffer operations.
  • p-buffer offscreen buffer
  • Figure 32 shows a simplified block diagram of the Sort Block.
  • Figure 32 shows double buffered state registers. These registers store the parameters of the frames being written and read. Parameters include: number of tiles horizontally, number of tiles vertically, whether the target draw buffer is double buffered, whether the target draw buffer is stereo, whether the frame is in Time Order Mode or Sorted Transparency Mode, sample location selection within pixels, sample weighting, and whether the frame was caused by an overflow in either Sort Memory or Polygon Memory.
  • tiles are independent, and can be read in any order.
  • tile groups called “supertiles” are read sequentially.
  • the number of tiles per supertile is selectable, but we expect to always select 2 x 2 tiles per supertile.
  • supertiles are not read either row-by-row or column-by-column. Rather, supertiles are read in a spatially staggered
  • the left and right buffers are considered separate, each with a separate set of tiles.
  • a 1024 x 768 window has 64 x 48 tiles (3072 tiles total), but a stereo window has 2 x 64 x 48 tiles (6144 tiles total), and has two tiles at each (x, y) location (one for left and one for right).
  • both front and back must be sent down the pipeline during both passes.
  • the same starting depth and stencil values must be used for both passes. Therefore, the back and front passes for a give tile must occur consecutively (i.e., no other tiles in between) so that the Back End can load the same initial depth and stencil values from the frame buffer into consecutive tile buffers in the Pixel Block. If the pass for the back buffer were to complete before the initial loading of the pass for the front buffer, then a rendering error could occur. The Backend must guarantee this.
  • Sort Memory Page Approximately half of a Sort Memory Page is used for pointers. Therefore, the number of bytes needed in Sort Memory is approximately 64 times the maximum number of vertices (mode packets don't contribute much). Each vertex requires 16 bytes, pointers requires an additional 16 bytes, and there are two pages required.
  • the Sort Block keeps track of several performance meters, such as the number of triangles in each frame. Please see the subsection “Performance Metering Capabilities, Readable from the Host", in the section "Output from the Sort Block”. 5.5.2 Sort Block Functional Details
  • the Sort block includes two processes the operation in parallel: 1 ) the Sort Write Process; and 2) the Sort Read Process.
  • the Sort Write Process is the "master" of the two, because it initiates the Sort Read Process when writing is completed and the read process is idle.
  • the pseudo-code assumes all the variables are "global”. Other functional details are included in this section, such as Touched Tile Calculation, which determines which tiles are touched by a primitive.
  • the Sort Write Process creates a sequential list of vertex and mode packets in Data Storage (see Figure 31).
  • the Sort Write Process also creates a Tile Pointer List per tile and one Mode Pointer List per frame.
  • the Sort Read Process generates output packet sequences in a strict tile-by-tile fashion, and left tiles and right tiles are treated separately. 5.5.2.2.1 Sort Read Process Outer Control Loop
  • the outer control loop of the Sort Read Process includes three functional components: 1 ) TimeOrderMode; 2) Sorted Transparency Mode OpaqueLoop(); and 3) SortedTransparency Mode TranspLoopO, Each of these are described in the following sections.
  • Caching of mode packets should be done on a FILO basis, because the first mode packets will be output in every tile. Also, the caching mechanism should look ahead at least two mode packets to prevent address comparisons (to determine time ordering) that choose the mode packet from injecting bubbles into the processing.
  • Sorted Transparency Mode during the multiple passes for transparent geometry. Sort Memory Clear Packets are always skipped during transparency processing.
  • StencilMode has set the window in 2-bit stencil mode
  • software replicates the two least significant bits of StencilMask and StencilValue across all eight bits.
  • Software also takes into account OpenGL DepthMask when setting the value of ClearDepth. This is because the Backend block does not check DepthMask when doing a clear.
  • CullFlushAIIReg is the only signal that is actually "accumulated”. SoftSubFrameBreak and OnlySoftSubFrameBreak are not used by the Sort Read Process, but are included in the Sort
  • each line in the triangle divides the plane into two half-planes: an interior half-plane, and an exterior half- plane. If the Tile is entirely within the exterior half-plane defined by any of the lines then it is not touched by the triangle. To be touched by the triangle, the Tiie must be at least partly contained in all three interior half-planes.
  • the touched tile calculation is also applied to lines, however, line stippling is ignored for purposes of the touched tile calculation.
  • the sequence in which tiles are processed (called the "SuperTile Hop Sequence") is controlled by SuperTiieStep, also included in the MEX Output Begin Frame packet.
  • Figure 38A describes a simple example of the SuperTile Hop Sequence.
  • the example shows a window 6202 composed of 252 tiles in an 18x14 array.
  • the SuperTileSize is assumed to be 2x2 tiles (but can be any size, including 1x1 , 1x2, 2x1 , 2x2, 2x3, 3x2, 3x3, 3x4, 4x3, or 4x4), so there are 63 SuperTiles in a 9x7 array.
  • the list of SuperTiles is considered to converted to a linear list, which can be done by numbering the Supertiles in a row-by-row manner starting in the upper left. Define the following variables:
  • N number of SuperTiles in the window
  • M SuperTiieStep
  • T n n th SuperTile to be processed
  • M be less than N.
  • This iterative algorithm will hit every SuperTile as long as N and M are mutually prime (that is, their greatest common factor is 1). Neither N nor M need to be prime numbers, but if M is always selected to be a prime number, then every SuperTile will be hit.
  • the Sort block is sorting Sort Primitives (not Cull Primitives).
  • LineMode is TRUE
  • one or more bits in the LineFlags parameter is TRUE
  • the triangle is to be drawn as one or more lines, rather than as a filled triangle.
  • the three bits represent: 1 ) bit 0 (the LSB) corresponds to the edge between vertices 0 and 1 ; 2) bit 1 corresponds to the edge between vertices 1 and 2; and 3) bit 2 (the MSB) corresponds to the edge between vertices 2 and 0.
  • the LineFlags parameter is set in the GEO block because it is the part of the pipeline that determines which vertices complete polygons, and also because it is responsible for clipping.
  • the three LineFlags bits independently control their corresponding edge because some edge lines should not be drawn. For example, an OpenGL quadrilateral is always split into two triangles, but when drawn in line mode, the edges interior to the quadrilateral are not drawn.
  • lines are drawn as an antialiased rectangle whose width is specified as a number of pixel widths, and whose length is the distance between the endpoints.
  • these lines can be stippled, which breaks the rectangle into a series of antialiased squares along its length, and each square can be designated to be either colored in the usual way or completely transparent. Stippled lines can be thought of as fancy dashed lines.
  • the Setup (STP) block receives a stream of packets from the Sort (SRT) block. These packets have spatial information about the primitives to be rendered.
  • the output of the STP block goes to the Cull (CUL) block.
  • the primitives received from SRT can be filled triangles, line triangles, lines, stippled lines, and points. Each of these primitives can be rendered in aliased or anti-aliased mode.
  • the SRT block sends primitives to STP (and other pipeline stages downstream) in tile order. Within each tile the data is organized in time order or in sorted transparency order.
  • the CUL block receives data from the STP block in tile order (in fact in the order that STP receives primitives from SRT), and culls out parts of the primitives that definitely do not contribute to the rendered images. This is accomplished in two stages.
  • the first stage, MCCAM Cull allows detection of those elements in a rectangular memory array whose content is greater than a given value.
  • the second stage refines on this search by doing a sample by sample content comparison.
  • the STP block prepares the incoming primitives for processing by the CUL block.
  • STP produces a tight bounding box and minimum depth value Zmin for the part of the primitive intersecting the tile for MCCAM culling.
  • MCCAM cull stage marks the stamps in the bounding box that may contain depth values less than Zmin.
  • the Z cull stage takes these candidate stamps, and if they are a part of the primitive, computes the actual depth value for samples in that stamp. This more accurate depth value is then used for comparison and possible discard on a sample by sample basis.
  • STP also computes the depth gradients, line slopes, and other reference parameters such as depth and primitive intersection points with the tile edge for the Z cull stage.
  • the CUL unit produces the VSPs used by the other pipeline stages. To set the context, we briefly describe various STP primitives.
  • Polygons arriving at the STP block are essentially triangles.
  • the triangles can be rendered in the aliased or anti-aliased mode.
  • Figure 39 shows DSGP triangles.
  • the STP unit processes the aliased and anti-aliased triangles identically.
  • the pipeline units downstream render aliased triangles by locating all samples at the center of the pixel. In the anti-aliased case the sample locations are determined by the SampleLocSel parameters passed down with one of the control packets.
  • a sample belongs to the triangle if it falls within the geometric boundary of the triangle. If the sample falls exactly on the edge of the triangle, then the inclusion rules are used to determine whether or not that sample belongs to the triangle. 5.6.0.2 Lines
  • DSGP renders lines by converting them into quads.
  • Figure 40 shows various quads generated for the drawing of aliased and anti-aliased lines of various orientations.
  • the width of the lines is rounded to the nearest supported width. The width adjustment needs to be done prior to the SORT stage. It can be done by the software. STP does not modify the incoming line widths.
  • the quads are generated differently for aliased and anti-aliased lines. For aliased lines the quad vertices also depend on whether the line is x-major or y-major. 5.6.0.3 Points
  • DSGP renders anti-aliased points as circles and aliased points as squares.
  • the circles are centered at the user specified position.
  • the diameter of the circle is the width specified by the user rounded to the nearest supported width.
  • the user specified position of the point is snapped to the center of the pixel or rounded to a corner of the pixel depending on whether the resulting width is odd or even respectively.
  • the adjustment of point size and position should happen in the pipeline prior to the SORT block. Since the position of the point is subject to transformations, Geometry unit seems like the right place to do this.
  • Figure 41 shows the rendered point.
  • the user specified point is indicated by the circle. 5.6.1 Setup Block Functional Overview
  • edge-on triangles are discarded.
  • the edge-on triangles are not expected to generate any VSPs. If we do not discard them in STP, then there will be a processing overhead in CUL associated with the rasterization of these triangles.
  • the pixel intensity may be anomalous. This is detected when two of the edge slopes are found to be equal.
  • STP For each filled polygon, STP does the following:
  • the CUL unit implements a scan converter that rasterizes the parallelograms and triangles uniformly. Anti-aliased line segments are converted into a rectangle as shown in Figure 42.
  • STP does the following: 1. Determines the x and y vertex displacements (xhw, yhw). 2. Determines the vertices of the rectangle. The computed vertices depend on whether the line is aliased or anti-aliased.
  • the end points of aliased lines are computed differently from the way the anti-aliased line end points are computed.
  • a parallelogram for aliased lines. Two of the edges of the parallelogram are parallel to the length of the line and the other two edges are either vertical (for x-major lines) or horizontal (for y-major lines) as shown in Figure 43.
  • OpenGL requires that the parallelogram vertices be computed such that 1. There are no gaps or overstrikes while drawing consecutive polyline segments if both segments are either x-major or y-major. 2. There is at most one column (or row) disparity between the total number of fragments rasterized using the OpenGL diamond exit rule and DSGP method.
  • the coordinates of the rasterized fragments deviate by no more than one unit in the x and y directions.
  • the other axis is horizontal or vertical.
  • the state associated with stippling includes a 16 bit stipple pattern, stipple repeat factor r, stplStartBit, and stplRepeatStrt.
  • the stipple pattern must continue over each segment of line strips, line loops, and polygons drawn in line mode.
  • stplStartBit and StplRepeatStart are state parameters used to implement this continuity. Setup gets the information about stplStartBit and
  • Geometry unit is responsible for computing the stplStartBit and StplRepeatStart offsets at the beginning of each line segment.
  • the line width, w also controls the appearance of the generated line segments.
  • Setup breaks the continuous sequences of 1s in the stipple pattern into quads. For antialiased lines the quads are rectangles. These rectangles are "ni" long and w wide; where n is the number of 1s in that sequence. These represent the visible portions of the line ( Figure 44).
  • the quads are parallelograms. Since STP generates a quadrangle for each run of 1 bits, some of these quads might be outside the tile boundaries. In order to reduce the unnecessary processing of these quads we clip the stipple segments giving rise to the quads that lie wholly outside the tile. If the start point of the line (xO, yO) lies outside the tile, then we clip the line to the tile boundaries closest to the start point. The clipped line start points is generated such that the first line quad is completely included. This will ensure that there is continuity across the tile boundary. This is equivalent to placing a clipping guard band around the tile. A new line start-point as well as stipple offset stplStartBit is generated for the clipped point. (We retain the old StplRepeatStart.) This is shown in Figure 45.
  • the line is clipped to the edge of the tile displaced by xhw and yhw in x and y direction respectively.
  • the processing of stippled lines thus has the following steps.
  • the STP unit receives the edge flags in addition to window coordinates (x, y, z) for the three triangle vertices. These edge flags tell the Setup unit which edges are to be drawn. Setup unit also receives the "factor" used in the computation of polygon offset. The edges that are to be drawn are first offset by the polygon offset and then drawn as ribbons of width w (line attribute). These lines may also be stippled if stippling is enabled.
  • Figure 46 shows the geometry of line mode triangles. For each line polygon, STP does the following: 1. Discards any edge-on triangles. Please see the section on filled triangles for more on this. 2. Computes the partial derivatives of z along x and y ( ⁇ z/ ⁇ x, ⁇ z/ ⁇ y). Note that these z gradients are for the triangle and are needed to compute the z offset for the triangle. These gradients do not need to be computed if 'factor' is zero.
  • Setup converts the line segments into parallelograms which consists of four vertices.
  • a triangle has three vertices.
  • Setup describes the each primitive with a set of four points. Note that not all values are needed for all primitives.
  • Setup uses top, bottom, and either left or right corner, depending on the triangle's orientation.
  • a line segment is treated as a parallelogram, so Setup uses all four points.
  • Figures 47-51 show how Setup represents triangles and lines. Note that while the triangle's vertices are the same as the original vertices, Setup generates new vertices to represent the lines as quads.
  • the unified representation of primitives uses primitive descriptors which are assigned to the original set of vertices in the window coordinates. In addition, there are flags which indicate which descriptors have valid and meaningful values: VtxYmin, VtxYmax, VtxLeftC, VtxRightC, LeftCorner, and RightCorner.
  • these descriptors are obtained by sorting the triangle vertices by their y coordinates. For line segments these descriptors are assigned when the line quad vertices are generated.
  • VtxYmin is the vertex with the minimum y value.
  • VtxYmax is the vertex with the maximum y value.
  • VtxLeftC is the vertex that lies to the left of the long y-edge (the edge of the triangle formed by joining the vertices VtxYmin and VtxYmax) in the case of a triangle, and to the left of the diagonal formed by joining the vertices VtxYmin and VtxYmax for parallelograms.
  • VtxRightC is the vertex that lies to the right of the long y-edge in the case of a triangle, and to the right of the diagonal formed by joining the vertices VtxYmin and VtxYmax for parallelograms. If the triangle is such that the long edge is also the right edge, then the flag RightCorner is FALSE (0) indicating that the VtxRightC is invalid.
  • VtxXmin is the vertex with the minimum x value.
  • VtxXmax is the vertex with the maximum x value.
  • VtxTopC is the vertex that lies above the long x-edge (edge joining vertices VtxXmin and VtxXmax) in the case of a triangle, and above the diagonal formed by joining the vertices VtxXmin and VtxXmax for parallelograms. If the triangle is such that the long x-edge is also the top edge, then the flag TopCorner is FALSE (0) indicating that the VtxTopC is invalid.
  • VtxBotC is the vertex that lies below the long x-axis in the case of a triangle, and below the diagonal formed by joining the vertices VtxXmin and VbcXmax for parallelograms. If the triangle is such that the long x-edge is also the bottom edge, then the flag BottomComer is FALSE (0) indicating that the VtxBotC is invalid. These descriptors are used for clipping of primitives on the left and right tile edges. Note that in practice VtxXmin, VbcXmax, VtxTopC, and VtxBotC are indices into the original primitive vertices.
  • Figure 47 shows the vertex assignment graphically.
  • the slopes ( ⁇ x/ ⁇ y) of the four polygon edges - represented as ⁇ SIYmaxLeft, SIYmaxRight, SILeftYmin, SIRightYmin ⁇ and the inverse of slopes (dy/dx) ⁇ rSIXminTop, rSIXminBot, rSITopXmax, rSIBotXmax ⁇ .
  • Slope naming convention used is SIStrtEnd.
  • Si is for slope
  • Strt is first vertex identifier
  • End is the second vertex identifier of the edge.
  • SIYmaxLeft is the slope of the left edge - connecting the VtxYMax and VbcLeftC.
  • SIYmaxLeft is the slope of the long edge.
  • the letter r in front indicates that the slope is reciprocal, i.e. represents ( ⁇ y/ ⁇ x) instead of ( ⁇ x/ ⁇ y).
  • Figure 48 shows the slope assignments graphically. All of these descriptors have valid values for quadrilateral primitives, but all of them may not be valid for triangles. Initially, it seems like a lot of descriptors to describe simple primitives like triangles and quadrilaterals. However, as we shall see later, they can be obtained fairly easily, and they provide a nice uniform way to setup primitives.
  • indices iO, i1 , and i2 are used to compute a set of (dx dy) derivatives.
  • indices jO, j1 , and j2 are used to compute the (dy/dx) derivatives for the edges.
  • edge-on triangles i.e. triangles having two edges with equal slopes. Whether the middle vertex is on the left or the right is determined by comparing the slopes dx2/dy of line formed by vertices v[i2] and v[i1], and dxO/dy of the line formed by vertices v[i2] and v[i0j. If (dx2/dy > dxO/dy) then the middle vertex is to the right of the long edge else it is to the left of the long edge. The computed values are then assigned to the primitive descriptors. Assigning the x descriptors is similar. We thus have the edge slopes and vertex descriptors we need for the processing of triangles.
  • Depth gradients are the partial derivatives of z along the x- and y-axes.
  • Depth gradients are the partial derivatives of z along the x- and y-axes.
  • ⁇ z _ (yi - yo)(z ⁇ - zo) - (y ⁇ - yo)(z2 — zo) ⁇ x (x ⁇ - x )(y2 - yo) - (x2 - xo)(y ⁇ - yo) ⁇ z _ (x ⁇ — xo)(z2 - zo) - (x2 - xo)(z ⁇ - zo) ⁇ y (x ⁇ — xo)(y2 - yo) - x2 - - yo)
  • Setup receives 26 bits (s25) for each vertex z-value from Sort unit.
  • the partial derivatives are computed as 1.24.10 precision values.
  • the x, y coordinates are 14 bit integers with precision corresponding to the (8x8) sub-raster grid per pixel.
  • the partial derivatives are computed on the scale of the sub-raster grid.
  • the "factor” is passed down to from the SRT block.
  • the (r * unit) offset part is taken care of in GEO.
  • the depth values are represented as 24 bit integers. This offset is added to each of the vertex z values.
  • the computed offset is clamped to 24 bits (in fact s24) before being added to the z values.
  • V[0] (xO - xhw, yO + yhw);
  • V[1] (xO + xhw, yO - yhw);
  • V[2] (x1 - xhw, y1 + yhw);
  • V[3] (x1 + xhw, y1 - yhw);
  • the computation of xhw and yhw and hence quad vertices is done based on the orientation of the line and its aliasing state.
  • Figure 49 shows the quadrant assignment based on the orientation of the line.
  • stippled line preprocessing has two stages. We first remove the stipple segments that do not touch the tile, and calculate the new start stipple bit. We then traverse the line and generate line lengths corresponding to sequences of 1 bits in the stipple. We assume that quad vertex generation has provided us with the half width displacements. The first step is to find the first intersection point of the line with the tile boundaries after displacing the edges by the guard band. Note that SRT block should only send us lines that touch the tile. Therefore, it is unnecessary to check for trivial rejection of lines based on their slopes and such. StrtClipX, StrtClipY, OpX, and OpY were obtained in the previous section. Once the intersection point (xint, yint) is computed, find the number of stipple pattern bits
  • the clipcodes are assigned to the vertices as shown in Figure 50, and are obtained as follows for each of the vertices.
  • Bottom edge clipping yields the bLeft and bRight-the bottom left and bottom right clip vertices.
  • Left and right edge clipping uses vertices sorted in x and yields the high and low intersection points ILow, IHigh on the left edge and rLow and rHigh on the right edge. Note that the procedure for the left edge is identical to the bottom edge and that for right edge is identical to the top edge. Note also that we are using the inverse slope descriptors instead of the slope descriptors.
  • Clipping on the left tile edge is done identically to the right tile edge.
  • the output of left edge clipping are the two points ILow and IHigh.
  • intersection points with the top tile edge may be such that they are both to the left of the tile. In this case, the intersection points are marked invalid. If the intersection with the edge is such that one or both tile top corners are included in the intersection, then new intersection points are generated that are valid.
  • a primitive is discarded if none of the intersection points are found to be valid. Note that in most cases the triangles lying outside the tile will be discarded by the SRT block. However, in some rare cases we might get a triangle that is completely outside the tile, for example a long thin triangle, where the vertex snapping to 11.3 causes reversal of winding. In this case the valid flags will allow us to discard the triangle.
  • the bounding box of the primitive intersection is determined by examining the clipped vertices. We use these eight points to compute the bounding box. We first initialize the bounding box to the tile boundaries, and then move in to the tile by examining the edge clip points. We have now got the bounding box. These xmin, xmax, ymin, ymax pixel coordinates need to be converted to the stamp coordinates. This can be accomplished by first converting the coordinates to tile-relative values and then considering the high three bits only (i.e. shift right by 1 bit). This works; except when xmax (and/or ymax) is at the edge of the tile. In that case, we decrement the xmax (and/or ymax) by 1 unit before shifting. 5.6.2.7.2 Minimum Z computation
  • Setup passes a single Z value, representing the Z value at a specific point within the primitive.
  • Setup chooses a reference stamp that contains the vertex with the minimum z. We accomplish this by truncating the vertex coordinates to the integer values and finding the corresponding stamp. For vertices on the right edge, the x-coordinates is decremented and for the top edge the y-coordinate is decremented before the reference stamp is computed.
  • the reference Z value, z Re(Tlte , is calculated at the center of the reference stamp.
  • Setup identifies the Reference Stamp with a pair of 3 bit values, x RefStamp and y RefStamp , that specify its location in the Tile. Note that the reference stamp is identified as an offset in stamps from the corner of the Tile.
  • CY T (the circle's topmost point, clipped by the tile's top edge, in tile coordinates)
  • CY B the circle's bottom most point, clipped by the tile's bottom edge, in tile coordinates
  • Y oftset (the distance between CYT and the bottom of the undipped circle)
  • XO (the X coordinate of the center, in window coordinates)
  • An infinite dx/dy implies that an edge is perfectly horizontal. In the case of horizontal edges, one of the two end-points has got to be a corner vertex (VbcLeftC or VtxRightC). With a primitive whose coordinates lie within the window range, Cull will not make use of an infinite slope. This is because with Cull's edge walking algorithm, it will be able to tell from the y value of the left and/or right corner vertices that it has turned a corner and that it will not need to walk along the horizontal edge at all.
  • Cull's edge walking will not think to turn a corner on the horizontal edge and it will try to calculate the span end-point from tRight (or tLeft). (See Figure 51 ). ln this case, Cull's edge walking will need a slope. Since the start point for edge walking is at the very edge of the window, any X that edge walking calculates with a correctly signed slope will cause an overflow (or underflow) and X will simply be clamped back to the window edge. So it is actually unimportant what value of slope it uses as long as it is of the correct sign. A value of infinity is also a don't care for setup's own usage of slopes. Setup uses slopes to calculate intercepts of primitive edges with tile edges.
  • a dx/dy of infinity necessarily implies a ⁇ Y of zero.
  • the value of dx/dy is a don't care.
  • the Cull unit is responsible for: 1 ) pre-shading hidden surface removal; and 2) breaking down primitive geometry entities (triangles, lines and points) to stamp based geometry entities called Visible Stamp Portions (VSPs).
  • VSPs Visible Stamp Portions
  • the Cull unit does, in general, a conservative culling of hidden surfaces. Cull can only conservatively remove hidden surfaces because it does not handle some "fragment operations" such as alpha test and stencil test.
  • the Cull block's sample z-buffer can hold two depth values, but the Cull block can only store the attributes of one primitive per sample. Thus, whenever a sample requires blending colors from two pieces of geometry, Cull has to send the first primitive (using time order) down the pipeline, even though there may be later geometry that hides both pieces of the blended geometry.
  • the Cull Unit receives Setup Output Primitive Packets that each describe, on a per tile basis, either a triangle, a line or a point.
  • Sort is the unit that bins the incoming geometry entities to tiles.
  • Setup is the unit that pre-processed the primitives to provide more detailed geometric information for Cull to do the hidden surface removal. Setup will pre-calculate the slope value for all the edges, the bounding box of the primitive within the tile, minimum depth value (front most) of the primitive within the tile, and other relevant data.
  • Mode Extraction Prior to Sort, Mode Extraction has already extracted the information of color, light, texture and related mode data, Cull only gets the mode data that is relevant to Cull and a pointer, called Color Pointer, that points to color, light and texture data stored in Polygon Memory.
  • the Cull Unit sends one Visible Stamp Portion (VSP) at a time to the Mode Injection unit.
  • VSP Visible Stamp Portion
  • a VSP is a visible portion of a geometry entity within a stamp.
  • Mode Injection reconnects the VSP with its color, light and texture data and sends it to Fragment and later stages in the pipeline.
  • the Cull Unit performs two main functions.
  • the primary function is to remove geometry that is guaranteed to not affect the final results in the frame buffer (i.e., a conservative form of hidden surface removal).
  • the second function is to break primitives into units of stamp portions (SPs).
  • SPs stamp portions
  • a stamp portion is the intersection of a primitive with a given stamp.
  • the portion amount is determined by sampling. Any stamp will have 16 predetermined sample points (actually each pixel within a stamp has 4 predetermined sample points).
  • the portion "size" is then given by the number and the set of sample points covered by a primitive in a given stamp.
  • Cull processes primitives one tile at a time. However, for the current frame, the pipeline is in one of two modes: 1 ) Time Order Mode; or 2) Sorted Transparency Mode. In Time Order
  • Sorted Transparency Mode time order of vertices and modes are preserved within each tile, and the tile is processed in a single pass through the data. That is, for a given tile, vertices and modes are read in the same order as they are written, but are skipped if they do not affect the current tile.
  • Sorted Transparency Mode the processing of each tile is divided into multiple passes, where, in the first pass, guaranteed opaque geometry is processed (the Sort Block only send non-transparent geometry for this pass). In subsequent passes, potentially transparent geometry is processed (the Sort Block repeatedly sends all the transparent geometry for each pass). Within each pass, the time ordering is preserved, and mode data is inserted in its correct time-order location.
  • Time Order Mode when there is only "simple opaque geometry" (i.e. no scissor testing, alpha testing, color testing, stencil testing, blending, or logicop) in a tile, Cull will process all the primitives in the tile before dispatching any VSPs to Mode Injection. This is because the Cull hidden surface removal algorithm can unambiguously determine, for each sample, the single primitive that covers (i.e., colors) that sample.
  • the case of "simple opaque geometry” is a special case that renderers do not generally see too often.
  • Time Order Mode when the input geometry is not limited to "simple opaque geometry" within a tile, early dispatch of VSPs (entire set of VSPs or selected VSPs) may be required.
  • each tile is processed in multiple passes (assuming there is at least some transparent geometry in the tile). In each pass, there is no early dispatch of VSPs.
  • the PrimType parameter indicates the primitive type (triangle, line or point).
  • the spatial location of the primitive is done using a "unified description". That is, the packet describes the primitive as a quadrilateral (not screen aligned), and triangles and points are degenerate cases. This "unified description" is described in great detail in the section "Setup Output Primitive Packet".
  • the packet includes a color pointer, used by Mode Injection.
  • the packet also includes several mode bits, many of which can change primitive-by-primitive. The following are considered to be "mode bits", and are input to the Z Cull state machine: CullFlushCurrent, DoAlphaTest; DoABIend, DepthFunc,
  • Cull receives the following packet types: Setup Output Clear Packet; Setup Output Cull Packet; Setup Output Begin Frame Packet; Setup Output End Frame Packet; Setup Output Begin Tile Packet; and Setup Output Tween Packet.
  • Each of these packet types is described in detail in a later section. But, collectively, these packets are known as "mode packets" (admittedly, a somewhat misleading name).
  • the Setup Output Clear Packet indicates some type of buffer clear is to be performed. However, buffer clears that occur at the beginning of a user frame (and not subject to scissor test) are included in the begin tile packet.
  • the Setup Output Cull Packet is a packet of mode bits. This packet includes bits for: 1) enabling/disabling the MCCAM Cull and Z Cull processes; 2) a bit, CullFlushAII, that causes a flush of all the VSPs from the Cull block; and 3) AliasPolys, AliasLines, and AliasPoints, which disable antialiasing for the three types of primitives.
  • the Setup Output Begin Frame Packet tells Cull that a new frame is starting. The next packet will be a Sort Output Begin Tile Packet.
  • the Setup Output Begin Frame Packet contains all the per-frame information that is needed throughout the pipeline.
  • the Setup Output End Frame Packet indicates the frame has ended, and that the current tile's input has completed.
  • the Setup Output Begin Tile Packet tells Cull that the current tile has ended and the processed data should be flushed down the pipeline. And, at the same time, it should start to process the new tile's primitives. If a tile is to be repeated due to the pipeline being in Sorted Transparency Mode, then this requires another Setup Output Begin Tile Packet. Hence, if a particular tile needs an opaque pass and four transparent passes, then a total of five begin tile packets are sent from Setup. This packet specifies the location of the tile within the window.
  • Tween Packet can only occur between (hence 'tween) frames, which, of course is between tiles. Cull treats this packet as a black box, and just passes it down the pipeline. This packet has only one parameter, TweenData, which is 144 bits.
  • Figure 53 shows a basic block diagram of the Cull block. Whenever a primitive is received, Cull will attempt to eliminate it by querying the MCCAM
  • each stamp in the list may contain a portion of the primitive that may be visible.
  • This list of potentially visible stamps is sent to the stamp selection block 9008 of Cull.
  • the stamp selection block will use the geometry data of the primitive to determine the set of stamps within each stamp row of the tile that is actually touched by the primitive.
  • the stamp selection block dispatches one potential visible stamp 9006 at a time to the Z Cull block 9012.
  • Each stamp is divided into a grid of 16 by 16 sub-pixels. Each horizontal grid line is called a subraster line.
  • Each of the 16 sample points per stamp has to fall (for antialiased primitives) at the center of one of the 256 possible sub-pixel locations.
  • Each pixel has 4 sample points within its boundary.
  • the process of determining the set of stamps within a stamp row that is touched by a primitive involves the calculation of the left most and right most position of the primitive in each subraster line that contain at least 1 sample point.
  • XleftSubS, and XrightSubS stands for x left most subraster line for sample i and x right most subraster line for sample i respectively.
  • Samples are enumerated from 0 to 15.
  • the determination of XleftSubS, and XrightSubS is typically called the edge walking process. If we know a point on an edge (xO, yO), then the value of x1 corresponding to the y position of y1 can easily be determined by:
  • the set of 16 pairs of XleftSubS, and XrightSubS is also sent by stamp selection block to Z Cull.
  • the Z Cull unit receives one stamp number (or StamplD) at a time.
  • stamp number contains a portion of a primitive that may be visible as determined by MCCAM.
  • the set of 16 pairs of XleftSubSi and XrightSubS allows us to decide which of the 16 sample points are covered by the primitive. Sample i is covered if Xsample,, the x-coordinate value of sample i satisfies:
  • each sample that is covered we calculate the primitive's z-value at that sample point.
  • the current z-values and z-states for all 16 sample points are read from the sample z-buffer.
  • Each sample point can have a z-state of "conservative" or "accurate”.
  • the z- state combined with the mode bits received by Cull drives the sample finite state machine.
  • Each sample point has a FSM independent of other samples.
  • the state machine controls the comparison on a per sample basis between the primitive's z-value and the z-buffer J s z-value. The result of the comparison is used to determine if the new primitive is visible or hidden at each sample point that the primitive covers.
  • a sample's pixel FSM determines how the z-buffer should be updated for that sample, and if the sample point of the new VSP should be dispatched early. In addition, it determines if any old VSP that may contain the sample point should be destroyed or should be dispatched early.
  • These per sample control signals are generated as the SendNew, KeepOld and SendOld masks by Z Cull and sent to the stamp portion mask unit 9014.
  • the state table for pixel finite state is described in the architecture specification and is not repeated here. The maximum of the 16 sample points' z-value is used to update the MCCAM.
  • Sorted Transparency Mode we want the transparent primitive to be rasterized in the spatial order starting with the layer closest to front most opaque layer instead of the regular mode of time order rasterization. This requires the transparent primitives for a tile to go through the Cull unit several times The first time, the Sort unit send only the opaque primitives. The z-values are updated as described in the last paragraph. We call the z-values for opaque primitives of type Zfar. At the end of the pass, the opaque VSPs are dispatched. The second time Sort will only send the transparent primitives for the tile to Cull.
  • the Znear portion of the z-buffer are preset to smallest z-value possible.
  • a sample point with z-value behind Zfar is hidden, but a z-value before Zfar and behind Znear is closer to opaque and therefore replaces the current Znear's z-value.
  • the VSPs representing the closest to opaque layer is dispatched.
  • the role of Znear and Zfar is the switched, and Z Cull receives the second pass of transparent primitives. This process continues until Z Cull determines that it has processed all possible layers of transparent primitives.
  • Z Cull in sorted transparent mode is also controlled by the pixel finite state machines.
  • the stamp portion mask block contains the VSP coverage masks for each stamp in the tile.
  • the maximum number of VSPs a stamp can have is 16.
  • the VSP masks need to be updated or dispatched early when a New VSP comes in from Z Cull.
  • the stamp portion mask block will perform the mask update or dispatched strictly depending on the SendNew, KeepOld and SendOid control signals.
  • the update has to occur at the same time for a maximum of 16 old VSPs in a stamp because a new VSP can potentially modify the coverage mask of all the old VSPs in the stamp.
  • the stamp portion data block 9016 contains other information associated with a VSP including but not limited to the color pointer.
  • the stamp portion data memory also needs to hold the data for all VSPs contained in a tile. Whenever a new VSP is created, its associated data need to be stored in the memory. And whenever an old VSP is dispatched, its data need to be retrieved from the memory. 5.7.2 Cull Block Functional Details
  • the Cull block is composed of the following sub-units: 1) Input FIFO; 2) MCCAM Cull; 3) Subrasterizer; 4) Column Selection; 5) Z Cull; 6) MCCAM Update; 7) New VSP Queue; 8) Stamp Portion Memory Mask; 9) Stamp Portion Memory Data; 10) Dispatch Queue; and 11) Dispatch Logic. These sub-units are described in the following sections.
  • Figure 54 shows a block diagram of the Cull sub-units.
  • the input FIFO sub-unit 9050 interfaces with the Setup unit 8000. It receives data packets from Setup and stores each packet in a queue.
  • the number of needed FIFO memory locations is between 16 to 32, but we currently assume the depth to be 16. 5.7.2.2 MCCAM Cull
  • the MCCAM Cull sub-block 9002 uses the Spatial Addressable Memory (MCCAM) to perform a spatial query on a primitive's bounding box to determine the set of stamps within the bounding box that may be visible.
  • the value that it will use for Z comparison is ZminTile.
  • MCCAM Cull can process one primitive per cycle from the input FIFO. Read operations form the FIFO occur when the FIFO is not empty and either the last primitive removed is completely hidden as determined by MCCAM Cull or the last primitive is being processed by the Subrasterizer unit 9052. In other words, MCCAM Cull will not "work ahead" of the Subrasterizer. Rather, it only gets the next primitive that the Subrasterizer needs to process, and then waits.
  • MCCAM Cull will not "work ahead" of the Subrasterizer. Rather, it only gets the next primitive that the Subrasterizer needs to process, and then waits.
  • the subrasterizer 9052 is the sub-unit that does the edge walking (actually, the computation is not iterative, as the term "walking" would imply). For each row of stamps that MCCAM Cull indicates to be potentially visible. It simultaneously calculates the XleftSub, and XrightSub, for each of the 16 sample points. Each pair of XleftSub, and XrightSub, will specify a set of stamps in the row that is touched by the primitive. The Subrasterizer determines the set of stamps touched in a stamp row for each subraster line where a sample point is located, and combines the 16 sets of stamps touched into 1 touched stamp list.
  • the Subraterizer passes a request to MCCAM Cull for each stamp row, and receives a visible stamp list.
  • the visible stamp list is combined with the touched stamp list, thereby determining the final potential visible stamp set in a stamp row.
  • the visible stamp set is sent to the Column Selection portion of the Stamp Selection Logic.
  • the Subrasterizer can process one row of stamps per cycle. If a primitive contains more than 1 row of stamps then the Subrasterizer will take more than 1 cycle to process the primitive and therefore need to request MCCAM to stall the removal of primitives from input FIFO.
  • the Subrasterizer itself can be stalled if a request is made by the Column Selection unit.
  • the column selection sub-unit 9054 tells the Z Cull unit 9012 which stamp to process in each clock cycle. If a stamp row contains more than 1 potentially visible stamp, the Column Selection unit needs to request the Subrasterizer to stall. 5.7.2.5 Z Cull
  • the Z Cull sub-unit 9012 contains the sample z-buffer. Based on the XleftSub, and XrightSub, calculated by the Subrasterizer, it determines the set of sample points in the stamp that is covered by the primitive. It then calculates the z-value of the primitive at those sample points and compare the resulting z-values to the corresponding z-values stored in the z-buffer for that stamp. Based on the result of the comparison, current Cull mode bits and the states of the sample state machines, the z-buffer is updated. For each sample, the finite state machine in Z Cull generate the bits: OldSampleKeep; OldSampleSend; NewSampleMask; and NewSampleSend.
  • the set of NewSampleMask bits (16 of them) constitute a new Stamp Portion (SP) coverage mask.
  • SP Stamp Portion
  • the MCCAM Update sub-unit 9056 determines the maximum of the 16 updated z-values for the 16 sample points and sends it to the MCCAM unit to update MCCAM. 5.7.2.7 NewVSP Queue
  • the Z Cull sub-unit generates 4 set of bits per Stamp Portion per clock cycle: OldSampleKeep; OldSampleSend; NewSampleMask; and NewSampleSend.
  • the SPM Mask&Valid sub-unit can store one new Stamp Portion every clock cycle.
  • the SPM Mask&Valid sub-unit requires multiple clocks for a new Stamp Portion when early dispatch of VSPs occur.
  • the NewVSP Queue 9058 stores new Stamp Portions, thus allowing Z Cull to proceed without stalling.
  • the NewVSP Queue is a simple queue. This queue is useful only in the case of early dispatch.
  • the SPM Mask&Valid unit can only handle 1 VSP at a time. If early dispatch involves more than 1 VSP, the Z Cull unit would have to stall if we did not have the NewVSP Queue.
  • the Stamp Portion Memory Mask and Valid sub-unit contains the VSP coverage masks for the tile. Each VSP entry will require a valid bit to indicate if there is a valid VSP stored there. The valid bits for the VSPs are stored in a separate memory. This sub-unit is double buffered (i.e. there are two copies) as shown in the microarchitecture block diagram.
  • the active state page will contain VSPs for the current tile while the dispatch state page will contain VSPs of last tile (currently being dispatched).
  • the active state SPM Mask&Valid unit 9060 will update the VSPMask for the VSPs that already exist in its mask memory and add the new VSP to the memory content. When color blending or other conditions occur that require early dispatch, the active state SPM Mask&Valid will dispatch VSPs through the
  • SPM Data unit to the dispatch queue.
  • the behavior of mask update or early dispatch is controlled by the OldSampleKeep; OldSampleSend; and NewSampleSend control signals generated in Z Cull.
  • the state transition from active to dispatch and vice versa is controlled by mode packets.
  • Receiving a packet signaling end of a tile Begin Tile, End Frame, Buffer Clear, or Cull Packet with CullFlushAII set to TRUE
  • the page in dispatch state simply cycles through each stamp and sends all VSPs to the SPM Data unit 9064, which forwards them to the dispatch queue.
  • the Stamp Portion Memory Data sub-unit 9064 stores the Zstamp, dz/dx, dz/dy and the ColorPointer for every VSP in the tile. This unit is also double buffered.
  • the SPM Mask&Valid sends the new VSP information to the SPM Data and tells it whether it should send the new VSP or save the new VSP to its memory. If the new VSP should be saved, the SPM Mask&Valid will also tell it which location among the 16 possible slots the new VSP should occupy.
  • SPM Data also gets a list of old VSP locations and the associated VSPMasks that need early dispatch. The SPM Data block will first check to see if there is any old
  • VSP that need to be dispatched. If it finds any, it will simply read the VSP data from its memory, merge with the VSPMask sent from SPM Mask&Valid block, and put the VSP into the dispatch queue. It then checks if the new VSP should be sent too, and if it is affirmative, then it passes the new VSP data to the dispatch queue. If the new VSP should not be sent, it writes the new VSP data into its memory. 5.7.2.10 The Dispatch Queue and Dispatch Logic
  • This unit will attempt to send one entry's worth of data from one of the two SPMs' dispatch queues to Mode Inject unit. It will attempt to dispatch from the dispatch state SPM first. Only after the dispatch state Stamp Portion Memory has exhausted all of its VSPs, it will try to dispatch from the active state SPM dispatch queue.
  • the Mode Injection (MIJ) block in conjunction with the Mode Extraction block is responsible for the management of graphics state related information.
  • state changes are incremental, i.e. the value of a state parameter remains in effect until it is changed. Therefore, the applications only need to update the parameters that change.
  • the rendering is linear, i.e. primitives are rendered in the order received. Points, lines, triangle strips, triangle fans, polygons, quads, and quad strips are examples of graphical primitives.
  • rendering is tile based.
  • the Geometry (GEO) block receives the primitives in order, performs all vertex operations (transformations, vertex lighting, clipping, and primitive assembly), and sends the data down the pipeline.
  • the Sort block receives the time ordered data and bins it by the tiles it touches. (Within each tile, the list is in time order.)
  • the CUL block receives the data from the SRT block in tile order, and culls out parts of the primitives that definitely do not contribute to the rendered images.
  • the CUL block generates the VSPs.
  • a VSP corresponds to the visible portion of a polygon on the stamp.
  • a stamp is a 2x2 pixel area of the image.
  • the TEX and PHG units receive the VSPs and are responsible for the texturing and lighting of the fragments respectively.
  • the last block, i.e. the Pixel block consumes the VSPs and the fragment colors to generate the final picture.
  • a primitive may touch many tiles and therefore, unlike traditional rendering pipelines, may be visited many times (once for each tile it touches) during the course of rendering the frame.
  • the pipeline must remember the graphics state in effect at the time the primitive entered the pipeline, and recall it every time it is visited by the pipeline stages downstream from SRT.
  • MEX is a logic block between Geometry and Sort blocks that collects and saves the temporally ordered state change data, and attaches appropriate pointers to the primitive vertices in order to associate the correct state with the primitive when it is rendered.
  • the Mode Injection (MIJ) block is responsible for the retrieval of the state and any other information associated with the state pointer (aka the MLM Pointer) when it is needed. It is also responsible for the repackaging of the information as appropriate. An example of the repackaging occurs when the vertex data in polygon memory is retrieved and bundled into primitive (triangle, line, point) input packets for fragment.
  • MIJ block we first describe the functional requirements of the MIJ block. We then discuss the input and output interfaces to the MIJ block. This is followed by the functional details and algorithms used by the MIJ block. Lastly, we discuss the performance and memory bandwidth requirements. 5.8.2 Functional Overview of MIJ block
  • MIJ receives VSP packets from the CUL block.
  • Each VSP packet corresponds to the visible portion of a primitive on the 2x2 pixel stamp.
  • the VSPs output from the Cull block to MIJ block are not necessarily ordered by primitives. In most cases, they will be in the VSP scan order on the tile, i.e. the VSPs for different primitives may be interleaved.
  • the pipeline stages downstream from the MIJ block need information about the type of the primitive (i.e. point, line, triangle, line-mode triangle); its geometry such as window and eye coordinates, normal, color, and texture coordinates at the vertices of the primitive; and the rendering state such as the PixelModes, TextureA,
  • MEX also attaches ColorPointers ⁇ ColorAddress, ColorOffset, and ColorType ⁇ to each primitive sent to Sort, which is in turn passed on to each of the VSPs of that primitive.
  • MIJ decodes this pointer to retrieve the necessary information from the polygon memory. MIJ starts working on a frame after it receives a BeginFrame packet from CUL. The VSP processing for the frame begins when CUL is done with the first tile in the frame and MIJ receives the first VSP for that tile.
  • the color pointer consists of three parts, the ColorAddress, ColorOffset, and ColorType. (We refer the reader to the Mode Extraction Architecture Specification for details of the
  • ColorPointer and the MLM_Pointer.
  • the ColorAddress points to the ColorVertex that completes the primitive.
  • ColorOffset provides the number of vertices separating the ColorAddress from the dualoct that contains the MLM_Pointer.
  • ColorType contains information about the type of the primitive, size of each ColorVertex, and the enabled edges for line mode triangles. The ColorVertices making up the primitive may be 2, 4, 6, or 9 dualocts long. MIJ decodes the
  • the MLM_Pointer contains the dualoct address of the six state packets in polygon memory.
  • the MIJ block is responsible for making sure that the Fragment, Texture, Phong and Pixel blocks have all the information they need for processing the fragments in the VSP, before the VSP arrives at that stage.
  • the ColorVertices of the primitive as well as the six state packets pointed to by the pointers in the MLM_Pointer need to be resident in the blocks that need them, before the VSP fragments can be processed. If MIJ was to retrieve the MLM_pointer, the state packets, and ColorVertices for each of the VSPs, it will amount to nearly 1 KB of data per VSP. This is equivalent to 125GB/sec of polygon memory bandwidth for reading the data, and as much for writing out the data to FRG and PIX blocks.
  • VSPs do not arrive at MIJ in primitive order. Instead, they are in the VSP scan order on the tile, i.e. the VSPs for different primitives crossing the scan-line may be interleaved.
  • the data retrieved by MIJ is consumed by other blocks. Therefore, we store the cache data within those blocks.
  • Each of the Fragment, Texture, Phong, and Pixel blocks have a set of caches. These caches hold the actual data that goes in their cache-line entries. Since MIJ is responsible for retrieving the relevant data for each of the units from Polygon memory and sending it down to the units - it needs to know the current state of each of the caches in the four aforementioned units. This is accomplished by keeping tags for each of the caches and allowing MIJ to do all cache management. Thus cache data resides in the block that needs it and the cache tags reside in MIJ.
  • MIJ manages seven caches for the downstream blocks - one for FRG (ColorData Cache 10016) and two each for the TEX (TexA 10018, TexB 10020), PHG (Light 10024, Material 10022), and PIX (PixMode 10026 and Stipple 10028) blocks. For each of these caches the tags are cached in MIJ and the data is cached in the corresponding block. MIJ also maintains the index of the data entry along with the tag. In addition to these seven caches, MIJ also maintains two caches internally for efficiency, one is the ColorVertex cache 10012 and the other is the MLM_Pointer cache 10014. For these, both the tag and the data reside in MIJ. All of these nine tag caches are fully associative and we use CAMs for Cache tag lookup. These caches are listed in Figure 55
  • Color caching is used to cache color primitives. Depending on the extent of the processing features enabled, a ColorVertex may be 2, 4, 6, or 9 dualocts long in the polygon memory. Furthermore, a primitive may require one, two or three ColorVertices depending on if it is a point, line or a filled triangle respectively. Unlike other caches, Color Caching needs to deal with the problem of variable data sizes in additions to the usual problems of cache lookup and replacement.
  • the Color cache in Fragment block can hold 256 full performance color primitives.
  • the TagRam in MIJ has a 1-to-1 correspondence with the Color data cache in the Fragment block. Note that in the APEX pipeline a ColorAddress uniquely identifies a Color primitive. We therefore use the 24 bit ColorAddress as tag for the color cache.
  • the Color data fetch request is sent to the ColorDataFetch subblock.
  • This block uses the Color Address and the Color type to determine the number of vertices needed for this primitive, the size of each vertex and the ColorAddress of each vertex to be fetched.
  • the CCIX is incorporated in the VSP going out to the Fragment block.
  • the inventive structure also provides for Vertex Caching, MLM-Pointer Caching, Mode packet caching, Control Packet Processing, and for Fragment and Pixel Output Queue
  • the Mode Injection block resides between the CUL block and the rest of the pipeline downstream from CUL.
  • MIJ receives the control and VSP packets from the CUL block.
  • MIJ interfaces with the Fragment and Pixel blocks.
  • the MIJ is responsible for the following: 1. Routing various control packets such as BeginFrame, EndFrame, and BeginTile to
  • Polygon memory stores per-vertex data. Depending on the primitive type of the VSP, MIJ retrieves the required vertices (3 for a triangle, 2 for a line, and 1 for point primitives) from the polygon memory. 10. Sending data to the fragment and pixel blocks.
  • the Fragment block is located after Cull and Mode Injection and before Texture, Phong, and Bump. It receives Visible Stamp Portions (VSPs) that consist of up to 4 fragments that need to be shaded.
  • VSPs Visible Stamp Portions
  • the fragments in a VSP always belongs to the same primitive, therefore the fragments share the primitive data defined at vertices including all the mode settings.
  • a sample mask, sMask defines which subpixel samples of the VSP are active. If one or more of the four samples for a given pixel is active. This means a fragment is needed for the pixel, and the vertex- based data for primitive will be interpolated to make fragment-based data.
  • the active subpixel sample locations are used to determine the corresponding x and y coordinates of the fragment.
  • the Fragment block caches the color data to be reused by multiple VPSs belonging to the same primitive.
  • Mode Injection identifies if the color cache contains the required data. If it is a hit, Mode Injection sends the VSP, which includes an index into the cache. On a cache miss, Mode Injection replaces an entry from the cache with the new color data, prior to sending the VSP packet with the Color cache index pointing to the new entry.
  • Mode Injection replaces an entry from the cache with the new color data, prior to sending the VSP packet with the Color cache index pointing to the new entry.
  • all modes, materials, texture info, and light info settings are cached in the blocks in which they are used. An index for each of these caches is also included in the VSP packet.
  • the Fragment block caches some texture and mode info.
  • Figure 56 shows the flow and caching of mode data in the last half of the DSGP pipeline.
  • the Fragment block's main function is the interpolation of the polygon information provided at the vertices for all active fragments in a VSP.
  • the Fragment block can perform the interpolations of a given fragment in parallel and fragments within a VSP can be done in an arbitrary order. Fully interpolated stamps are forwarded to the Texture, Phong and Bump blocks in the same order as received.
  • the Fragment block generates Level of Detail (LOD or ⁇ ) values for up to four textures and sends them to the Texture block.
  • LOD or ⁇ Level of Detail
  • the Fragment block will have an adequately sized FIFO in its input to smooth variable stamp processing time and the Color cache fill latency.
  • Figure 57 shows a block diagram of the Fragment block.
  • the Fragment block can be divided into six sub-blocks. Namely: 1.
  • the cache fill sub-block 11050 is a cache fill sub-block 11050 .
  • the first block handles Color cache misses. New polygon data replaces old data in the cache.
  • the Color cache index, CCIX points to the entry to be replaced.
  • the block doesn't write all of the polygon data directly into the cache. It uses the vertex coordinates, the reciprocal of the w coordinate, and the optional texture q coordinate to calculate the barycentric coefficients. It writes the barycentric coefficients into the cache, instead of the info used to calculate them.
  • the second sub-block implements the Color cache.
  • Fragment receives a VSP packet (hit)
  • the cache entry pointed to by CCIX is read to access the polygon data at the vertices and the associated barycentric coefficients.
  • the third sub-block prepares the interpolation coefficients for the first fragment of the VSP.
  • the coefficients are expressed in plane equation form for the numerator and the denominator to facilitate incremental computation of the next fragment's coefficients.
  • the total area of the triangle divides both the numerator and denominator, therefore can be simplified.
  • additional storage and bandwidth is saved by only providing two out of three sets of barycentric coordinates along with the denominator. As a non-performance case, texture coordinates with a q other than 1 will be interpolated using 3 more coefficients for the denominator.
  • the x and y coordinates given per stamp correspond to the lower left pixel in the stamp. Only the position of the stamp in a tile is determined by these coordinates. A separate packet provides the coordinates of the tile that subsequent stamps belong to. A lookup table is used with the corresponding bits in sMask to determine the lower bits of the fragment x and y coordinates at subpixel accuracy. This choosing of an interpolation location at an active sample location ensures that the interpolation coefficients will always be positive with their sum being equal to one.
  • the fourth sub-block interpolates the colors, normals, texture coordinates, eye coordinates, and Bump tangents for each covered pixel.
  • the interpolators are divided in four groups according to their precision. The first group interpolates 8 bit fixed point color fractions.
  • the values are between 0 and 1 , the binary representation of the value 1 is with all the bits set to one.
  • the second set interpolates sixteen bit, fixed point, unit vectors for the normals and the surface tangent directions.
  • the third set interpolates 24 bit floating point numbers with sixteen bit mantissas. The vertex eye coordinates and the magnitudes of the normals and surface tangents fall into this category.
  • the last group interpolates the texture coordinates which are also 24 bit FP numbers but may have different interpolation coefficients. All interpolation coefficients are generated as 24 bit FP values but fewer bits or fixed point representation can be used when interpolating 8 bit or 16 bit fixed point values.
  • the fifth sub-block re-normalizes the normal and surface tangents.
  • the magnitudes obtained during this process are discarded.
  • the original magnitudes are interpolated separately before being forwarded to the Phong and Bump block.
  • the texture map u, v coordinates and Level of Detail (LOD) are evaluated in the sixth sub- block.
  • the barycentric coefficients are used in determining the texture LOD. Up to four separate textures associated with two texture coordinates are supported. Therefore the unit can produce up to four LODs and two sets of s, t coordinates per fragment, represented as 24 bit FP values.
  • Figure 58 shows examples of VSPs with the pixel fragments formed by various primitives.
  • a copy of the sMask is also sent directly to the Pixel block, bypassing the shading blocks (Fragment, Texture, Phong and Bump).
  • the bypass packet also includes the z values, the Mode and Polygon Stipple Indices and is written in the reorder buffer at the location pointed to by the VSPptr.
  • the pMask is generated in the Fragment block and sent Texture and Phong instead of the sMask. The actual coverage is evaluated in Pixel.
  • V 0 , V 1t and V 2 are the vertices of the triangle.
  • A-,, A, and A 2 can be found as: Area(p,V v V 2 ) Area(p,V 0 V 2 ) Areaip.V ⁇ J
  • Area(i,j,k) denotes the area in window coordinates of the triangle with vertices i, j, and k.
  • Area(i,j,k) denotes the area in window coordinates of the triangle with vertices i, j, and k.
  • the normal and surface tangents may have a magnitude associated with directional unit vectors.
  • Figure 60 shows how interpolating between vectors of unequal magnitude results in uneven angular granularity, which is why we do not interpolate normals and tangents this way.
  • Figure 61 shows how the fragment x and y coordinates used to form the interpolation coefficients are formed.
  • the tile x and y coordinates, set at the beginning of a tile processing form the most significant bits.
  • the sample mask (sMask) is used to find which fragments need to be processed.
  • a lookup table provides the least significant bits of the coordinates at sub-pixel accuracy. We may be able to reduce the size of the LUT if we can get away with 2 bits of sample location select.
  • x ⁇ , x w1 , x w2 are the window x-coordinates of the three triangle vertices.
  • y w0 , y ⁇ , y 2 are the three y-coordinates of the triangle vertices.
  • the denominator components can be formed by adding the individual constants in the numerator:
  • G 0 (x, y) C x0 ⁇ x + C y0 ⁇ y + C k0
  • G 2 (x, y) W, (x, y) - G 0 (x, y) - G, (x, y)
  • G 2 (x+1,y) G 2 (x,y)*C x2
  • G om L 0 ( ⁇ . ) x G tf «r L t ( f .y) ⁇ G DAT) +L 2 (x,y) ⁇ G D//r(
  • B DM '- 0 ( ⁇ .y) xS D ( r 0 +L , ⁇ .y) ⁇ s Dff r, + '- 2 ( .y) ⁇ s Dft ⁇ 2
  • a om *. ) x ⁇ D / ff *.y) ⁇ *D f 4 ⁇ , + *.y) x D cramp ⁇ .
  • the 8-bit color values are actually fraction between 0 and 1 inclusive.
  • the missing represented number is 1-2 "8 .
  • the value one is represented with all the bits set taking the place of the missing representation.
  • the 8-bit index value replaces the R value of the Diffuse and the Specular component of the color.
  • the normal vector has to be re-normalized after the interpolation:
  • At half-rate (accumulative) we interpolate up to four texture coordinates. This is done either using the plane equations or barycentric coordinates.
  • the r-texture coordinates are also interpolated for volume texture rendering but at one third of the full rate.
  • s[1] L 0 (x,y) ⁇ s 0 [1] + L ( (x,y)xs r [1] + L 2 (x l y) ⁇ s 2 [1]
  • is called the Level of Detail (LOD) and p is called the scale factor that governs the magnification or minificafion of the texture image
  • n and m are the width and the height of a two dimensional texture map.
  • the Fragment block passes s, t, r, and ⁇ to the Texture block for each active texture. Note that ⁇ is not the final LOD.
  • the Texture block applies additional rules such as LOD clamping to obtain the final value for ⁇ .
  • Fragment uses three caches to perform the needed operations.
  • the primary cache is the
  • Color cache It holds the color data for the primitive (triangle, line, or point).
  • the cache miss determination and replacement logic is actually located in the Mode Inject block.
  • the Fragment block normally receives a "hit" packet with an index pointing to the entry that hold the associated

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Graphics (AREA)
  • Geometry (AREA)
  • Computing Systems (AREA)
  • Image Generation (AREA)
  • Image Processing (AREA)
  • Image Input (AREA)
  • Processing Or Creating Images (AREA)
  • Complex Calculations (AREA)
EP99943867A 1998-08-20 1999-08-20 Graphics processor with deferred shading Withdrawn EP1105844A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US9733698P 1998-08-20 1998-08-20
US97336P 1998-08-20
US213990 1998-12-17
US09/213,990 US6771264B1 (en) 1998-08-20 1998-12-17 Method and apparatus for performing tangent space lighting and bump mapping in a deferred shading graphics processor
PCT/US1999/019254 WO2000019377A1 (en) 1998-08-20 1999-08-20 Graphics processor with deferred shading

Publications (1)

Publication Number Publication Date
EP1105844A1 true EP1105844A1 (en) 2001-06-13

Family

ID=26793137

Family Applications (2)

Application Number Title Priority Date Filing Date
EP99943867A Withdrawn EP1105844A1 (en) 1998-08-20 1999-08-20 Graphics processor with deferred shading
EP99945112A Withdrawn EP1138023A4 (en) 1998-08-20 1999-08-20 PIPELINE PROCESSOR FOR ADVANCED ASYNCHRONOUS SHAPED GRAPHICS

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP99945112A Withdrawn EP1138023A4 (en) 1998-08-20 1999-08-20 PIPELINE PROCESSOR FOR ADVANCED ASYNCHRONOUS SHAPED GRAPHICS

Country Status (6)

Country Link
US (5) US6771264B1 (ja)
EP (2) EP1105844A1 (ja)
JP (3) JP3657519B2 (ja)
KR (2) KR100478767B1 (ja)
AU (6) AU5687899A (ja)
WO (6) WO2000019377A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8106904B2 (en) 2002-03-20 2012-01-31 Nvidia Corporation Shader program generation system and method
US10332290B2 (en) * 2016-03-21 2019-06-25 Adobe Inc. Fast, coverage-optimized, resolution-independent and anti-aliased graphics processing

Families Citing this family (652)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8253729B1 (en) * 1983-05-09 2012-08-28 Geshwind David M Trimming depth buffer during 2D to 3D conversion
US6590996B1 (en) * 2000-02-14 2003-07-08 Digimarc Corporation Color adaptive watermarking
US7023437B1 (en) 1998-07-22 2006-04-04 Nvidia Corporation System and method for accelerating graphics processing using a post-geometry data stream during multiple-pass rendering
US6480205B1 (en) 1998-07-22 2002-11-12 Nvidia Corporation Method and apparatus for occlusion culling in graphics systems
US7068272B1 (en) 2000-05-31 2006-06-27 Nvidia Corporation System, method and article of manufacture for Z-value and stencil culling prior to rendering in a computer graphics processing pipeline
US6646639B1 (en) * 1998-07-22 2003-11-11 Nvidia Corporation Modified method and apparatus for improved occlusion culling in graphics systems
US7375727B1 (en) * 1998-07-22 2008-05-20 Nvidia Corporation System, method and computer program product for geometrically transforming geometric objects
WO2000011607A1 (en) * 1998-08-20 2000-03-02 Apple Computer, Inc. Deferred shading graphics pipeline processor
US6771264B1 (en) * 1998-08-20 2004-08-03 Apple Computer, Inc. Method and apparatus for performing tangent space lighting and bump mapping in a deferred shading graphics processor
US6978045B1 (en) * 1998-10-02 2005-12-20 Minolta Co., Ltd. Image-processing apparatus
GB2343601B (en) * 1998-11-06 2002-11-27 Videologic Ltd Shading and texturing 3-dimensional computer generated images
US6509905B2 (en) * 1998-11-12 2003-01-21 Hewlett-Packard Company Method and apparatus for performing a perspective projection in a graphics device of a computer graphics display system
JP3258286B2 (ja) * 1998-12-15 2002-02-18 インターナショナル・ビジネス・マシーンズ・コーポレーション 半透明物体と不透明物体とが混在する複数の物体についての画像データをコンピュータ表示画面に表示する描画方法および描画装置
US7224364B1 (en) * 1999-02-03 2007-05-29 Ati International Srl Optimal initial rasterization starting point
US6466223B1 (en) * 1999-03-24 2002-10-15 Microsoft Corporation Method and apparatus for texture memory management
US6791569B1 (en) * 1999-07-01 2004-09-14 Microsoft Corporation Antialiasing method using barycentric coordinates applied to lines
US6628836B1 (en) * 1999-10-05 2003-09-30 Hewlett-Packard Development Company, L.P. Sort middle, screen space, graphics geometry compression through redundancy elimination
JP3950926B2 (ja) * 1999-11-30 2007-08-01 エーユー オプトロニクス コーポレイション 画像表示方法、ホスト装置、画像表示装置、およびディスプレイ用インターフェイス
US7209140B1 (en) 1999-12-06 2007-04-24 Nvidia Corporation System, method and article of manufacture for a programmable vertex processing model with instruction set
US6870540B1 (en) * 1999-12-06 2005-03-22 Nvidia Corporation System, method and computer program product for a programmable pixel processing model with instruction set
US6844880B1 (en) 1999-12-06 2005-01-18 Nvidia Corporation System, method and computer program product for an improved programmable vertex processing model with instruction set
US6848029B2 (en) 2000-01-03 2005-01-25 Dirk Coldewey Method and apparatus for prefetching recursive data structures
US7058636B2 (en) * 2000-01-03 2006-06-06 Dirk Coldewey Method for prefetching recursive data structure traversals
US6731297B1 (en) * 2000-01-11 2004-05-04 Intel Corporation Multiple texture compositing
US7483042B1 (en) * 2000-01-13 2009-01-27 Ati International, Srl Video graphics module capable of blending multiple image layers
US6995761B1 (en) * 2000-01-14 2006-02-07 California Institute Of Technology Compression of 3D surfaces using progressive geometry
GB2363045B (en) * 2000-01-28 2004-06-02 Namco Ltd Game system and image creating method
US20020009293A1 (en) * 2000-02-03 2002-01-24 Aldrich Kipp A. HDTV video server
JP3349490B2 (ja) * 2000-02-14 2002-11-25 インターナショナル・ビジネス・マシーンズ・コーポレーション 画像表示方法、画像表示システム、ホスト装置、画像表示装置、およびディスプレイ用インターフェイス
US7159041B2 (en) * 2000-03-07 2007-01-02 Microsoft Corporation Method and system for defining and controlling algorithmic elements in a graphics display system
US7098925B1 (en) * 2000-03-10 2006-08-29 Intel Corporation Shading of images using texture
US7038811B1 (en) * 2000-03-31 2006-05-02 Canon Kabushiki Kaisha Standardized device characterization
US6819321B1 (en) * 2000-03-31 2004-11-16 Intel Corporation Method and apparatus for processing 2D operations in a tiled graphics architecture
CN1430769B (zh) * 2000-03-31 2012-05-30 英特尔公司 拼块式图形结构
US6532013B1 (en) 2000-05-31 2003-03-11 Nvidia Corporation System, method and article of manufacture for pixel shaders for programmable shading
US6690372B2 (en) 2000-05-31 2004-02-10 Nvidia Corporation System, method and article of manufacture for shadow mapping
US6664963B1 (en) 2000-05-31 2003-12-16 Nvidia Corporation System, method and computer program product for programmable shading using pixel shaders
US7119813B1 (en) * 2000-06-02 2006-10-10 Nintendo Co., Ltd. Variable bit field encoding
US7032031B2 (en) * 2000-06-23 2006-04-18 Cloudshield Technologies, Inc. Edge adapter apparatus and method
US7405734B2 (en) * 2000-07-18 2008-07-29 Silicon Graphics, Inc. Method and system for presenting three-dimensional computer graphics images using multiple graphics processing units
US6963347B1 (en) * 2000-08-04 2005-11-08 Ati International, Srl Vertex data processing with multiple threads of execution
US6980218B1 (en) * 2000-08-23 2005-12-27 Nintendo Co., Ltd. Method and apparatus for efficient generation of texture coordinate displacements for implementing emboss-style bump mapping in a graphics rendering system
US6999100B1 (en) 2000-08-23 2006-02-14 Nintendo Co., Ltd. Method and apparatus for anti-aliasing in a graphics system
US7002591B1 (en) * 2000-08-23 2006-02-21 Nintendo Co., Ltd. Method and apparatus for interleaved processing of direct and indirect texture coordinates in a graphics system
US7061502B1 (en) * 2000-08-23 2006-06-13 Nintendo Co., Ltd. Method and apparatus for providing logical combination of N alpha operations within a graphics system
US6825851B1 (en) 2000-08-23 2004-11-30 Nintendo Co., Ltd. Method and apparatus for environment-mapped bump-mapping in a graphics system
US8692844B1 (en) * 2000-09-28 2014-04-08 Nvidia Corporation Method and system for efficient antialiased rendering
US6828980B1 (en) * 2000-10-02 2004-12-07 Nvidia Corporation System, method and computer program product for z-texture mapping
US6914618B2 (en) * 2000-11-02 2005-07-05 Sun Microsystems, Inc. Methods and systems for producing A 3-D rotational image from A 2-D image
US7079133B2 (en) * 2000-11-16 2006-07-18 S3 Graphics Co., Ltd. Superscalar 3D graphics engine
US6778181B1 (en) 2000-12-07 2004-08-17 Nvidia Corporation Graphics processing system having a virtual texturing array
JP3705739B2 (ja) * 2000-12-11 2005-10-12 株式会社ナムコ 情報記憶媒体及びゲーム装置
US6975320B1 (en) 2000-12-12 2005-12-13 Micron Technology, Inc. Method and apparatus for level-of-detail computations
US6664961B2 (en) * 2000-12-20 2003-12-16 Rutgers, The State University Of Nj Resample and composite engine for real-time volume rendering
US20030063095A1 (en) * 2000-12-29 2003-04-03 Sun Microsystems, Inc. Statistic logic for collecting a histogram of pixel exponent values
JP2002252770A (ja) * 2001-02-22 2002-09-06 Matsushita Graphic Communication Systems Inc 画像情報の分類方法,画像符号化方法および画像符号化装置
US6791559B2 (en) * 2001-02-28 2004-09-14 3Dlabs Inc., Ltd Parameter circular buffers
US6828975B2 (en) * 2001-03-01 2004-12-07 Microsoft Corporation Method and system for managing graphics objects in a graphics display system
FR2822274B1 (fr) * 2001-03-13 2003-11-21 Stephane Clement Francoi Rehel Procede d'affichage et de manipulation d'un objet en trois dimensions et applications correspondantes
EP1258837A1 (en) * 2001-05-14 2002-11-20 Thomson Licensing S.A. Method to generate mutual photometric effects
US6859209B2 (en) * 2001-05-18 2005-02-22 Sun Microsystems, Inc. Graphics data accumulation for improved multi-layer texture performance
US7009615B1 (en) 2001-11-30 2006-03-07 Nvidia Corporation Floating point buffer system and method for use during programmable fragment processing in a graphics pipeline
US7006101B1 (en) 2001-06-08 2006-02-28 Nvidia Corporation Graphics API with branching capabilities
US7162716B2 (en) 2001-06-08 2007-01-09 Nvidia Corporation Software emulator for optimizing application-programmable vertex processing
WO2002101497A2 (en) 2001-06-08 2002-12-19 Nvidia Corporation System, method and computer program product for programmable fragment processing in a graphics pipeline
US6697064B1 (en) 2001-06-08 2004-02-24 Nvidia Corporation System, method and computer program product for matrix tracking during vertex processing in a graphics pipeline
US7456838B1 (en) 2001-06-08 2008-11-25 Nvidia Corporation System and method for converting a vertex program to a binary format capable of being executed by a hardware graphics pipeline
GB2378108B (en) * 2001-07-24 2005-08-17 Imagination Tech Ltd Three dimensional graphics system
US6778189B1 (en) 2001-08-24 2004-08-17 Nvidia Corporation Two-sided stencil testing system and method
US6734853B2 (en) * 2001-08-28 2004-05-11 Intel Corporation Method of using view frustrum culling for scaleable collision detection
US7145577B2 (en) * 2001-08-31 2006-12-05 Micron Technology, Inc. System and method for multi-sampling primitives to reduce aliasing
US6704025B1 (en) 2001-08-31 2004-03-09 Nvidia Corporation System and method for dual-depth shadow-mapping
US6924820B2 (en) * 2001-09-25 2005-08-02 Sun Microsystems, Inc. Over-evaluating samples during rasterization for improved datapath utilization
AU2002335799A1 (en) * 2001-10-10 2003-04-22 Sony Computer Entertainment America Inc. System and method for environment mapping
US6999076B2 (en) * 2001-10-29 2006-02-14 Ati Technologies, Inc. System, method, and apparatus for early culling
JP3761085B2 (ja) * 2001-11-27 2006-03-29 株式会社ソニー・コンピュータエンタテインメント 画像処理装置及びその構成部品、レンダリング処理方法
KR100450836B1 (ko) * 2001-12-11 2004-10-01 삼성전자주식회사 이차원 영상의 입체화 장치 및 방법
US7426534B2 (en) * 2001-12-19 2008-09-16 International Business Machines Corporation Method and system for caching message fragments using an expansion attribute in a fragment link tag
US6816161B2 (en) * 2002-01-30 2004-11-09 Sun Microsystems, Inc. Vertex assembly buffer and primitive launch buffer
US6774895B1 (en) * 2002-02-01 2004-08-10 Nvidia Corporation System and method for depth clamping in a hardware graphics pipeline
AU2003238511A1 (en) * 2002-02-01 2003-09-02 Koninklijke Philips Electronics N.V. Stepless 3d texture mapping in computer graphics
US7310103B2 (en) * 2002-03-05 2007-12-18 Sun Microsystems, Inc. Pipelined 2D viewport clip circuit
US7535913B2 (en) * 2002-03-06 2009-05-19 Nvidia Corporation Gigabit ethernet adapter supporting the iSCSI and IPSEC protocols
US7159212B2 (en) * 2002-03-08 2007-01-02 Electronic Arts Inc. Systems and methods for implementing shader-driven compilation of rendering assets
US6975322B2 (en) * 2002-03-12 2005-12-13 Sun Microsystems, Inc. Dynamically adjusting a number of rendering passes in a graphics system
US7015909B1 (en) * 2002-03-19 2006-03-21 Aechelon Technology, Inc. Efficient use of user-defined shaders to implement graphics operations
US8284844B2 (en) 2002-04-01 2012-10-09 Broadcom Corporation Video decoding system supporting multiple standards
US7376743B1 (en) * 2002-04-02 2008-05-20 Cisco Technology, Inc. Method and apparatus for load balancing in a virtual private network
US7009608B2 (en) * 2002-06-06 2006-03-07 Nvidia Corporation System and method of using multiple representations per object in computer graphics
US6771271B2 (en) * 2002-06-13 2004-08-03 Analog Devices, Inc. Apparatus and method of processing image data
AUPS300502A0 (en) * 2002-06-17 2002-07-11 Canon Kabushiki Kaisha Generating one or more linear blends
US6812927B1 (en) * 2002-06-18 2004-11-02 Nvidia Corporation System and method for avoiding depth clears using a stencil buffer
KR20030097507A (ko) * 2002-06-21 2003-12-31 삼성전자주식회사 평판 표시 장치의 색도 보정 장치 및 그 방법
US6977658B2 (en) * 2002-06-27 2005-12-20 Broadcom Corporation System for and method of performing an opacity calculation in a 3D graphics system
US6954215B2 (en) * 2002-06-28 2005-10-11 Microsoft Corporation System and method for employing non-alpha channel image data in an alpha-channel-aware environment
JP3845045B2 (ja) * 2002-07-23 2006-11-15 株式会社リコー 画像処理装置、画像処理方法、画像形成装置、印刷装置及びホストpc
FR2842977A1 (fr) 2002-07-24 2004-01-30 Total Immersion Procede et systeme permettant a un utilisateur de melanger en temps reel des images de synthese avec des images video
US7002599B2 (en) * 2002-07-26 2006-02-21 Sun Microsystems, Inc. Method and apparatus for hardware acceleration of clipping and graphical fill in display systems
US6857108B2 (en) * 2002-07-31 2005-02-15 Lsi Logic Corporation Interactive representation of structural dependencies in semiconductor design flows
US7257519B2 (en) * 2002-08-02 2007-08-14 Evans & Sutherland Computer Corporation System and method for weighted correction of an eyepoint position
US7176917B1 (en) 2002-08-09 2007-02-13 Avid Technology, Inc. Visual programming interface for a three-dimensional animation system for defining real time shaders using a real-time rendering engine application programming interface
US7508398B1 (en) 2002-08-27 2009-03-24 Nvidia Corporation Transparent antialiased memory access
US20040088682A1 (en) * 2002-11-05 2004-05-06 Thompson Ryan C. Method, program product, and apparatus for cache entry tracking, collision detection, and address reasignment in processor testcases
US7242400B2 (en) * 2002-11-13 2007-07-10 Ati Technologies Ulc Compression and decompression of data using plane equations
US7656416B2 (en) * 2002-11-27 2010-02-02 Ati Technologies, Inc. Apparatus for generating anti-aliased and stippled 3d lines, points and surfaces using multi-dimensional procedural texture coordinates
US7633506B1 (en) * 2002-11-27 2009-12-15 Ati Technologies Ulc Parallel pipeline graphics system
WO2004055697A1 (ja) * 2002-12-13 2004-07-01 Fujitsu Limited 処理方法、処理装置及びコンピュータプログラム
US7928997B2 (en) * 2003-02-06 2011-04-19 Nvidia Corporation Digital image compositing using a programmable graphics processor
US8749561B1 (en) * 2003-03-14 2014-06-10 Nvidia Corporation Method and system for coordinated data execution using a primary graphics processor and a secondary graphics processor
JP4590398B2 (ja) * 2003-04-03 2010-12-01 エヌエックスピー ビー ヴィ ランタイム構成可能仮想ビデオパイプライン
US7259765B2 (en) 2003-04-04 2007-08-21 S3 Graphics Co., Ltd. Head/data scheduling in 3D graphics
US7148888B2 (en) * 2003-04-04 2006-12-12 Via Technologies, Inc. Head/data request in 3D graphics
US7714858B2 (en) * 2003-04-18 2010-05-11 Hewlett-Packard Development Company, L.P. Distributed rendering of interactive soft shadows
JP3966832B2 (ja) 2003-04-28 2007-08-29 株式会社東芝 描画処理装置、及び、描画処理方法
US7218331B2 (en) * 2003-05-13 2007-05-15 Via Technologies, Inc. Bounding box in 3D graphics
US20050017969A1 (en) * 2003-05-27 2005-01-27 Pradeep Sen Computer graphics rendering using boundary information
US7681112B1 (en) 2003-05-30 2010-03-16 Adobe Systems Incorporated Embedded reuse meta information
US7852405B1 (en) * 2003-06-27 2010-12-14 Zoran Corporation Method and apparatus for high definition capture
US8275910B1 (en) * 2003-07-02 2012-09-25 Apple Inc. Source packet bridge
US7164420B2 (en) * 2003-07-24 2007-01-16 Autodesk, Inc. Ray tracing hierarchy
WO2005013066A2 (en) * 2003-07-25 2005-02-10 New York University Logic arrangement, data structure, system and method for miltilinear representation of multimodal data ensembles for synthesis, rotation and compression
US7139005B2 (en) * 2003-09-13 2006-11-21 Microsoft Corporation Optimized fixed-point mathematical library and graphics functions for a software-implemented graphics rendering system and method using a normalized homogenous coordinate system
US8872833B2 (en) 2003-09-15 2014-10-28 Nvidia Corporation Integrated circuit configuration system and method
US8732644B1 (en) 2003-09-15 2014-05-20 Nvidia Corporation Micro electro mechanical switch system and method for testing and configuring semiconductor functional circuits
US8775997B2 (en) 2003-09-15 2014-07-08 Nvidia Corporation System and method for testing and configuring semiconductor functional circuits
CN100483463C (zh) * 2003-09-17 2009-04-29 皇家飞利浦电子股份有限公司 用于在3-d图像显示屏上显示3-d图像的系统和方法
US7593010B2 (en) * 2003-09-18 2009-09-22 Microsoft Corporation Software-implemented transform and lighting module and pipeline for graphics rendering on embedded platforms using a fixed-point normalized homogenous coordinate system
JP2005100176A (ja) * 2003-09-25 2005-04-14 Sony Corp 画像処理装置およびその方法
JP4183082B2 (ja) * 2003-09-26 2008-11-19 シャープ株式会社 3次元画像描画装置および3次元画像描画方法
KR100546383B1 (ko) * 2003-09-29 2006-01-26 삼성전자주식회사 눈에 보이지 않는 프래그먼트를 처리하기 위한 3차원그래픽스 렌더링 엔진 및 그 방법
US8133115B2 (en) 2003-10-22 2012-03-13 Sony Computer Entertainment America Llc System and method for recording and displaying a graphical path in a video game
US8174531B1 (en) 2003-10-29 2012-05-08 Nvidia Corporation Programmable graphics processor for multithreaded execution of programs
US7139003B1 (en) * 2003-12-15 2006-11-21 Nvidia Corporation Methods of processing graphics data including reading and writing buffers
US7836276B2 (en) * 2005-12-02 2010-11-16 Nvidia Corporation System and method for processing thread groups in a SIMD architecture
US8860737B2 (en) * 2003-10-29 2014-10-14 Nvidia Corporation Programmable graphics processor for multithreaded execution of programs
US8823718B2 (en) * 2003-11-14 2014-09-02 Microsoft Corporation Systems and methods for downloading algorithmic elements to a coprocessor and corresponding techniques
KR20050047741A (ko) * 2003-11-18 2005-05-23 삼성전자주식회사 영상처리장치 및 그 방법
US7015914B1 (en) 2003-12-10 2006-03-21 Nvidia Corporation Multiple data buffers for processing graphics data
US7102645B2 (en) * 2003-12-15 2006-09-05 Seiko Epson Corporation Graphics display controller providing enhanced read/write efficiency for interfacing with a RAM-integrated graphics display device
US7053893B1 (en) * 2003-12-15 2006-05-30 Nvidia Corporation Position conflict detection and avoidance in a programmable graphics processor using tile coverage data
US7053904B1 (en) * 2003-12-15 2006-05-30 Nvidia Corporation Position conflict detection and avoidance in a programmable graphics processor
US7420568B1 (en) * 2003-12-17 2008-09-02 Nvidia Corporation System and method for packing data in different formats in a tiled graphics memory
US8711161B1 (en) 2003-12-18 2014-04-29 Nvidia Corporation Functional component compensation reconfiguration system and method
US7221368B1 (en) * 2003-12-18 2007-05-22 Nvidia Corporation Stippled lines using direct distance evaluation
US7450120B1 (en) 2003-12-19 2008-11-11 Nvidia Corporation Apparatus, system, and method for Z-culling
US8269769B1 (en) 2003-12-22 2012-09-18 Nvidia Corporation Occlusion prediction compression system and method
US8390619B1 (en) * 2003-12-22 2013-03-05 Nvidia Corporation Occlusion prediction graphics processing system and method
US8854364B1 (en) * 2003-12-22 2014-10-07 Nvidia Corporation Tight depth range occlusion prediction system and method
US7995056B1 (en) 2003-12-22 2011-08-09 Nvidia Corporation Culling data selection system and method
US7433364B2 (en) * 2003-12-24 2008-10-07 Intel Corporation Method for optimizing queuing performance
US8643659B1 (en) 2003-12-31 2014-02-04 3Dlabs Inc., Ltd. Shader with global and instruction caches
US9098943B1 (en) 2003-12-31 2015-08-04 Ziilabs Inc., Ltd. Multiple simultaneous bin sizes
US7281122B2 (en) * 2004-01-14 2007-10-09 Ati Technologies Inc. Method and apparatus for nested control flow of instructions using context information and instructions having extra bits
US20050195186A1 (en) * 2004-03-02 2005-09-08 Ati Technologies Inc. Method and apparatus for object based visibility culling
FI117655B (fi) * 2004-03-25 2006-12-29 Cadfaster Oy Menetelmä tietokoneavusteisen polygonimallin prosessointiin, laite ja tietokoneohjelma
US7609902B2 (en) * 2004-04-13 2009-10-27 Microsoft Corporation Implementation of discrete cosine transformation and its inverse on programmable graphics processor
US7847800B2 (en) * 2004-04-16 2010-12-07 Apple Inc. System for emulating graphics operations
US7248265B2 (en) * 2004-04-16 2007-07-24 Apple Inc. System and method for processing graphics operations with graphics processing unit
US7636489B2 (en) * 2004-04-16 2009-12-22 Apple Inc. Blur computation algorithm
US8704837B2 (en) * 2004-04-16 2014-04-22 Apple Inc. High-level program interface for graphics operations
US7231632B2 (en) * 2004-04-16 2007-06-12 Apple Computer, Inc. System for reducing the number of programs necessary to render an image
US8134561B2 (en) * 2004-04-16 2012-03-13 Apple Inc. System for optimizing graphics operations
KR100601952B1 (ko) * 2004-04-20 2006-07-14 삼성전자주식회사 3차원 그래픽 데이터의 재구성장치 및 방법
JP4914829B2 (ja) 2004-05-14 2012-04-11 エヌヴィディア コーポレイション 低電力プログラマブルプロセッサ
US8743142B1 (en) 2004-05-14 2014-06-03 Nvidia Corporation Unified data fetch graphics processing system and method
US8711155B2 (en) * 2004-05-14 2014-04-29 Nvidia Corporation Early kill removal graphics processing system and method
US8736620B2 (en) * 2004-05-14 2014-05-27 Nvidia Corporation Kill bit graphics processing system and method
US7091982B2 (en) * 2004-05-14 2006-08-15 Nvidia Corporation Low power programmable processor
US7389006B2 (en) * 2004-05-14 2008-06-17 Nvidia Corporation Auto software configurable register address space for low power programmable processor
US8432394B1 (en) 2004-05-14 2013-04-30 Nvidia Corporation Method and system for implementing clamped z value interpolation in a raster stage of a graphics pipeline
US20060007234A1 (en) * 2004-05-14 2006-01-12 Hutchins Edward A Coincident graphics pixel scoreboard tracking system and method
US7190366B2 (en) 2004-05-14 2007-03-13 Nvidia Corporation Method and system for a general instruction raster stage that generates programmable pixel packets
US8411105B1 (en) 2004-05-14 2013-04-02 Nvidia Corporation Method and system for computing pixel parameters
US7079156B1 (en) * 2004-05-14 2006-07-18 Nvidia Corporation Method and system for implementing multiple high precision and low precision interpolators for a graphics pipeline
US8416242B1 (en) 2004-05-14 2013-04-09 Nvidia Corporation Method and system for interpolating level-of-detail in graphics processors
US8736628B1 (en) 2004-05-14 2014-05-27 Nvidia Corporation Single thread graphics processing system and method
US8687010B1 (en) 2004-05-14 2014-04-01 Nvidia Corporation Arbitrary size texture palettes for use in graphics systems
US8860722B2 (en) * 2004-05-14 2014-10-14 Nvidia Corporation Early Z scoreboard tracking system and method
JP4451717B2 (ja) 2004-05-31 2010-04-14 株式会社ソニー・コンピュータエンタテインメント 情報処理装置および情報処理方法
US20050275733A1 (en) * 2004-06-10 2005-12-15 Philip Chao Method and apparatus of rendering a video image by polynomial evaluation
US7382377B1 (en) * 2004-06-17 2008-06-03 Nvidia Corporation Render to texture cull
WO2006000087A1 (en) 2004-06-23 2006-01-05 Quin Media Arts And Sciences Inc. Sculptural imaging with optical tiles
US7397964B2 (en) * 2004-06-24 2008-07-08 Apple Inc. Gaussian blur approximation suitable for GPU
US8068103B2 (en) * 2004-06-24 2011-11-29 Apple Inc. User-interface design
US8130237B2 (en) * 2004-06-24 2012-03-06 Apple Inc. Resolution independent user interface design
US7490295B2 (en) 2004-06-25 2009-02-10 Apple Inc. Layer for accessing user interface elements
US8302020B2 (en) 2004-06-25 2012-10-30 Apple Inc. Widget authoring and editing environment
US7546543B2 (en) 2004-06-25 2009-06-09 Apple Inc. Widget authoring and editing environment
US8239749B2 (en) 2004-06-25 2012-08-07 Apple Inc. Procedurally expressing graphic objects for web pages
US7652678B2 (en) * 2004-06-25 2010-01-26 Apple Inc. Partial display updates in a windowing system using a programmable graphics processing unit
US20050285866A1 (en) * 2004-06-25 2005-12-29 Apple Computer, Inc. Display-wide visual effects for a windowing system using a programmable graphics processing unit
US8566732B2 (en) 2004-06-25 2013-10-22 Apple Inc. Synchronization of widgets and dashboards
US7761800B2 (en) 2004-06-25 2010-07-20 Apple Inc. Unified interest layer for user interface
US8453065B2 (en) 2004-06-25 2013-05-28 Apple Inc. Preview and installation of user interface elements in a display environment
US7755629B2 (en) * 2004-06-30 2010-07-13 Canon Kabushiki Kaisha Method of rendering graphic objects
US7518608B2 (en) * 2004-07-30 2009-04-14 Sony Corporation Z-depth matting of particles in image rendering
US7256796B1 (en) * 2004-08-03 2007-08-14 Nvidia Corporation Per-fragment control for writing an output buffer
US7400325B1 (en) * 2004-08-06 2008-07-15 Nvidia Corporation Culling before setup in viewport and culling unit
US20060033736A1 (en) * 2004-08-10 2006-02-16 Wang Andy W Enhanced Color and Lighting Model for Computer Graphics Productions
US7564462B2 (en) * 2004-08-31 2009-07-21 Teranex Systems, Inc. Method and apparatus for reading and writing pixel-aligned subframes in a frame buffer
US7218291B2 (en) * 2004-09-13 2007-05-15 Nvidia Corporation Increased scalability in the fragment shading pipeline
US8723231B1 (en) 2004-09-15 2014-05-13 Nvidia Corporation Semiconductor die micro electro-mechanical switch management system and method
US7286139B2 (en) * 2004-09-17 2007-10-23 Via Technologies, Inc. Partial guardband clipping
US20060061577A1 (en) * 2004-09-22 2006-03-23 Vijay Subramaniam Efficient interface and assembler for a graphics processor
US8711156B1 (en) 2004-09-30 2014-04-29 Nvidia Corporation Method and system for remapping processing elements in a pipeline of a graphics processing unit
US20060071933A1 (en) * 2004-10-06 2006-04-06 Sony Computer Entertainment Inc. Application binary interface for multi-pass shaders
US20060082577A1 (en) * 2004-10-20 2006-04-20 Ugs Corp. System, method, and computer program product for dynamic shader generation
US7385604B1 (en) * 2004-11-04 2008-06-10 Nvidia Corporation Fragment scattering
JP4692956B2 (ja) * 2004-11-22 2011-06-01 株式会社ソニー・コンピュータエンタテインメント 描画処理装置および描画処理方法
US7227551B2 (en) * 2004-12-23 2007-06-05 Apple Inc. Manipulating text and graphic appearance
US7209139B1 (en) * 2005-01-07 2007-04-24 Electronic Arts Efficient rendering of similar objects in a three-dimensional graphics engine
US8140975B2 (en) 2005-01-07 2012-03-20 Apple Inc. Slide show navigation
JP4812073B2 (ja) * 2005-01-31 2011-11-09 キヤノン株式会社 画像撮像装置、画像撮像方法、プログラムおよび記録媒体
KR100612890B1 (ko) * 2005-02-17 2006-08-14 삼성전자주식회사 3차원 이미지의 다중 특수 효과 표현 방법 및 장치
US7242169B2 (en) * 2005-03-01 2007-07-10 Apple Inc. Method and apparatus for voltage compensation for parasitic impedance
US8089486B2 (en) * 2005-03-21 2012-01-03 Qualcomm Incorporated Tiled prefetched and cached depth buffer
WO2006101367A1 (en) * 2005-03-24 2006-09-28 Lg Electronics Inc. Method of executing scanning in broadband wireless access system
JP2006293553A (ja) * 2005-04-07 2006-10-26 Aisin Aw Co Ltd フォントデータの回転処理装置及び地図表示システム
US7479965B1 (en) * 2005-04-12 2009-01-20 Nvidia Corporation Optimized alpha blend for anti-aliased render
US9363481B2 (en) * 2005-04-22 2016-06-07 Microsoft Technology Licensing, Llc Protected media pipeline
US7463261B1 (en) * 2005-04-29 2008-12-09 Adobe Systems Incorporated Three-dimensional image compositing on a GPU utilizing multiple transformations
US7499051B1 (en) 2005-04-29 2009-03-03 Adobe Systems Incorporated GPU assisted 3D compositing
US7802028B2 (en) * 2005-05-02 2010-09-21 Broadcom Corporation Total dynamic sharing of a transaction queue
US7349066B2 (en) * 2005-05-05 2008-03-25 Asml Masktools B.V. Apparatus, method and computer program product for performing a model based optical proximity correction factoring neighbor influence
US8427496B1 (en) 2005-05-13 2013-04-23 Nvidia Corporation Method and system for implementing compression across a graphics bus interconnect
US8386628B1 (en) * 2005-05-23 2013-02-26 Glance Networks, Inc. Method and apparatus for reducing the amount of information that must be transmitted to slower viewers over a remote viewing session
US7894528B2 (en) * 2005-05-25 2011-02-22 Yissum Research Development Company Of The Hebrew University Of Jerusalem Fast and robust motion computations using direct methods
US8543931B2 (en) 2005-06-07 2013-09-24 Apple Inc. Preview including theme based installation of user interface elements in a display environment
US7636126B2 (en) 2005-06-22 2009-12-22 Sony Computer Entertainment Inc. Delay matching in audio/video systems
US9298311B2 (en) * 2005-06-23 2016-03-29 Apple Inc. Trackpad sensitivity compensation
US7432937B2 (en) * 2005-06-30 2008-10-07 Intel Corporation System and method for concave polygon rasterization
US7496416B2 (en) * 2005-08-01 2009-02-24 Luxology, Llc Input/output curve editor
US20070035553A1 (en) * 2005-08-12 2007-02-15 Microsoft Corporation General framework for aligning textures
US7436412B2 (en) * 2005-08-24 2008-10-14 Qualcomm Incorporated Graphics engine with efficient interpolation
US7551177B2 (en) 2005-08-31 2009-06-23 Ati Technologies, Inc. Methods and apparatus for retrieving and combining samples of graphics information
US8189908B2 (en) * 2005-09-02 2012-05-29 Adobe Systems, Inc. System and method for compressing video data and alpha channel data using a single stream
US8014615B2 (en) * 2005-09-02 2011-09-06 Adobe Systems Incorporated System and method for decompressing video data and alpha channel data using a single stream
US7433191B2 (en) * 2005-09-30 2008-10-07 Apple Inc. Thermal contact arrangement
US7441230B2 (en) * 2005-10-07 2008-10-21 Lucasfilm Entertainment Company Ltd. Method of utilizing product proxies with a dependency graph
US8144149B2 (en) * 2005-10-14 2012-03-27 Via Technologies, Inc. System and method for dynamically load balancing multiple shader stages in a shared pool of processing units
US8266232B2 (en) * 2005-10-15 2012-09-11 International Business Machines Corporation Hardware processing of commands within virtual client computing environment
US9104294B2 (en) 2005-10-27 2015-08-11 Apple Inc. Linked widgets
US7954064B2 (en) 2005-10-27 2011-05-31 Apple Inc. Multiple dashboards
US7752556B2 (en) 2005-10-27 2010-07-06 Apple Inc. Workflow widgets
US8543824B2 (en) 2005-10-27 2013-09-24 Apple Inc. Safe distribution and use of content
US7743336B2 (en) 2005-10-27 2010-06-22 Apple Inc. Widget security
US7414624B2 (en) * 2005-10-28 2008-08-19 Intel Corporation Apparatus and method for a frustum culling algorithm suitable for hardware implementation
US20070097139A1 (en) * 2005-11-02 2007-05-03 Chao-Chin Chen Method and apparatus of primitive filter in graphic process applications
GB0524804D0 (en) 2005-12-05 2006-01-11 Falanx Microsystems As Method of and apparatus for processing graphics
US7934255B1 (en) * 2005-11-08 2011-04-26 Nvidia Corporation Apparatus, system, and method for offloading packet classification
US8294731B2 (en) * 2005-11-15 2012-10-23 Advanced Micro Devices, Inc. Buffer management in vector graphics hardware
US7707514B2 (en) 2005-11-18 2010-04-27 Apple Inc. Management of user interface elements in a display environment
US8624909B2 (en) * 2005-11-21 2014-01-07 Vixs Systems Inc. Image processing system and method thereof
US7598711B2 (en) * 2005-11-23 2009-10-06 Apple Inc. Power source switchover apparatus and method
DE112005003766B4 (de) * 2005-11-30 2010-06-17 Fujitsu Microelectronics Ltd. Gerät für dreidimensionale Grafik, Verfahren für dreidimensionale Grafik, Programm für dreidimensionale Grafik und Aufzeichnungsmedium
US8803872B2 (en) * 2005-12-01 2014-08-12 Intel Corporation Computer graphics processor and method for rendering a three-dimensional image on a display screen
US7439988B1 (en) 2005-12-05 2008-10-21 Nvidia Corporation Apparatus, system, and method for clipping graphics primitives with respect to a clipping plane
US7616218B1 (en) 2005-12-05 2009-11-10 Nvidia Corporation Apparatus, system, and method for clipping graphics primitives
US7434032B1 (en) 2005-12-13 2008-10-07 Nvidia Corporation Tracking register usage during multithreaded processing using a scoreboard having separate memory regions and storing sequential register size indicators
US7593018B1 (en) * 2005-12-14 2009-09-22 Nvidia Corp. Method and apparatus for providing explicit weights for texture filtering
US7423642B2 (en) * 2005-12-14 2008-09-09 Winbond Electronics Corporation Efficient video frame capturing
US8698811B1 (en) 2005-12-15 2014-04-15 Nvidia Corporation Nested boustrophedonic patterns for rasterization
US8701091B1 (en) 2005-12-15 2014-04-15 Nvidia Corporation Method and system for providing a generic console interface for a graphics application
US9123173B2 (en) * 2005-12-15 2015-09-01 Nvidia Corporation Method for rasterizing non-rectangular tile groups in a raster stage of a graphics pipeline
US8390645B1 (en) 2005-12-19 2013-03-05 Nvidia Corporation Method and system for rendering connecting antialiased line segments
US7791617B2 (en) * 2005-12-19 2010-09-07 Nvidia Corporation Method and system for rendering polygons having abutting edges
US7714877B1 (en) 2005-12-19 2010-05-11 Nvidia Corporation Apparatus, system, and method for determining clipping distances
US9117309B1 (en) 2005-12-19 2015-08-25 Nvidia Corporation Method and system for rendering polygons with a bounding box in a graphics processor unit
US7420572B1 (en) * 2005-12-19 2008-09-02 Nvidia Corporation Apparatus, system, and method for clipping graphics primitives with accelerated context switching
US8300059B2 (en) * 2006-02-03 2012-10-30 Ati Technologies Ulc Method and apparatus for selecting a mip map level based on a min-axis value for texture mapping
JP4782583B2 (ja) * 2006-02-23 2011-09-28 株式会社バンダイナムコゲームス プログラム、情報記憶媒体及び画像生成システム
JP4734138B2 (ja) * 2006-02-23 2011-07-27 株式会社バンダイナムコゲームス プログラム、情報記憶媒体及び画像生成システム
JP4734137B2 (ja) * 2006-02-23 2011-07-27 株式会社バンダイナムコゲームス プログラム、情報記憶媒体及び画像生成システム
US8006236B1 (en) * 2006-02-24 2011-08-23 Nvidia Corporation System and method for compiling high-level primitive programs into primitive program micro-code
US8171461B1 (en) 2006-02-24 2012-05-01 Nvidia Coporation Primitive program compilation for flat attributes with provoking vertex independence
US7825933B1 (en) * 2006-02-24 2010-11-02 Nvidia Corporation Managing primitive program vertex attributes as per-attribute arrays
US7891012B1 (en) 2006-03-01 2011-02-15 Nvidia Corporation Method and computer-usable medium for determining the authorization status of software
US8452981B1 (en) 2006-03-01 2013-05-28 Nvidia Corporation Method for author verification and software authorization
TWI319166B (en) * 2006-03-06 2010-01-01 Via Tech Inc Method and related apparatus for graphic processing
JP2007287085A (ja) * 2006-04-20 2007-11-01 Fuji Xerox Co Ltd 画像処理装置及びプログラム
JP2007287084A (ja) * 2006-04-20 2007-11-01 Fuji Xerox Co Ltd 画像処理装置及びプログラム
EP2008248A2 (en) 2006-04-20 2008-12-31 Telefonaktiebolaget LM Ericsson (publ) Image processing
US8766995B2 (en) * 2006-04-26 2014-07-01 Qualcomm Incorporated Graphics system with configurable caches
US20080082567A1 (en) * 2006-05-01 2008-04-03 Bezanson Jeffrey W Apparatuses, Methods And Systems For Vector Operations And Storage In Matrix Models
US7880746B2 (en) 2006-05-04 2011-02-01 Sony Computer Entertainment Inc. Bandwidth management through lighting control of a user environment via a display device
US7965859B2 (en) 2006-05-04 2011-06-21 Sony Computer Entertainment Inc. Lighting control of a user environment via a display device
SG137754A1 (en) * 2006-05-12 2007-12-28 Nvidia Corp Antialiasing using multiple display heads of a graphics processor
US20070268289A1 (en) * 2006-05-16 2007-11-22 Chun Yu Graphics system with dynamic reposition of depth engine
US7395180B2 (en) * 2006-05-17 2008-07-01 Lockheed Martin Corporation Efficient translation of data from a two-dimensional array to a wedge
US8884972B2 (en) 2006-05-25 2014-11-11 Qualcomm Incorporated Graphics processor with arithmetic and elementary function units
US8869147B2 (en) * 2006-05-31 2014-10-21 Qualcomm Incorporated Multi-threaded processor with deferred thread output control
KR101136684B1 (ko) * 2006-06-09 2012-04-23 도요타지도샤가부시키가이샤 데이터 갱신 시스템, 네비게이션 장치, 서버 장치, 및 데이터 갱신 방법
US8644643B2 (en) 2006-06-14 2014-02-04 Qualcomm Incorporated Convolution filtering in a graphics processor
US7940262B2 (en) * 2006-06-15 2011-05-10 Right Hemisphere Limited Unification and part hiding in three dimensional geometric data
US20070291031A1 (en) * 2006-06-15 2007-12-20 Right Hemisphere Limited Three dimensional geometric data correction
US8766996B2 (en) * 2006-06-21 2014-07-01 Qualcomm Incorporated Unified virtual addressed register file
US8928676B2 (en) * 2006-06-23 2015-01-06 Nvidia Corporation Method for parallel fine rasterization in a raster stage of a graphics pipeline
JP2008009696A (ja) * 2006-06-29 2008-01-17 Fuji Xerox Co Ltd 画像処理装置及びプログラム
JP4795138B2 (ja) * 2006-06-29 2011-10-19 富士ゼロックス株式会社 画像処理装置及びプログラム
US8284204B2 (en) * 2006-06-30 2012-10-09 Nokia Corporation Apparatus, method and a computer program product for providing a unified graphics pipeline for stereoscopic rendering
US8477134B1 (en) 2006-06-30 2013-07-02 Nvidia Corporation Conservative triage of polygon status using low precision edge evaluation and high precision edge evaluation
US8560495B1 (en) * 2006-07-07 2013-10-15 Sybase, Inc. System and method for synchronizing message processing in a continuous processing system
JP4979287B2 (ja) * 2006-07-14 2012-07-18 富士ゼロックス株式会社 画像処理装置及びプログラム
US8633927B2 (en) * 2006-07-25 2014-01-21 Nvidia Corporation Re-render acceleration of frame with lighting change
US9070213B2 (en) * 2006-07-26 2015-06-30 Nvidia Corporation Tile based precision rasterization in a graphics pipeline
US8085264B1 (en) 2006-07-26 2011-12-27 Nvidia Corporation Tile output using multiple queue output buffering in a raster stage
US8436864B2 (en) * 2006-08-01 2013-05-07 Nvidia Corporation Method and user interface for enhanced graphical operation organization
US8436870B1 (en) 2006-08-01 2013-05-07 Nvidia Corporation User interface and method for graphical processing analysis
US7778800B2 (en) * 2006-08-01 2010-08-17 Nvidia Corporation Method and system for calculating performance parameters for a processor
US8963932B1 (en) 2006-08-01 2015-02-24 Nvidia Corporation Method and apparatus for visualizing component workloads in a unified shader GPU architecture
US8607151B2 (en) * 2006-08-01 2013-12-10 Nvidia Corporation Method and system for debugging a graphics pipeline subunit
US7952588B2 (en) * 2006-08-03 2011-05-31 Qualcomm Incorporated Graphics processing unit with extended vertex cache
US8869027B2 (en) 2006-08-04 2014-10-21 Apple Inc. Management and generation of dashboards
US8493388B2 (en) * 2006-08-09 2013-07-23 Siemens Medical Solutions Usa, Inc. Modular volume rendering using visual programming
KR20080014402A (ko) * 2006-08-11 2008-02-14 삼성전자주식회사 컴퓨터 그래픽스 데이터 처리방법과 데이터 처리장치
US7773092B1 (en) * 2006-08-24 2010-08-10 Nvidia Corporation Texture map coverage optimization
KR100745768B1 (ko) * 2006-08-29 2007-08-02 삼성전자주식회사 전력 소비를 감소시키기 위한 lod 값 계산 방법과이것을 이용한 3차원 렌더링 시스템
US7905610B1 (en) * 2006-08-29 2011-03-15 Nvidia Corporation Graphics processor system and associated method for projecting an image onto a three-dimensional object
US8237739B2 (en) * 2006-09-12 2012-08-07 Qualcomm Incorporated Method and device for performing user-defined clipping in object space
JP4995827B2 (ja) * 2006-09-13 2012-08-08 パナソニック株式会社 画像処理装置、画像処理用集積回路、画像処理システム、インプットアセンブラ装置、インプットアセンブル用集積回路
JP4079378B2 (ja) 2006-09-21 2008-04-23 株式会社コナミデジタルエンタテインメント 画像処理装置、画像処理装置の制御方法及びプログラム
US8537168B1 (en) 2006-11-02 2013-09-17 Nvidia Corporation Method and system for deferred coverage mask generation in a raster stage
US8237738B1 (en) 2006-11-02 2012-08-07 Nvidia Corporation Smooth rasterization of polygonal graphics primitives
US8427487B1 (en) 2006-11-02 2013-04-23 Nvidia Corporation Multiple tile output using interface compression in a raster stage
US8228328B1 (en) * 2006-11-03 2012-07-24 Nvidia Corporation Early Z testing for multiple render targets
US8482567B1 (en) 2006-11-03 2013-07-09 Nvidia Corporation Line rasterization techniques
US7701459B1 (en) * 2006-11-03 2010-04-20 Nvidia Corporation Primitive oriented assembly for parallel vertex/geometry processing
US8059124B2 (en) 2006-11-28 2011-11-15 Adobe Systems Incorporated Temporary non-tiled rendering of 3D objects
US8300050B2 (en) * 2006-11-28 2012-10-30 Adobe Systems Incorporated Temporary low resolution rendering of 3D objects
GB0710795D0 (en) * 2007-06-05 2007-07-18 Arm Norway As Method of and apparatus for processing graphics
US9965886B2 (en) 2006-12-04 2018-05-08 Arm Norway As Method of and apparatus for processing graphics
WO2008073455A1 (en) * 2006-12-11 2008-06-19 Koplar Interactive Systems International, L.L.C. Spatial data encoding and decoding
WO2008073449A2 (en) 2006-12-12 2008-06-19 Evans & Sutherland Computer Corporation System and method for aligning rgb light in a single modulator projector
US8736627B2 (en) * 2006-12-19 2014-05-27 Via Technologies, Inc. Systems and methods for providing a shared buffer in a multiple FIFO environment
US7580035B2 (en) * 2006-12-28 2009-08-25 Intel Corporation Real-time collision detection using clipping
US7982733B2 (en) * 2007-01-05 2011-07-19 Qualcomm Incorporated Rendering 3D video images on a stereo-enabled display
US8638328B2 (en) * 2007-01-05 2014-01-28 Landmark Graphics Corporation Systems and methods for visualizing multiple volumetric data sets in real time
ITMI20070038A1 (it) * 2007-01-12 2008-07-13 St Microelectronics Srl Dispositivo di renderizzazione per grafica a tre dimensioni con architettura di tipo sort-middle.
CN103310480B (zh) 2007-01-24 2016-12-28 英特尔公司 通过使用可置换的剔除程序提高图形性能的方法和装置
US7746355B1 (en) * 2007-01-24 2010-06-29 Vivante Corporation Method for distributed clipping outside of view volume
US8549500B2 (en) * 2007-02-14 2013-10-01 The Mathworks, Inc. Saving and loading graphical processing unit (GPU) arrays providing high computational capabilities in a computing environment
US20080218512A1 (en) * 2007-02-20 2008-09-11 Ofer Alon System and method for interactive masking and modifying of 3d objects
US7473258B2 (en) * 2007-03-08 2009-01-06 Cardica, Inc. Surgical stapler
US8471862B2 (en) * 2007-03-09 2013-06-25 Ati Technologies Ulc Offset tiles in vector graphics
US7694193B2 (en) * 2007-03-13 2010-04-06 Hewlett-Packard Development Company, L.P. Systems and methods for implementing a stride value for accessing memory
JP4446201B2 (ja) * 2007-03-30 2010-04-07 アイシン・エィ・ダブリュ株式会社 画像認識装置及び画像認識方法
US8155826B2 (en) * 2007-03-30 2012-04-10 Aisin Aw Co., Ltd. Vehicle behavior learning apparatuses, methods, and programs
JP5306317B2 (ja) * 2007-04-04 2013-10-02 テレフオンアクチーボラゲット エル エム エリクソン(パブル) ベクトルを使用する画像処理
US10605610B2 (en) * 2007-04-09 2020-03-31 Ian Cummings Apparatus and methods for reducing data transmission in wireless client-server navigation systems
JP4588736B2 (ja) * 2007-04-12 2010-12-01 富士フイルム株式会社 画像処理方法および装置並びにプログラム
US8633948B2 (en) 2007-04-16 2014-01-21 Sunfish Studio, Llc Single-pass and order-independent transparency in computer graphics using constant memory
GB2448717B (en) * 2007-04-25 2012-09-19 David Hostettler Wain Method and apparatus for the efficient animation of textures based on images and graphical components
US8203560B2 (en) * 2007-04-27 2012-06-19 Sony Corporation Method for predictively splitting procedurally generated particle data into screen-space boxes
US20080273113A1 (en) * 2007-05-02 2008-11-06 Windbond Electronics Corporation Integrated graphics and KVM system
US7876677B2 (en) * 2007-05-22 2011-01-25 Apple Inc. Transmission control protocol queue sorting
FR2917211A1 (fr) 2007-06-08 2008-12-12 St Microelectronics Sa Procede et dispositif de generation d'images graphiques
US8558832B1 (en) * 2007-06-19 2013-10-15 Nvida Corporation System, method, and computer program product for generating a plurality of two-dimensional images and depth maps for a scene at a point in time
KR101378372B1 (ko) * 2007-07-12 2014-03-27 삼성전자주식회사 디지털 이미지 처리장치, 그 제어방법 및 제어방법을실행시키기 위한 프로그램을 저장한 기록매체
US8954871B2 (en) 2007-07-18 2015-02-10 Apple Inc. User-centric widgets and dashboards
US7925100B2 (en) * 2007-07-31 2011-04-12 Microsoft Corporation Tiled packaging of vector image data
US7805579B2 (en) * 2007-07-31 2010-09-28 International Business Machines Corporation Methods and arrangements for multi-buffering data
US8667415B2 (en) 2007-08-06 2014-03-04 Apple Inc. Web widgets
US8441497B1 (en) 2007-08-07 2013-05-14 Nvidia Corporation Interpolation of vertex attributes in a graphics processor
US8296738B1 (en) 2007-08-13 2012-10-23 Nvidia Corporation Methods and systems for in-place shader debugging and performance tuning
US9035957B1 (en) 2007-08-15 2015-05-19 Nvidia Corporation Pipeline debug statistics system and method
US8521800B1 (en) 2007-08-15 2013-08-27 Nvidia Corporation Interconnected arithmetic logic units
US8599208B2 (en) * 2007-08-15 2013-12-03 Nvidia Corporation Shared readable and writeable global values in a graphics processor unit pipeline
US8736624B1 (en) 2007-08-15 2014-05-27 Nvidia Corporation Conditional execution flag in graphics applications
US9183607B1 (en) 2007-08-15 2015-11-10 Nvidia Corporation Scoreboard cache coherence in a graphics pipeline
US20090046105A1 (en) * 2007-08-15 2009-02-19 Bergland Tyson J Conditional execute bit in a graphics processor unit pipeline
US8314803B2 (en) * 2007-08-15 2012-11-20 Nvidia Corporation Buffering deserialized pixel data in a graphics processor unit pipeline
US8775777B2 (en) * 2007-08-15 2014-07-08 Nvidia Corporation Techniques for sourcing immediate values from a VLIW
US8249391B2 (en) * 2007-08-24 2012-08-21 Ancestry.com Operations, Inc. User interface method for skew correction
US8156467B2 (en) 2007-08-27 2012-04-10 Adobe Systems Incorporated Reusing components in a running application
KR100933366B1 (ko) * 2007-09-13 2009-12-22 한국전자통신연구원 블랙박스 기능을 가지는 라우터 장치와 그 장치를 포함하는네트워크 시스템
JP4501983B2 (ja) * 2007-09-28 2010-07-14 アイシン・エィ・ダブリュ株式会社 駐車支援システム、駐車支援方法、駐車支援プログラム
US8176466B2 (en) 2007-10-01 2012-05-08 Adobe Systems Incorporated System and method for generating an application fragment
US8724483B2 (en) 2007-10-22 2014-05-13 Nvidia Corporation Loopback configuration for bi-directional interfaces
KR101407639B1 (ko) * 2007-10-22 2014-06-16 삼성전자주식회사 3차원 그래픽 렌더링 장치 및 방법
US8638341B2 (en) * 2007-10-23 2014-01-28 Qualcomm Incorporated Antialiasing of two-dimensional vector images
US8760450B2 (en) * 2007-10-30 2014-06-24 Advanced Micro Devices, Inc. Real-time mesh simplification using the graphics processing unit
US7765500B2 (en) * 2007-11-08 2010-07-27 Nvidia Corporation Automated generation of theoretical performance analysis based upon workload and design configuration
US8063903B2 (en) * 2007-11-09 2011-11-22 Nvidia Corporation Edge evaluation techniques for graphics hardware
US8035641B1 (en) 2007-11-28 2011-10-11 Adobe Systems Incorporated Fast depth of field simulation
US9153211B1 (en) * 2007-12-03 2015-10-06 Nvidia Corporation Method and system for tracking accesses to virtual addresses in graphics contexts
US8026912B1 (en) * 2007-12-04 2011-09-27 Nvidia Corporation System and method for structuring an A-buffer
US8040349B1 (en) 2007-12-04 2011-10-18 Nvidia Corporation System and method for structuring an A-buffer
US7940280B2 (en) * 2007-12-06 2011-05-10 Seiko Epson Corporation System and method for color format conversion in a graphics environment
US8102393B1 (en) 2007-12-13 2012-01-24 Nvidia Corporation Cull streams for fine-grained rendering predication
US8179394B1 (en) 2007-12-13 2012-05-15 Nvidia Corporation Cull streams for fine-grained rendering predication
US9489767B1 (en) * 2007-12-13 2016-11-08 Nvidia Corporation Cull streams for fine-grained rendering predication
US8878849B2 (en) * 2007-12-14 2014-11-04 Nvidia Corporation Horizon split ambient occlusion
US9064333B2 (en) 2007-12-17 2015-06-23 Nvidia Corporation Interrupt handling techniques in the rasterizer of a GPU
US8780123B2 (en) 2007-12-17 2014-07-15 Nvidia Corporation Interrupt handling techniques in the rasterizer of a GPU
CN101216944B (zh) * 2008-01-07 2011-08-03 北大方正集团有限公司 在排版过程中实现渐变底纹的方法及装置
US20090184972A1 (en) * 2008-01-18 2009-07-23 Qualcomm Incorporated Multi-buffer support for off-screen surfaces in a graphics processing system
US9214007B2 (en) * 2008-01-25 2015-12-15 Via Technologies, Inc. Graphics processor having unified cache system
US20090189896A1 (en) * 2008-01-25 2009-07-30 Via Technologies, Inc. Graphics Processor having Unified Shader Unit
US20110149340A1 (en) * 2008-01-30 2011-06-23 Ramot At Tel-Aviv University Ltd. Method, system and computer program product for manipulating a graphic entity
GB0801812D0 (en) * 2008-01-31 2008-03-05 Arm Noway As Methods of and apparatus for processing computer graphics
US9619304B2 (en) 2008-02-05 2017-04-11 Adobe Systems Incorporated Automatic connections between application components
US8098251B2 (en) * 2008-02-22 2012-01-17 Qualcomm Incorporated System and method for instruction latency reduction in graphics processing
KR100866573B1 (ko) * 2008-02-22 2008-11-03 인하대학교 산학협력단 가시성 맵을 이용한 점-기반 렌더링 방법
KR100914171B1 (ko) 2008-02-28 2009-08-28 한국전자통신연구원 휴대 방송에서의 3차원 서비스를 위한 깊이 영상 기반렌더링 장치 및 방법
US7675513B2 (en) * 2008-03-14 2010-03-09 Evans & Sutherland Computer Corp. System and method for displaying stereo images
GB2458488C (en) * 2008-03-19 2018-09-12 Imagination Tech Ltd Untransformed display lists in a tile based rendering system
US7984317B2 (en) * 2008-03-24 2011-07-19 Apple Inc. Hardware-based power management of functional blocks
US8125494B2 (en) * 2008-04-03 2012-02-28 American Panel Corporation Method for mapping optical properties for a display device
US8448002B2 (en) * 2008-04-10 2013-05-21 Nvidia Corporation Clock-gated series-coupled data processing modules
US8681861B2 (en) 2008-05-01 2014-03-25 Nvidia Corporation Multistandard hardware video encoder
US8923385B2 (en) 2008-05-01 2014-12-30 Nvidia Corporation Rewind-enabled hardware encoder
US8358317B2 (en) 2008-05-23 2013-01-22 Evans & Sutherland Computer Corporation System and method for displaying a planar image on a curved surface
KR101427408B1 (ko) * 2008-05-30 2014-08-07 어드밴스드 마이크로 디바이시즈, 인코포레이티드 스케일링가능하고 통합된 컴퓨팅 시스템
GB0810205D0 (en) * 2008-06-04 2008-07-09 Advanced Risc Mach Ltd Graphics processing systems
US8702248B1 (en) 2008-06-11 2014-04-22 Evans & Sutherland Computer Corporation Projection method for reducing interpixel gaps on a viewing surface
US8656293B1 (en) 2008-07-29 2014-02-18 Adobe Systems Incorporated Configuring mobile devices
US8427497B1 (en) 2008-08-01 2013-04-23 Marvell International Ltd. Methods and apparatuses for processing cached image data
US8553041B1 (en) 2008-09-10 2013-10-08 Nvidia Corporation System and method for structuring an A-buffer to support multi-sample anti-aliasing
US8654135B1 (en) * 2008-09-10 2014-02-18 Nvidia Corporation A-Buffer compression for different compression formats
US8130223B1 (en) 2008-09-10 2012-03-06 Nvidia Corporation System and method for structuring an A-buffer to support multi-sample anti-aliasing
US8370759B2 (en) 2008-09-29 2013-02-05 Ancestry.com Operations Inc Visualizing, creating and editing blending modes methods and systems
US9336624B2 (en) * 2008-10-07 2016-05-10 Mitsubishi Electric Research Laboratories, Inc. Method and system for rendering 3D distance fields
KR101496340B1 (ko) 2008-10-31 2015-03-04 삼성전자주식회사 프로세서 및 메모리 제어 방법
US8077378B1 (en) 2008-11-12 2011-12-13 Evans & Sutherland Computer Corporation Calibration system and method for light modulation device
US8355022B2 (en) * 2008-11-25 2013-01-15 Sony Computer Entertainment America Llc Method and apparatus for aggregating light sources per-vertex in computer graphics
WO2010062790A1 (en) * 2008-11-25 2010-06-03 Sony Computer Entertainment America Inc. Computer graphics method for aggregating light sources per-vertex and interpolating color and direction as one entity
US20100128038A1 (en) * 2008-11-25 2010-05-27 Sony Computer Entertainment America Inc. Method and apparatus for interpolating color and direction as one entity in computer graphics
CA2745421A1 (en) * 2008-12-01 2010-06-10 Life Image Inc. Medical imaging viewer
KR101511273B1 (ko) * 2008-12-29 2015-04-10 삼성전자주식회사 멀티 코어 프로세서를 이용한 3차원 그래픽 렌더링 방법 및시스템
GB0900700D0 (en) 2009-01-15 2009-03-04 Advanced Risc Mach Ltd Methods of and apparatus for processing graphics
EP2384585A4 (en) * 2009-02-01 2017-03-15 LG Electronics Inc. Broadcast receiver and 3d video data processing method
US8384740B1 (en) 2009-02-24 2013-02-26 A9.Com, Inc. Method and system for virtually placing a tangible item on an appendage
US8854379B2 (en) * 2009-02-25 2014-10-07 Empire Technology Development Llc Routing across multicore networks using real world or modeled data
US8095560B2 (en) * 2009-02-26 2012-01-10 Yahoo! Inc. Edge attribute aggregation in a directed graph
US20100241638A1 (en) * 2009-03-18 2010-09-23 O'sullivan Patrick Joseph Sorting contacts
US8330767B2 (en) * 2009-03-24 2012-12-11 Advanced Micro Devices, Inc. Method and apparatus for angular invariant texture level of detail generation
CN101859330B (zh) * 2009-04-09 2012-11-21 辉达公司 验证集成电路效能模型的方法
KR100927128B1 (ko) * 2009-04-30 2009-11-18 주식회사 넥서스칩스 타일 더티 테이블을 이용한 3d 그래픽 처리 장치 및 처리 방법
JP5304443B2 (ja) * 2009-05-28 2013-10-02 富士通セミコンダクター株式会社 描画データ処理方法、図形描画システム、及び図形描画データ作成プログラム
US8294714B1 (en) * 2009-06-26 2012-10-23 Nvidia Corporation Accelerated rendering with temporally interleaved details
KR101649098B1 (ko) * 2009-06-30 2016-08-19 삼성전자주식회사 휴대용 단말기에서 센서를 이용한 렌더링 방법 및 장치
US7973705B2 (en) * 2009-07-17 2011-07-05 Garmin Switzerland Gmbh Marine bump map display
US9142057B2 (en) * 2009-09-03 2015-09-22 Advanced Micro Devices, Inc. Processing unit with a plurality of shader engines
US9300969B2 (en) 2009-09-09 2016-03-29 Apple Inc. Video storage
GB2473513B (en) * 2009-09-14 2012-02-01 Sony Comp Entertainment Europe A method and apparatus for determining processor performance
US20110063309A1 (en) * 2009-09-16 2011-03-17 Nvidia Corporation User interface for co-processing techniques on heterogeneous graphics processing units
US8692829B2 (en) * 2009-10-05 2014-04-08 Nvidia Corporation Calculation of plane equations after determination of Z-buffer visibility
US9438861B2 (en) * 2009-10-06 2016-09-06 Microsoft Technology Licensing, Llc Integrating continuous and sparse streaming data
US9058672B2 (en) * 2009-10-06 2015-06-16 Nvidia Corporation Using a pixel offset for evaluating a plane equation
CN102087752B (zh) * 2009-12-08 2013-11-20 鸿富锦精密工业(深圳)有限公司 光照环境模拟系统及方法
RU2581714C2 (ru) * 2009-12-08 2016-04-20 Конинклейке Филипс Электроникс Н.В. Планирование абляционного лечения и устройство
US9530189B2 (en) 2009-12-31 2016-12-27 Nvidia Corporation Alternate reduction ratios and threshold mechanisms for framebuffer compression
TWI482998B (zh) * 2010-01-11 2015-05-01 Hon Hai Prec Ind Co Ltd 光照環境類比系統及方法
JP5571977B2 (ja) * 2010-03-01 2014-08-13 キヤノン株式会社 画像処理装置
US9331869B2 (en) 2010-03-04 2016-05-03 Nvidia Corporation Input/output request packet handling techniques by a device specific kernel mode driver
US9058685B2 (en) * 2010-03-11 2015-06-16 Broadcom Corporation Method and system for controlling a 3D processor using a control list in memory
US8320622B2 (en) * 2010-03-29 2012-11-27 Sharp Laboratories Of America, Inc. Color gradient object tracking
US10786736B2 (en) 2010-05-11 2020-09-29 Sony Interactive Entertainment LLC Placement of user information in a game space
US20110285718A1 (en) 2010-05-21 2011-11-24 Kilgard Mark J Point containment for quadratic bèzier strokes
KR101016075B1 (ko) * 2010-06-04 2011-02-17 김시용 러버 교체형 와이퍼 블레이드
US8593466B2 (en) * 2010-06-08 2013-11-26 Intel Corporation Tile rendering for image processing
US9053562B1 (en) 2010-06-24 2015-06-09 Gregory S. Rabin Two dimensional to three dimensional moving image converter
US10109103B2 (en) 2010-06-30 2018-10-23 Barry L. Jenkins Method of determining occluded ingress and egress routes using nav-cell to nav-cell visibility pre-computation
US8493404B2 (en) 2010-08-24 2013-07-23 Qualcomm Incorporated Pixel rendering on display
KR101064178B1 (ko) * 2010-08-24 2011-09-14 한국과학기술원 버퍼 캐시 관리 시스템 및 방법
CN111833424A (zh) * 2010-09-13 2020-10-27 巴里·林恩·詹金斯 传输和控制包括渲染的几何、纹理和光照数据的流交互媒体
KR101719485B1 (ko) 2010-09-20 2017-03-27 삼성전자주식회사 그래픽 처리 유닛에서의 사전 픽셀 제거를 위한 장치 및 방법
US8811699B2 (en) * 2010-09-22 2014-08-19 Siemens Aktiengesellschaft Detection of landmarks and key-frames in cardiac perfusion MRI using a joint spatial-temporal context model
US9171350B2 (en) 2010-10-28 2015-10-27 Nvidia Corporation Adaptive resolution DGPU rendering to provide constant framerate with free IGPU scale up
US9395885B1 (en) 2010-12-10 2016-07-19 Wyse Technology L.L.C. Methods and systems for a remote desktop session utilizing HTTP header
US9245047B2 (en) 2010-12-10 2016-01-26 Wyse Technology L.L.C. Methods and systems for facilitating a remote desktop session utilizing a remote desktop client common interface
US9535560B1 (en) 2010-12-10 2017-01-03 Wyse Technology L.L.C. Methods and systems for facilitating a remote desktop session for a web browser and a remote desktop server
US9244912B1 (en) 2010-12-10 2016-01-26 Wyse Technology L.L.C. Methods and systems for facilitating a remote desktop redrawing session utilizing HTML
US9430036B1 (en) * 2010-12-10 2016-08-30 Wyse Technology L.L.C. Methods and systems for facilitating accessing and controlling a remote desktop of a remote machine in real time by a windows web browser utilizing HTTP
US8949726B2 (en) 2010-12-10 2015-02-03 Wyse Technology L.L.C. Methods and systems for conducting a remote desktop session via HTML that supports a 2D canvas and dynamic drawing
KR20120065589A (ko) * 2010-12-13 2012-06-21 삼성전자주식회사 저전력을 위한 타일 비닝 장치 및 방법
US9477597B2 (en) 2011-03-25 2016-10-25 Nvidia Corporation Techniques for different memory depths on different partitions
US8422770B2 (en) * 2011-03-30 2013-04-16 Mckesson Financial Holdings Method, apparatus and computer program product for displaying normalized medical images
US8701057B2 (en) 2011-04-11 2014-04-15 Nvidia Corporation Design, layout, and manufacturing techniques for multivariant integrated circuits
CN102739998B (zh) * 2011-05-11 2017-03-01 新奥特(北京)视频技术有限公司 一种三维空间中空间变换的实现方法
GB2491156B (en) * 2011-05-25 2019-08-07 Advanced Risc Mach Ltd Processing pipeline control
AU2011202508B2 (en) 2011-05-27 2013-05-16 Canon Kabushiki Kaisha Method, apparatus and system for rendering an object on a page
US9311433B2 (en) * 2011-05-27 2016-04-12 Airbus Operations S.L. Systems and methods for improving the execution of computational algorithms
US9342817B2 (en) 2011-07-07 2016-05-17 Sony Interactive Entertainment LLC Auto-creating groups for sharing photos
US9652560B1 (en) 2011-07-18 2017-05-16 Apple Inc. Non-blocking memory management unit
US9529712B2 (en) 2011-07-26 2016-12-27 Nvidia Corporation Techniques for balancing accesses to memory having different memory types
US9342322B2 (en) 2011-09-12 2016-05-17 Microsoft Technology Licensing, Llc System and method for layering using tile-based renderers
US9641826B1 (en) 2011-10-06 2017-05-02 Evans & Sutherland Computer Corporation System and method for displaying distant 3-D stereo on a dome surface
US20130106887A1 (en) * 2011-10-31 2013-05-02 Christopher Tremblay Texture generation using a transformation matrix
CN103108197A (zh) 2011-11-14 2013-05-15 辉达公司 一种用于3d视频无线显示的优先级压缩方法和系统
US9633458B2 (en) * 2012-01-23 2017-04-25 Nvidia Corporation Method and system for reducing a polygon bounding box
US9829715B2 (en) 2012-01-23 2017-11-28 Nvidia Corporation Eyewear device for transmitting signal and communication method thereof
US9087409B2 (en) 2012-03-01 2015-07-21 Qualcomm Incorporated Techniques for reducing memory access bandwidth in a graphics processing system based on destination alpha values
US20130235154A1 (en) * 2012-03-09 2013-09-12 Guy Salton-Morgenstern Method and apparatus to minimize computations in real time photo realistic rendering
US8959494B2 (en) * 2012-03-20 2015-02-17 Massively Parallel Technologies Inc. Parallelism from functional decomposition
US9411595B2 (en) 2012-05-31 2016-08-09 Nvidia Corporation Multi-threaded transactional memory coherence
US9148699B2 (en) * 2012-06-01 2015-09-29 Texas Instruments Incorporated Optimized algorithm for construction of composite video from a set of discrete video sources
US9251555B2 (en) 2012-06-08 2016-02-02 2236008 Ontario, Inc. Tiled viewport composition
JP2014006674A (ja) * 2012-06-22 2014-01-16 Canon Inc 画像処理装置及びその制御方法、プログラム
US20140010479A1 (en) * 2012-07-09 2014-01-09 Samsung Electro-Mechanics Co., Ltd. Bilinear interpolation circuit for image and method thereof
US9105250B2 (en) * 2012-08-03 2015-08-11 Nvidia Corporation Coverage compaction
US9323315B2 (en) 2012-08-15 2016-04-26 Nvidia Corporation Method and system for automatic clock-gating of a clock grid at a clock source
US8928929B2 (en) * 2012-08-29 2015-01-06 Eastman Kodak Company System for generating tag layouts
US8786889B2 (en) * 2012-08-29 2014-07-22 Eastman Kodak Company Method for computing scale for tag insertion
US9578224B2 (en) 2012-09-10 2017-02-21 Nvidia Corporation System and method for enhanced monoimaging
US8850371B2 (en) 2012-09-14 2014-09-30 Nvidia Corporation Enhanced clock gating in retimed modules
US9002125B2 (en) 2012-10-15 2015-04-07 Nvidia Corporation Z-plane compression with z-plane predictors
US8941676B2 (en) * 2012-10-26 2015-01-27 Nvidia Corporation On-chip anti-alias resolve in a cache tiling architecture
US9317948B2 (en) 2012-11-16 2016-04-19 Arm Limited Method of and apparatus for processing graphics
GB201223089D0 (en) 2012-12-20 2013-02-06 Imagination Tech Ltd Hidden culling in tile based computer generated graphics
US9082212B2 (en) * 2012-12-21 2015-07-14 Nvidia Corporation Programmable blending via multiple pixel shader dispatches
US9824009B2 (en) 2012-12-21 2017-11-21 Nvidia Corporation Information coherency maintenance systems and methods
US10102142B2 (en) 2012-12-26 2018-10-16 Nvidia Corporation Virtual address based memory reordering
US9251554B2 (en) * 2012-12-26 2016-02-02 Analog Devices, Inc. Block-based signal processing
US9317251B2 (en) 2012-12-31 2016-04-19 Nvidia Corporation Efficient correction of normalizer shift amount errors in fused multiply add operations
US9607407B2 (en) 2012-12-31 2017-03-28 Nvidia Corporation Variable-width differential memory compression
US9591309B2 (en) 2012-12-31 2017-03-07 Nvidia Corporation Progressive lossy memory compression
DE102013201377A1 (de) * 2013-01-29 2014-07-31 Bayerische Motoren Werke Aktiengesellschaft Verfahren und Vorrichtung zum Verarbeiten von 3d-Bilddaten
US20140225902A1 (en) * 2013-02-11 2014-08-14 Nvidia Corporation Image pyramid processor and method of multi-resolution image processing
KR101529942B1 (ko) * 2013-02-18 2015-06-18 서경대학교 산학협력단 병렬 처리 래스터라이저 및 병렬 처리를 이용한 래스터라이징 방법
GB2511817A (en) * 2013-03-14 2014-09-17 Imagination Tech Ltd Rendering in computer graphics systems
WO2014152800A1 (en) 2013-03-14 2014-09-25 Massively Parallel Technologies, Inc. Project planning and debugging from functional decomposition
US9992021B1 (en) 2013-03-14 2018-06-05 GoTenna, Inc. System and method for private and point-to-point communication between computing devices
US10169906B2 (en) 2013-03-29 2019-01-01 Advanced Micro Devices, Inc. Hybrid render with deferred primitive batch binning
US10957094B2 (en) 2013-03-29 2021-03-23 Advanced Micro Devices, Inc. Hybrid render with preferred primitive batch binning and sorting
GB2506706B (en) 2013-04-02 2014-09-03 Imagination Tech Ltd Tile-based graphics
US10008029B2 (en) 2013-05-31 2018-06-26 Nvidia Corporation Updating depth related graphics data
US10204391B2 (en) 2013-06-04 2019-02-12 Arm Limited Method of and apparatus for processing graphics
US9710894B2 (en) 2013-06-04 2017-07-18 Nvidia Corporation System and method for enhanced multi-sample anti-aliasing
KR20140142863A (ko) * 2013-06-05 2014-12-15 한국전자통신연구원 그래픽 편집기 제공 장치 및 그 방법
KR101451966B1 (ko) * 2013-06-17 2014-10-22 (주)가비아 모바일용 영상 렌더링 제공 시스템 및 방법
US9418400B2 (en) 2013-06-18 2016-08-16 Nvidia Corporation Method and system for rendering simulated depth-of-field visual effect
US9177413B2 (en) * 2013-06-26 2015-11-03 Nvidia Corporation Unique primitive identifier generation
US9607574B2 (en) 2013-08-09 2017-03-28 Apple Inc. Video data compression format
US9569385B2 (en) 2013-09-09 2017-02-14 Nvidia Corporation Memory transaction ordering
US9230362B2 (en) 2013-09-11 2016-01-05 Nvidia Corporation System, method, and computer program product for using compression with programmable sample locations
US9230363B2 (en) 2013-09-11 2016-01-05 Nvidia Corporation System, method, and computer program product for using compression with programmable sample locations
US9437040B2 (en) 2013-11-15 2016-09-06 Nvidia Corporation System, method, and computer program product for implementing anti-aliasing operations using a programmable sample pattern table
US10935788B2 (en) 2014-01-24 2021-03-02 Nvidia Corporation Hybrid virtual 3D rendering approach to stereovision
US9276610B2 (en) * 2014-01-27 2016-03-01 Tensorcom, Inc. Method and apparatus of a fully-pipelined layered LDPC decoder
US20150228106A1 (en) * 2014-02-13 2015-08-13 Vixs Systems Inc. Low latency video texture mapping via tight integration of codec engine with 3d graphics engine
US9710957B2 (en) * 2014-04-05 2017-07-18 Sony Interactive Entertainment America Llc Graphics processing enhancement by tracking object and/or primitive identifiers
CN105100862B (zh) * 2014-04-18 2018-04-24 阿里巴巴集团控股有限公司 网格移动的显示处理方法及其系统
GB2526598B (en) * 2014-05-29 2018-11-28 Imagination Tech Ltd Allocation of primitives to primitive blocks
US9547918B2 (en) * 2014-05-30 2017-01-17 Intel Corporation Techniques for deferred decoupled shading
GB2524120B (en) * 2014-06-17 2016-03-02 Imagination Tech Ltd Assigning primitives to tiles in a graphics processing system
GB2524121B (en) * 2014-06-17 2016-03-02 Imagination Tech Ltd Assigning primitives to tiles in a graphics processing system
US9307249B2 (en) * 2014-06-20 2016-04-05 Freescale Semiconductor, Inc. Processing device and method of compressing images
US9721376B2 (en) * 2014-06-27 2017-08-01 Samsung Electronics Co., Ltd. Elimination of minimal use threads via quad merging
CN104217461B (zh) * 2014-07-10 2017-05-10 无锡梵天信息技术股份有限公司 一种基于深度图模拟实时凹凸效果的视差映射方法
US9832388B2 (en) 2014-08-04 2017-11-28 Nvidia Corporation Deinterleaving interleaved high dynamic range image by using YUV interpolation
US9569862B2 (en) * 2014-08-15 2017-02-14 Qualcomm Incorporated Bandwidth reduction using texture lookup by adaptive shading
US9665370B2 (en) * 2014-08-19 2017-05-30 Qualcomm Incorporated Skipping of data storage
US10019834B2 (en) 2014-09-26 2018-07-10 Microsoft Technology Licensing, Llc Real-time rendering of volumetric models with occlusive and emissive particles
KR102281180B1 (ko) 2014-11-21 2021-07-23 삼성전자주식회사 영상 처리 장치 및 방법
US9720769B2 (en) * 2014-12-03 2017-08-01 Sandisk Technologies Llc Storage parameters for a data storage device
US10249079B2 (en) * 2014-12-11 2019-04-02 Intel Corporation Relaxed sorting in a position-only pipeline
US9916326B2 (en) 2015-01-27 2018-03-13 Splunk, Inc. Efficient point-in-polygon indexing technique for facilitating geofencing operations
US9836874B2 (en) * 2015-01-27 2017-12-05 Splunk Inc. Efficient polygon-clipping technique to reduce data transfer requirements for a viewport
US10026204B2 (en) 2015-01-27 2018-07-17 Splunk Inc. Efficient point-in-polygon indexing technique for processing queries over geographic data sets
US9607414B2 (en) 2015-01-27 2017-03-28 Splunk Inc. Three-dimensional point-in-polygon operation to facilitate displaying three-dimensional structures
US9530237B2 (en) * 2015-04-02 2016-12-27 Apple Inc. Interpolation circuitry and techniques for graphics processing
US10255651B2 (en) 2015-04-15 2019-04-09 Channel One Holdings Inc. Methods and systems for generating shaders to emulate a fixed-function graphics pipeline
US9922449B2 (en) 2015-06-01 2018-03-20 Intel Corporation Apparatus and method for dynamic polygon or primitive sorting for improved culling
US9959665B2 (en) 2015-07-21 2018-05-01 Qualcomm Incorporated Zero pixel culling for graphics processing
KR20170034727A (ko) 2015-09-21 2017-03-29 삼성전자주식회사 그림자 정보 저장 방법 및 장치, 3d 렌더링 방법 및 장치
US10269154B2 (en) * 2015-12-21 2019-04-23 Intel Corporation Rasterization based on partial spans
KR102521654B1 (ko) * 2016-01-25 2023-04-13 삼성전자주식회사 컴퓨팅 시스템 및 컴퓨팅 시스템에서 타일-기반 렌더링의 그래픽스 파이프라인을 수행하는 방법
US9818051B2 (en) * 2016-01-29 2017-11-14 Ricoh Company, Ltd. Rotation and clipping mechanism
US9906981B2 (en) 2016-02-25 2018-02-27 Nvidia Corporation Method and system for dynamic regulation and control of Wi-Fi scans
CN107180441B (zh) * 2016-03-10 2019-04-09 腾讯科技(深圳)有限公司 生成眼睛图像的方法和装置
US11847040B2 (en) 2016-03-16 2023-12-19 Asg Technologies Group, Inc. Systems and methods for detecting data alteration from source to target
KR101821124B1 (ko) 2016-04-05 2018-01-23 한화테크윈 주식회사 웹브라우저 상에서 미디어 스트림을 재생하는 방법 및 장치
US10412130B2 (en) 2016-04-04 2019-09-10 Hanwha Techwin Co., Ltd. Method and apparatus for playing media stream on web browser
US9798672B1 (en) 2016-04-14 2017-10-24 Macom Connectivity Solutions, Llc Data managment for cache memory
GB2553744B (en) 2016-04-29 2018-09-05 Advanced Risc Mach Ltd Graphics processing systems
EP3249612B1 (en) * 2016-04-29 2023-02-08 Imagination Technologies Limited Generation of a control stream for a tile
CN109643460B (zh) * 2016-08-29 2023-08-15 超威半导体公司 使用推迟图元批量合并和分类的混合渲染器
US10756785B2 (en) * 2016-09-29 2020-08-25 Nokia Technologies Oy Flexible reference signal design
US10417134B2 (en) * 2016-11-10 2019-09-17 Oracle International Corporation Cache memory architecture and policies for accelerating graph algorithms
US10282889B2 (en) * 2016-11-29 2019-05-07 Samsung Electronics Co., Ltd. Vertex attribute compression and decompression in hardware
KR20180070314A (ko) 2016-12-16 2018-06-26 삼성전자주식회사 그래픽스 처리 장치 및 그래픽스 처리 장치에서 그래픽스 파이프라인을 처리하는 방법
KR102637736B1 (ko) * 2017-01-04 2024-02-19 삼성전자주식회사 그래픽스 처리 방법 및 시스템
US10977858B2 (en) 2017-03-30 2021-04-13 Magic Leap, Inc. Centralized rendering
KR20240036150A (ko) 2017-03-30 2024-03-19 매직 립, 인코포레이티드 중앙화된 렌더링
US10157493B2 (en) * 2017-04-01 2018-12-18 Intel Corporation Adaptive multisampling based on vertex attributes
GB2562041B (en) * 2017-04-28 2020-11-25 Imagination Tech Ltd Multi-output decoder for texture decompression
US10521877B2 (en) 2017-05-23 2019-12-31 Samsung Electronics Co., Ltd Apparatus and method for speculative buffer reservations with cancellation mechanism
US10969740B2 (en) 2017-06-27 2021-04-06 Nvidia Corporation System and method for near-eye light field rendering for wide field of view interactive three-dimensional computer graphics
US10510181B2 (en) * 2017-06-27 2019-12-17 Samsung Electronics Co., Ltd. System and method for cache management using a cache status table
CN107463398B (zh) * 2017-07-21 2018-08-17 腾讯科技(深圳)有限公司 游戏渲染方法、装置、存储设备及终端
GB2569775B (en) * 2017-10-20 2020-02-26 Graphcore Ltd Synchronization in a multi-tile, multi-chip processing arrangement
GB2569271B (en) 2017-10-20 2020-05-13 Graphcore Ltd Synchronization with a host processor
GB2569844B (en) 2017-10-20 2021-01-06 Graphcore Ltd Sending data off-chip
US10600142B2 (en) * 2017-11-02 2020-03-24 Advanced Micro Devices, Inc. Compression and decompression of indices in a graphics pipeline
US11057500B2 (en) * 2017-11-20 2021-07-06 Asg Technologies Group, Inc. Publication of applications using server-side virtual screen change capture
US10699374B2 (en) 2017-12-05 2020-06-30 Microsoft Technology Licensing, Llc Lens contribution-based virtual reality display rendering
GB2569546B (en) * 2017-12-19 2020-10-14 Sony Interactive Entertainment Inc Determining pixel values using reference images
US10877740B2 (en) 2017-12-29 2020-12-29 Asg Technologies Group, Inc. Dynamically deploying a component in an application
US11611633B2 (en) 2017-12-29 2023-03-21 Asg Technologies Group, Inc. Systems and methods for platform-independent application publishing to a front-end interface
US10812611B2 (en) 2017-12-29 2020-10-20 Asg Technologies Group, Inc. Platform-independent application publishing to a personalized front-end interface by encapsulating published content into a container
GB2572617B (en) 2018-04-05 2021-06-16 Imagination Tech Ltd Blending hardware
US10672182B2 (en) * 2018-04-19 2020-06-02 Microsoft Technology Licensing, Llc Compact visibility state for GPUs compatible with hardware instancing
JP7119081B2 (ja) 2018-05-24 2022-08-16 株式会社Preferred Networks 投影データ生成装置、3次元モデル、投影データ生成方法、ニューラルネットワーク生成方法及びプログラム
GB2575294B8 (en) 2018-07-04 2022-07-20 Graphcore Ltd Host Proxy On Gateway
US10861230B2 (en) * 2018-08-01 2020-12-08 Nvidia Corporation System-generated stable barycentric coordinates and direct plane equation access
MX2021002931A (es) * 2018-09-13 2021-07-16 Fraunhofer Ges Forschung Intrapredicciones ponderadas lineales afines.
US11138747B1 (en) * 2018-11-02 2021-10-05 Facebook Technologies, Llc Interpolation optimizations for a display engine for post-rendering processing
GB2579412B (en) 2018-11-30 2020-12-23 Graphcore Ltd Gateway pull model
US10909659B2 (en) 2018-12-12 2021-02-02 Apical Limited Super-resolution image processing using a machine learning system
US11715262B2 (en) * 2018-12-17 2023-08-01 Advanced Micro Devices, Inc. Optimizing primitive shaders
KR102216749B1 (ko) * 2019-03-05 2021-02-17 네이버웹툰 유한회사 타겟 이미지의 채색 완성 방법, 장치 및 컴퓨터 프로그램
US10866280B2 (en) * 2019-04-01 2020-12-15 Texas Instruments Incorporated Scan chain self-testing of lockstep cores on reset
US11640649B2 (en) * 2019-06-19 2023-05-02 Samsung Electronics Co., Ltd. Methods and apparatus for efficient range calculation
US11488349B2 (en) 2019-06-28 2022-11-01 Ati Technologies Ulc Method and apparatus for alpha blending images from different color formats
US11762634B2 (en) 2019-06-28 2023-09-19 Asg Technologies Group, Inc. Systems and methods for seamlessly integrating multiple products by using a common visual modeler
US10981059B2 (en) * 2019-07-03 2021-04-20 Sony Interactive Entertainment LLC Asset aware computing architecture for graphics processing
EP4004766A4 (en) 2019-07-30 2023-09-20 Falkonry, Inc. SMOOTH AND RESOLUTION-FRIENDLY REPRESENTATION OF LARGE AMOUNTS OF TIME SERIES DATA
US11886397B2 (en) 2019-10-18 2024-01-30 Asg Technologies Group, Inc. Multi-faceted trust system
US11941137B2 (en) 2019-10-18 2024-03-26 Asg Technologies Group, Inc. Use of multi-faceted trust scores for decision making, action triggering, and data analysis and interpretation
US11055067B2 (en) 2019-10-18 2021-07-06 Asg Technologies Group, Inc. Unified digital automation platform
US11755760B2 (en) 2019-10-18 2023-09-12 Asg Technologies Group, Inc. Systems and methods for secure policies-based information governance
US11269660B2 (en) 2019-10-18 2022-03-08 Asg Technologies Group, Inc. Methods and systems for integrated development environment editor support with a single code base
US11216993B2 (en) * 2019-11-27 2022-01-04 Arm Limited Graphics processing systems
US11210847B2 (en) 2019-11-27 2021-12-28 Arm Limited Graphics processing systems
US11210821B2 (en) * 2019-11-27 2021-12-28 Arm Limited Graphics processing systems
US11170555B2 (en) 2019-11-27 2021-11-09 Arm Limited Graphics processing systems
US11514549B2 (en) * 2020-02-03 2022-11-29 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by generating information in one rendering phase for use in another rendering phase
US11508110B2 (en) 2020-02-03 2022-11-22 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by performing geometry analysis before rendering
US11113858B2 (en) * 2020-02-04 2021-09-07 Inventive Software, LLC System and method for deep compositing of images in web browsers
US11321259B2 (en) * 2020-02-14 2022-05-03 Sony Interactive Entertainment Inc. Network architecture providing high speed storage access through a PCI express fabric between a compute node and a storage server
US11132831B1 (en) 2020-03-02 2021-09-28 Qualcomm Incorporated Methods and apparatus for efficient multi-view rasterization
US11243882B2 (en) * 2020-04-15 2022-02-08 International Business Machines Corporation In-array linked list identifier pool scheme
US11250627B2 (en) * 2020-06-29 2022-02-15 Intel Corporation Tile sequencing mechanism
US11277658B1 (en) 2020-08-21 2022-03-15 Beam, Inc. Integrating overlaid digital content into displayed data via graphics processing circuitry
EP4229534A1 (en) 2020-10-13 2023-08-23 ASG Technologies Group, Inc. DBA ASG Technologies Geolocation-based policy rules
CN116670723A (zh) * 2020-10-22 2023-08-29 彩滋公司 用于定制产品的合成视图的高质量渲染的系统和方法
US11232628B1 (en) * 2020-11-10 2022-01-25 Weta Digital Limited Method for processing image data to provide for soft shadow effects using shadow depth information
US11481933B1 (en) 2021-04-08 2022-10-25 Mobeus Industries, Inc. Determining a change in position of displayed digital content in subsequent frames via graphics processing circuitry
US11483156B1 (en) 2021-04-30 2022-10-25 Mobeus Industries, Inc. Integrating digital content into displayed data on an application layer via processing circuitry of a server
US11601276B2 (en) 2021-04-30 2023-03-07 Mobeus Industries, Inc. Integrating and detecting visual data security token in displayed data via graphics processing circuitry using a frame buffer
US11475610B1 (en) 2021-04-30 2022-10-18 Mobeus Industries, Inc. Controlling interactivity of digital content overlaid onto displayed data via graphics processing circuitry using a frame buffer
US11682101B2 (en) 2021-04-30 2023-06-20 Mobeus Industries, Inc. Overlaying displayed digital content transmitted over a communication network via graphics processing circuitry using a frame buffer
US11586835B2 (en) 2021-04-30 2023-02-21 Mobeus Industries, Inc. Integrating overlaid textual digital content into displayed data via graphics processing circuitry using a frame buffer
US11477020B1 (en) 2021-04-30 2022-10-18 Mobeus Industries, Inc. Generating a secure random number by determining a change in parameters of digital content in subsequent frames via graphics processing circuitry
CN113256485B (zh) * 2021-05-21 2024-01-30 百果园技术(新加坡)有限公司 图像拉伸方法、装置、电子设备和存储介质
US20220410002A1 (en) * 2021-06-29 2022-12-29 Bidstack Group PLC Mesh processing for viewability testing
US11562153B1 (en) 2021-07-16 2023-01-24 Mobeus Industries, Inc. Systems and methods for recognizability of objects in a multi-layer display
US20230334728A1 (en) * 2022-04-15 2023-10-19 Meta Platforms Technologies, Llc Destination Update for Blending Modes in a Graphics Pipeline
US11882295B2 (en) 2022-04-15 2024-01-23 Meta Platforms Technologies, Llc Low-power high throughput hardware decoder with random block access
US20230334736A1 (en) * 2022-04-15 2023-10-19 Meta Platforms Technologies, Llc Rasterization Optimization for Analytic Anti-Aliasing
CN114529705B (zh) * 2022-04-22 2022-07-19 山东捷瑞数字科技股份有限公司 一种三维引擎编辑器的界面布局处理方法

Family Cites Families (132)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2353185A1 (fr) 1976-04-09 1977-12-23 Thomson Csf Dispositif correlateur rapide, et systeme de traitement des signaux d'un recepteur comportant un tel dispositif
FR2481489A1 (fr) 1980-04-25 1981-10-30 Thomson Csf Dispositif correlateur bidimensionnel
US4484346A (en) 1980-08-15 1984-11-20 Sternberg Stanley R Neighborhood transformation logic circuitry for an image analyzer system
US4559618A (en) 1982-09-13 1985-12-17 Data General Corp. Content-addressable memory module with associative clear
US4783829A (en) 1983-02-23 1988-11-08 Hitachi, Ltd. Pattern recognition apparatus
US4581760A (en) 1983-04-27 1986-04-08 Fingermatrix, Inc. Fingerprint verification method
US4670858A (en) 1983-06-07 1987-06-02 Tektronix, Inc. High storage capacity associative memory
US4594673A (en) 1983-06-28 1986-06-10 Gti Corporation Hidden surface processor
US4532606A (en) 1983-07-14 1985-07-30 Burroughs Corporation Content addressable memory cell with shift capability
US4564952A (en) 1983-12-08 1986-01-14 At&T Bell Laboratories Compensation of filter symbol interference by adaptive estimation of received symbol sequences
US4694404A (en) 1984-01-12 1987-09-15 Key Bank N.A. High-speed image generation of complex solid objects using octree encoding
US4794559A (en) 1984-07-05 1988-12-27 American Telephone And Telegraph Company, At&T Bell Laboratories Content addressable semiconductor memory arrays
US4622653A (en) 1984-10-29 1986-11-11 Texas Instruments Incorporated Block associative memory
US4669054A (en) 1985-05-03 1987-05-26 General Dynamics, Pomona Division Device and method for optically correlating a pair of images
SE445154B (sv) 1985-07-08 1986-06-02 Ibm Svenska Ab Metod for att avlegsna dolda linjer
US4695973A (en) 1985-10-22 1987-09-22 The United States Of America As Represented By The Secretary Of The Air Force Real-time programmable optical correlator
US4758982A (en) 1986-01-08 1988-07-19 Advanced Micro Devices, Inc. Quasi content addressable memory
US4890242A (en) 1986-06-05 1989-12-26 Xox Corporation Solid-modeling system using topology directed subdivision for determination of surface intersections
US5067162A (en) 1986-06-30 1991-11-19 Identix Incorporated Method and apparatus for verifying identity using image correlation
US4998286A (en) 1987-02-13 1991-03-05 Olympus Optical Co., Ltd. Correlation operational apparatus for multi-dimensional images
US4825391A (en) 1987-07-20 1989-04-25 General Electric Company Depth buffer priority processing for real time computer image generating systems
US5146592A (en) 1987-09-14 1992-09-08 Visual Information Technologies, Inc. High speed image processing computer with overlapping windows-div
US5129060A (en) 1987-09-14 1992-07-07 Visual Information Technologies, Inc. High speed image processing computer
US4841467A (en) 1987-10-05 1989-06-20 General Electric Company Architecture to implement floating point multiply/accumulate operations
GB2215623B (en) 1987-10-23 1991-07-31 Rotation Limited Apparatus for playing a game for one or more players and to games played with the apparatus
US4888712A (en) 1987-11-04 1989-12-19 Schlumberger Systems, Inc. Guardband clipping method and apparatus for 3-D graphics display system
US4945500A (en) 1987-11-04 1990-07-31 Schlumberger Technologies, Inc. Triangle processor for 3-D graphics display system
FR2625345A1 (fr) 1987-12-24 1989-06-30 Thomson Cgr Procede de visualisation en trois dimensions d'objets codes numeriquement sous forme arborescente et dispositif de mise en oeuvre
DE68918724T2 (de) 1988-02-17 1995-05-24 Nippon Denso Co Fingerabdruck-Prüfungsverfahren mit Verwendung mehrerer Korrelierungsentscheidungspegel und aufeinanderfolgenden Entscheidungsstufen.
US4888583A (en) 1988-03-14 1989-12-19 Ligocki Terry J Method and apparatus for rendering an image from data arranged in a constructive solid geometry format
GB2223384B (en) 1988-07-14 1992-05-06 Daikin Ind Ltd Method and apparatus for applying shadowing operation to figures to be drawn for displaying on crt-display
US5133052A (en) 1988-08-04 1992-07-21 Xerox Corporation Interactive graphical search and replace utility for computer-resident synthetic graphic image editors
US4996666A (en) 1988-08-12 1991-02-26 Duluk Jr Jerome F Content-addressable memory system capable of fully parallel magnitude comparisons
GB8828342D0 (en) 1988-12-05 1989-01-05 Rediffusion Simulation Ltd Image generator
US4970636A (en) 1989-01-23 1990-11-13 Honeywell Inc. Memory interface controller
FR2646046B1 (fr) 1989-04-18 1995-08-25 France Etat Procede et dispositif de compression de donnees d'image par transformation mathematique a cout reduit de mise en oeuvre, notamment pour la transmission a debit reduit de sequences d'images
JPH0776991B2 (ja) 1989-10-24 1995-08-16 インターナショナル・ビジネス・マシーンズ・コーポレーション Nurbsデータ変換方法及び装置
US5245700A (en) 1989-11-21 1993-09-14 International Business Machines Corporation Adjustment of z-buffer values for lines on the surface of a polygon
JPH03166601A (ja) 1989-11-27 1991-07-18 Hitachi Ltd 制御支援装置
US5129051A (en) 1990-03-16 1992-07-07 Hewlett-Packard Company Decomposition of arbitrary polygons into trapezoids
US5123085A (en) 1990-03-19 1992-06-16 Sun Microsystems, Inc. Method and apparatus for rendering anti-aliased polygons
US5128888A (en) 1990-04-02 1992-07-07 Advanced Micro Devices, Inc. Arithmetic unit having multiple accumulators
GB9009127D0 (en) 1990-04-24 1990-06-20 Rediffusion Simulation Ltd Image generator
US5369734A (en) 1990-05-18 1994-11-29 Kabushiki Kaisha Toshiba Method for processing and displaying hidden-line graphic images
DE69122557T2 (de) 1990-06-29 1997-04-24 Philips Electronics Nv Bilderzeugung
JPH0475183A (ja) 1990-07-17 1992-03-10 Mitsubishi Electric Corp 画像の相関度検出装置
US5054090A (en) 1990-07-20 1991-10-01 Knight Arnold W Fingerprint correlation system with parallel FIFO processor
US5050220A (en) 1990-07-24 1991-09-17 The United States Of America As Represented By The Secretary Of The Navy Optical fingerprint correlator
JPH07120435B2 (ja) 1990-12-06 1995-12-20 インターナショナル・ビジネス・マシーンズ・コーポレイション 高速zバッファの初期化および更新方法ならびにそのシステム
FR2670923A1 (fr) 1990-12-21 1992-06-26 Philips Lab Electronique Dispositif de correlation.
JPH07122908B2 (ja) 1991-03-12 1995-12-25 インターナショナル・ビジネス・マシーンズ・コーポレイション 3次元のソリッド物体を表す表示可能情報を生成する装置と方法
US5289567A (en) 1991-04-01 1994-02-22 Digital Equipment Corporation Computer apparatus and method for finite element identification in interactive modeling
US5293467A (en) 1991-04-03 1994-03-08 Buchner Gregory C Method for resolving priority between a calligraphically-displayed point feature and both raster-displayed faces and other calligraphically-displayed point features in a CIG system
US5315537A (en) 1991-04-08 1994-05-24 Blacker Teddy D Automated quadrilateral surface discretization method and apparatus usable to generate mesh in a finite element analysis system
US5347619A (en) 1991-04-30 1994-09-13 International Business Machines Corporation Nonconvex polygon identifier
US5263136A (en) 1991-04-30 1993-11-16 Optigraphics Corporation System for managing tiled images using multiple resolutions
US5299139A (en) 1991-06-21 1994-03-29 Cadence Design Systems, Inc. Short locator method
US5493644A (en) 1991-07-11 1996-02-20 Hewlett-Packard Company Polygon span interpolator with main memory Z buffer
US5295235A (en) 1992-02-14 1994-03-15 Steve Newman Polygon engine for updating computer graphic display employing compressed bit map data
US5319743A (en) 1992-04-02 1994-06-07 Digital Equipment Corporation Intelligent and compact bucketing method for region queries in two-dimensional space
US5669010A (en) 1992-05-18 1997-09-16 Silicon Engines Cascaded two-stage computational SIMD engine having multi-port memory and multiple arithmetic units
WO1993023816A1 (en) 1992-05-18 1993-11-25 Silicon Engines Inc. System and method for cross correlation with application to video motion vector estimation
US5621866A (en) 1992-07-24 1997-04-15 Fujitsu Limited Image processing apparatus having improved frame buffer with Z buffer and SAM port
US5455900A (en) 1992-10-20 1995-10-03 Ricoh Company, Ltd. Image processing apparatus
US5388206A (en) 1992-11-13 1995-02-07 The University Of North Carolina Architecture and apparatus for image generation
TW241196B (ja) 1993-01-15 1995-02-21 Du Pont
JP3240447B2 (ja) 1993-02-19 2001-12-17 株式会社リコー 画像処理装置
US5574835A (en) 1993-04-06 1996-11-12 Silicon Engines, Inc. Bounding box and projections detection of hidden polygons in three-dimensional spatial databases
US5509110A (en) 1993-04-26 1996-04-16 Loral Aerospace Corporation Method for tree-structured hierarchical occlusion in image generators
US6167143A (en) * 1993-05-03 2000-12-26 U.S. Philips Corporation Monitoring system
US5684939A (en) 1993-07-09 1997-11-04 Silicon Graphics, Inc. Antialiased imaging with improved pixel supersampling
US5579455A (en) 1993-07-30 1996-11-26 Apple Computer, Inc. Rendering of 3D scenes on a display using hierarchical z-buffer visibility
GB9316214D0 (en) * 1993-08-05 1993-09-22 Philips Electronics Uk Ltd Image processing
JPH07182537A (ja) 1993-12-21 1995-07-21 Toshiba Corp 図形描画装置および図形描画方法
US5699497A (en) 1994-02-17 1997-12-16 Evans & Sutherland Computer Corporation Rendering global macro texture, for producing a dynamic image, as on computer generated terrain, seen from a moving viewpoint
US5778245A (en) 1994-03-01 1998-07-07 Intel Corporation Method and apparatus for dynamic allocation of multiple buffers in a processor
US5623628A (en) 1994-03-02 1997-04-22 Intel Corporation Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue
US5546194A (en) * 1994-03-23 1996-08-13 Videofaxx, Inc. Method and apparatus for converting a video image format to a group III fax format
US5596686A (en) * 1994-04-21 1997-01-21 Silicon Engines, Inc. Method and apparatus for simultaneous parallel query graphics rendering Z-coordinate buffer
US5544306A (en) 1994-05-03 1996-08-06 Sun Microsystems, Inc. Flexible dram access in a frame buffer memory and system
JPH0855239A (ja) * 1994-07-21 1996-02-27 Internatl Business Mach Corp <Ibm> グラフィカル・オブジェクトの可視性を判定するための方法および装置
US5572634A (en) 1994-10-26 1996-11-05 Silicon Engines, Inc. Method and apparatus for spatial simulation acceleration
JPH08127167A (ja) * 1994-11-01 1996-05-21 Arutetsuku Kk ロール紙終端検知装置及び方法
US5594854A (en) 1995-03-24 1997-01-14 3Dlabs Inc. Ltd. Graphics subsystem with coarse subpixel correction
US5798770A (en) 1995-03-24 1998-08-25 3Dlabs Inc. Ltd. Graphics rendering system with reconfigurable pipeline sequence
US5710876A (en) 1995-05-25 1998-01-20 Silicon Graphics, Inc. Computer graphics system for rendering images using full spectral illumination data
JPH08329276A (ja) 1995-06-01 1996-12-13 Ricoh Co Ltd 3次元グラフィックス処理装置
AU6600496A (en) * 1995-07-26 1997-02-26 Raycer, Incorporated Method and apparatus for span sorting rendering system
US5841447A (en) 1995-08-02 1998-11-24 Evans & Sutherland Computer Corporation System and method for improving pixel update performance
US5949428A (en) 1995-08-04 1999-09-07 Microsoft Corporation Method and apparatus for resolving pixel data in a graphics rendering system
US5990904A (en) 1995-08-04 1999-11-23 Microsoft Corporation Method and system for merging pixel fragments in a graphics rendering system
JP4540753B2 (ja) * 1995-08-04 2010-09-08 マイクロソフト コーポレーション グラフィックオブジェクトを画像チャンクにレンダリングして、画像層を表示画像に組み合わせる方法及びシステム
US5977977A (en) 1995-08-04 1999-11-02 Microsoft Corporation Method and system for multi-pass rendering
US5864342A (en) 1995-08-04 1999-01-26 Microsoft Corporation Method and system for rendering graphical objects to image chunks
US5767859A (en) 1995-09-28 1998-06-16 Hewlett-Packard Company Method and apparatus for clipping non-planar polygons
US5854631A (en) * 1995-11-22 1998-12-29 Silicon Graphics, Inc. System and method for merging pixel fragments based on depth range values
JP2882465B2 (ja) * 1995-12-25 1999-04-12 日本電気株式会社 画像生成方法およびその装置
US5574836A (en) 1996-01-22 1996-11-12 Broemmelsiek; Raymond M. Interactive display apparatus and method with viewer position compensation
US5850225A (en) 1996-01-24 1998-12-15 Evans & Sutherland Computer Corp. Image mapping system and process using panel shear transforms
US6046746A (en) * 1996-07-01 2000-04-04 Sun Microsystems, Inc. Method and apparatus implementing high resolution rendition of Z-buffered primitives
US5751291A (en) * 1996-07-26 1998-05-12 Hewlett-Packard Company System and method for accelerated occlusion culling
US5767589A (en) 1996-09-03 1998-06-16 Maximum Products Inc. Lighting control circuit for vehicle brake light/tail light/indicator light assembly
US5860158A (en) 1996-11-15 1999-01-12 Samsung Electronics Company, Ltd. Cache control unit with a cache request transaction-oriented protocol
US6167486A (en) 1996-11-18 2000-12-26 Nec Electronics, Inc. Parallel access virtual channel memory system with cacheable channels
US5936629A (en) 1996-11-20 1999-08-10 International Business Machines Corporation Accelerated single source 3D lighting mechanism
US6111582A (en) * 1996-12-20 2000-08-29 Jenkins; Barry L. System and method of image generation and encoding using primitive reprojection
US6697063B1 (en) * 1997-01-03 2004-02-24 Nvidia U.S. Investment Company Rendering pipeline
US5852451A (en) 1997-01-09 1998-12-22 S3 Incorporation Pixel reordering for improved texture mapping
US5880736A (en) 1997-02-28 1999-03-09 Silicon Graphics, Inc. Method system and computer program product for shading
US5949424A (en) * 1997-02-28 1999-09-07 Silicon Graphics, Inc. Method, system, and computer program product for bump mapping in tangent space
US6259452B1 (en) 1997-04-14 2001-07-10 Massachusetts Institute Of Technology Image drawing system and method with real-time occlusion culling
US6084591A (en) * 1997-04-29 2000-07-04 Ati Technologies, Inc. Method and apparatus for deferred video rendering
US6002412A (en) 1997-05-30 1999-12-14 Hewlett-Packard Co. Increased performance of graphics memory using page sorting fifos
US5889997A (en) 1997-05-30 1999-03-30 Hewlett-Packard Company Assembler system and method for a geometry accelerator
US5920326A (en) 1997-05-30 1999-07-06 Hewlett Packard Company Caching and coherency control of multiple geometry accelerators in a computer graphics system
US6118452A (en) 1997-08-05 2000-09-12 Hewlett-Packard Company Fragment visibility pretest system and methodology for improved performance of a graphics system
US6002410A (en) 1997-08-25 1999-12-14 Chromatic Research, Inc. Reconfigurable texture cache
US6128000A (en) 1997-10-15 2000-10-03 Compaq Computer Corporation Full-scene antialiasing using improved supersampling techniques
US6204859B1 (en) 1997-10-15 2001-03-20 Digital Equipment Corporation Method and apparatus for compositing colors of images with memory constraints for storing pixel data
JPH11161819A (ja) * 1997-11-27 1999-06-18 Sega Enterp Ltd 画像処理装置、画像処理方法、及び画像処理プログラムを記録した記録媒体
US6201540B1 (en) * 1998-01-07 2001-03-13 Microsoft Corporation Graphical interface components for in-dash automotive accessories
US6259460B1 (en) 1998-03-26 2001-07-10 Silicon Graphics, Inc. Method for efficient handling of texture cache misses by recirculation
US6246415B1 (en) 1998-04-30 2001-06-12 Silicon Graphics, Inc. Method and apparatus for culling polygons
US6243744B1 (en) * 1998-05-26 2001-06-05 Compaq Computer Corporation Computer network cluster generation indicator
US6650327B1 (en) * 1998-06-16 2003-11-18 Silicon Graphics, Inc. Display system having floating point rasterization and floating point framebuffering
US6216004B1 (en) * 1998-06-23 2001-04-10 Qualcomm Incorporated Cellular communication system with common channel soft handoff and associated method
US6263493B1 (en) * 1998-07-08 2001-07-17 International Business Machines Corporation Method and system for controlling the generation of program statements
WO2000011607A1 (en) * 1998-08-20 2000-03-02 Apple Computer, Inc. Deferred shading graphics pipeline processor
US6771264B1 (en) * 1998-08-20 2004-08-03 Apple Computer, Inc. Method and apparatus for performing tangent space lighting and bump mapping in a deferred shading graphics processor
US6577317B1 (en) * 1998-08-20 2003-06-10 Apple Computer, Inc. Apparatus and method for geometry operations in a 3D-graphics pipeline
US6275235B1 (en) * 1998-12-21 2001-08-14 Silicon Graphics, Inc. High precision texture wrapping method and device
US6228730B1 (en) * 1999-04-28 2001-05-08 United Microelectronics Corp. Method of fabricating field effect transistor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0019377A1 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8106904B2 (en) 2002-03-20 2012-01-31 Nvidia Corporation Shader program generation system and method
US10332290B2 (en) * 2016-03-21 2019-06-25 Adobe Inc. Fast, coverage-optimized, resolution-independent and anti-aliased graphics processing

Also Published As

Publication number Publication date
JP3657519B2 (ja) 2005-06-08
AU5779799A (en) 2000-06-05
WO2000011613A3 (en) 2000-06-29
WO2000011605A3 (en) 2000-06-22
JP2002526842A (ja) 2002-08-20
US6597363B1 (en) 2003-07-22
WO2000011614A2 (en) 2000-03-02
WO2000030040A9 (en) 2001-10-18
US6614444B1 (en) 2003-09-02
AU5782599A (en) 2000-03-14
JP3657518B2 (ja) 2005-06-08
AU5687599A (en) 2000-03-14
US20040130552A1 (en) 2004-07-08
JP2003515798A (ja) 2003-05-07
US6771264B1 (en) 2004-08-03
WO2000011613A2 (en) 2000-03-02
EP1138023A4 (en) 2005-09-07
AU5687899A (en) 2000-04-17
WO2000011605B1 (en) 2001-04-12
KR100478767B1 (ko) 2005-03-24
WO2000019377A1 (en) 2000-04-06
WO2000011613A9 (en) 2000-08-03
WO2000011614B1 (en) 2000-07-27
WO2000030040A1 (en) 2000-05-25
WO2000011604A3 (en) 2000-06-02
AU5576599A (en) 2000-03-14
KR20010085424A (ko) 2001-09-07
WO2000019377B1 (en) 2000-06-08
KR20010085426A (ko) 2001-09-07
AU5690499A (en) 2000-03-14
US6717576B1 (en) 2004-04-06
US7167181B2 (en) 2007-01-23
JP2004272928A (ja) 2004-09-30
WO2000011604B1 (en) 2000-07-20
WO2000011605A2 (en) 2000-03-02
EP1138023A1 (en) 2001-10-04
JP4516350B2 (ja) 2010-08-04
WO2000011605A9 (en) 2001-06-21
KR100485241B1 (ko) 2005-04-27
WO2000011614A3 (en) 2000-06-15
WO2000011604A2 (en) 2000-03-02

Similar Documents

Publication Publication Date Title
US6597363B1 (en) Graphics processor with deferred shading
US6268875B1 (en) Deferred shading graphics pipeline processor
US6577317B1 (en) Apparatus and method for geometry operations in a 3D-graphics pipeline
US5949428A (en) Method and apparatus for resolving pixel data in a graphics rendering system
US5990904A (en) Method and system for merging pixel fragments in a graphics rendering system
US5870097A (en) Method and system for improving shadowing in a graphics rendering system
US5977977A (en) Method and system for multi-pass rendering
US5886701A (en) Graphics rendering device and method for operating same
US6326964B1 (en) Method for sorting 3D object geometry among image chunks for rendering in a layered graphics rendering system
EP1434171A2 (en) Method and system for texture mapping a source image to a destination image

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20010319

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

AX Request for extension of the european patent

Free format text: AL;LT;LV;MK;RO;SI

RIN1 Information on inventor provided before grant (corrected)

Inventor name: FANG, EMERSON, S.

Inventor name: DODGEN, STEVEN, L.

Inventor name: CUAN, GEORGE

Inventor name: BRATT, JOSEPH, P.

Inventor name: BENKUAL, JACK

Inventor name: ARNOLD, VAUGHN, T.

Inventor name: HESSEL, RICHARD, E.

Inventor name: DULUK, JEROME, F., JR.

RIN1 Information on inventor provided before grant (corrected)

Inventor name: FANG, EMERSON, S.

Inventor name: DODGEN, STEVEN, L.

Inventor name: CUAN, GEORGE

Inventor name: BRATT, JOSEPH, P.

Inventor name: BENKUAL, JACK

Inventor name: ARNOLD, VAUGHN, T.

Inventor name: HESSEL, RICHARD, E.

Inventor name: DULUK, JEROME, F., JR.

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20030901