EP0977386A1 - Empfänger für den empfang von digitalen signalen - Google Patents

Empfänger für den empfang von digitalen signalen Download PDF

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Publication number
EP0977386A1
EP0977386A1 EP98905792A EP98905792A EP0977386A1 EP 0977386 A1 EP0977386 A1 EP 0977386A1 EP 98905792 A EP98905792 A EP 98905792A EP 98905792 A EP98905792 A EP 98905792A EP 0977386 A1 EP0977386 A1 EP 0977386A1
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EP
European Patent Office
Prior art keywords
data
multiplex signal
signal
multiplex
receiving
Prior art date
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Withdrawn
Application number
EP98905792A
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English (en)
French (fr)
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EP0977386A4 (de
Inventor
Hironori Mitoh
Masahiro Sata
Hiroyuki Tachibana
Morihiko Sumino
Takeharu Matsui
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Publication of EP0977386A1 publication Critical patent/EP0977386A1/de
Publication of EP0977386A4 publication Critical patent/EP0977386A4/de
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H40/00—Arrangements specially adapted for receiving broadcast information
    • H04H40/18—Arrangements characterised by circuits or components specially adapted for receiving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H20/00—Arrangements for broadcast or for distribution combined with broadcast
    • H04H20/16—Arrangements for broadcast or for distribution of identical information repeatedly
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H20/00—Arrangements for broadcast or for distribution combined with broadcast
    • H04H20/28—Arrangements for simultaneous broadcast of plural pieces of information

Definitions

  • the present invention relates to a digital signal receiving device which can receive programs over a plurality of networks in a multiplex broadcast system, and in particular an FM multiplex signal receiving device which receives the program data transmitted by FM multiplex broadcast system.
  • FM multiplex broadcast has been developed toward practical utilization as one kind of broadcast providing new service.
  • digital signals are multiplexed in a blank spectrum region of base band signals in FM stereo broadcast.
  • FM multiplex broadcast has already started in some fields as means for sending traffic jam information and others in real time to automobiles or the like carrying receivers, or as means providing inexpensive transmission paths over which users having handy-size receivers can access necessary information at any time and any place.
  • the phasing jam causes extreme voltage drop, resulting in a critical error which cannot be corrected in some cases.
  • the unit data length of data to be transmitted is determined to match with the average burst length of the error caused by phasing.
  • the data can be complemented by replacing the above unit data with the retransmitted unit data when uncorrectable error occurs.
  • the data has a two-dimensional frame structure which includes error correction codes in both the longitudinal and lateral directions.
  • the transmission data has a data structure having a hierarchical structure in which data of the above one frame forms a basic unit.
  • Fig. 12 shows specifications of a hierarchical structure of data.
  • transmission path properties are specified.
  • L+R signals and L-R signals which are usual FM stereo broadcast signals, multiplex signals are superimposed on the side of a higher frequency than the L-R signals.
  • LMSK Level controlled Minimum Shift Keying
  • the layer 2 specifies the frame structure of data including the error correction method.
  • Each frame is formed of 272 blocks in the column direction, and a BIC (Block Identification Code) of 16 bits are added to the front end. Frame synchronization and block synchronization are performed based on the BIC.
  • 190 blocks form a packet transmitting data
  • 82 blocks form a parity packet transmitting parities in the column direction.
  • Each packet is formed of an information portion of 176 bits in the row direction, a CRC (Cyclic Redundancy Code) of 14 bits forming an error detection code and a parity portion of 82 bits forming an error correction code.
  • CRC Cyclic Redundancy Code
  • the transmission data is first subjected to the error correction in this layer handling the one frame as a basic unit.
  • a layer 3 specifies the structure of the data packet.
  • the data packet is formed of 176 bits in each row of the frame other than BIC, CRC and the parities.
  • this data packet is formed of a prefix and a data block.
  • the prefix contains information for identifying contents of the data, and specifies, e.g., the program contents, to which the data packet in question belongs, as will be described later.
  • a layer 4 specifies a structure of a data group.
  • the data block is formed of one or more data blocks. Based on the information in the prefix of the data packet, the data blocks are arranged in the order of the data packet numbers starting from "0" to that of the data block carrying "ON information end flag in its prefix.
  • This data group likewise includes CRC, i.e., the error correction code, and error detection is likewise effected on the transmission data in this layer.
  • One data group corresponds to data of one display unit, i.e., one page.
  • a layer 5 specifies one grouped form or unit of information data transmitted by the FM multiplex broadcast, and thus specifies the structure of the program data.
  • Fig. 13 shows a structure of the program data.
  • the program of characters and graphic information is formed of a plurality of data groups.
  • the data group in the front end serves as program management data, and is formed of coded information relating, e.g., to a program number and a total number of pages, and thus relating to the whole of the program.
  • the program management data is followed by a plurality of page data, each of which is coded for each page.
  • the program data forms a group of data, in which the program data represents one grouped form of consistent information on the receiver side.
  • the program information presents a situation of traffic jam or the like in each junction on a specific route (e.g., a speedway).
  • a specific route e.g., a speedway.
  • weather forecast it represents weather forecast information or the like in a specific region.
  • Fig. 14 is a schematic block diagram showing a structure of an FM multiplex broadcast receiving device 10 in the prior art.
  • FM multiplex broadcast signals received via an antenna 12 and a tuner 14 are detected by a detector circuit 16, and are sent through a band-path filter 18 to an LMSK demodulation circuit 20.
  • LMSK demodulation circuit 20 performs data demodulation on LMSK-modulated FM multiplex broadcast signals to take out FM multiplex signals.
  • the demodulated data signals are processed in a synchronous reproducing circuit 22, which performs frame synchronization and block synchronization based on BIC, as already described in connection with layer 2 shown in Fig. 12.
  • the data signals thus synchronized are processed by an error correction circuit 24 performing error correction based on the parity code and CRC.
  • error correction circuit 24 issues packet data of the FM multiplex broadcast, which is correctly received, is subjected to error correction and has the structure shown in the layer 3 in Fig. 12.
  • a central processing unit 40 which will be referred to as a "CPU” hereinafter, processes the supplied packet data by performing extraction of data blocks, reconfiguration of data groups, error correction in the data group stage and reconfiguration into program data, and thereafter issues the program data to a display device 42.
  • Display device 42 displays the supplied program data as graphics or characters.
  • Display device 42 employs a liquid crystal screen or the like having a display region for one page, i.e., 248 x 60 dots (corresponding to 15.5 characters x 2.5 lines of Japanese letters).
  • FM multiplex broadcast receiving device 10 In FM multiplex broadcast receiving device 10 described above, programs transmitted over different networks, i.e., programs sent from different providers can be selectively received by such a structure that CPU 40 controls channel selection by a tuner.
  • channel selection information data for specifying the network selected by CPU 40 is applied to tuner 14 and LMSK demodulation circuit 20.
  • tuner 14 selects the intended network
  • the LMSK demodulation circuit 20 detects the reception of packet data over the selected network.
  • LMSK demodulation circuit 20 returns predetermined data to CPU 40. In this manner, it is possible to achieve a synchronous operation for notifying the start of data reception over the selected network. In other words, synchronous operation by so-called handshaking can be performed between CPU 40, and tuner 14 and LMSK demodulation circuit 20.
  • the FM multiplex broadcast receiving device may have a structure other than the integrated structure shown in Fig. 14, and more specifically may have a structure, in which circuits performing FM demodulation, LMSK demodulation and extraction of packet data (including synchronous reproduction and error correction of packet data) are integrated in a so-called PC card (PCMCIA card: Personal Computer Memory Card International Association card) and are connected to a host personal computer (which will be referred to as a "host PC” hereinafter) via an appropriate interface.
  • PC card PCMCIA card: Personal Computer Memory Card International Association card
  • character/graphic information transmitted by the FM multiplex broadcast can be displayed without restrictions on the display screen size in contrast to the FM multiplex broadcast receiving device of an integrated type.
  • Fig. 15 is a schematic block diagram showing a structure of an FM multiplex broadcast receiving device 80 having the above structure, in which a PC card is connected to a host PC via an interface.
  • Fig. 15 depicts tuner 14 and detector circuit 16 in Fig. 14 as one block of an FM demodulation circuit 17, and LMSK demodulation circuit 20 and error correction circuit 24 are depicted as one block of LMSK demodulation integrated circuit 25.
  • FM multiplex broadcast signals which are received by antenna 12 and are demodulated by FM demodulation circuit 17 are applied to LMSK demodulation integrated circuit 25 through band-path filter 18.
  • LMSK demodulation integrated circuit 25 performs data demodulation on the FM multiplex broadcast signals which were LMSK-modulated, and the frame synchronization and block synchronization are effected on the extracted FM multiplex signals based on BIC as already described in connection with the layer 2 in Fig. 12. Thereafter, the error correction is performed based on the parity code and CRC.
  • LMSK demodulation integrated circuit 25 issues the packet data (having the structure shown in layer 3 in Fig. 12) of the FM multiplex broadcast, which are normally received and are already subjected to the error correction.
  • An interface portion 30 receives the packet data from LMSK demodulation integrated circuit 25, and issues the same to an interface portion 38 on the host PC side.
  • a central processing unit (CPU) of the host PC processes the received packet data by performing extraction of data blocks, reconfiguration of data groups, error correction in the data group stage and reconfiguration to the program data, and thereafter issues the program data to a display device (not shown).
  • a display device not shown
  • the CPU and a memory transmitting data to and from the CPU are depicted as one block 45.
  • the display device may be provided by the display device of the host PC such as a liquid crystal flat panel display, whereby the display region in the above structure can have a resolution of 640 x 400 dots or more.
  • positions of delimiters in the program data cannot be determined when switching and receiving the program data over a plurality of networks.
  • various kinds of information supplied by FM multiplex broadcast over different networks aim at different kinds of services, respectively.
  • the structure additionally suffers from the following problem.
  • the above different kinds of services are, for example, so-called visible radio for transmitting news information as character information, traffic information (which will be referred to as VICS (Vehicle Information Communication System) information) and others.
  • a plurality of receiver systems may be mounted, as is done in a double tuner structure shown in Fig. 16.
  • a plurality of systems each formed of a simple receiving system are employed, a plurality of systems are likewise required for data transfer to the host PC.
  • a plurality of addresses must be allocated in the interface portion on the host PC side, and a plurality of interrupts are asynchronously performed on the host PC. This complicates data reception software on the host PC side, and increases loads on hardware.
  • the foregoing structure including the PC card and the host PC connected together via the interface may be used in such a field that prime importance is placed on acquisition of information over a plurality of networks rather than real-time output of information.
  • such a structure may be employed that is provided with only one receiving system, and can successively scan a plurality of networks.
  • this structure suffers from a problem that a delimiter of information cannot be detected on the host PC side when the networks are switched.
  • the above structure may employ such a specific structure that scans a plurality of networks in accordance with timing specified by a user. In this case, however, appropriate timing for scanning must be selected on the system side in order to prevent deterioration of the data acquisition efficiency.
  • Another object of the invention is to provide a digital signal receiving device, which can be used in an operation of asynchronously receiving and reconfiguring packet data received by switching a plurality of networks in a multiplex broadcast, and particularly can employ a receiver portion and a data reconfiguring portion having simplified structures and allowing reduction in manufacturing cost.
  • the multiplex signal separating circuit includes a demodulating circuit for receiving and demodulating a carrier wave carrying a multiplex signal corresponding to the selected network in accordance with the control signal; a multiplex signal decoding circuit for receiving the output of the demodulating circuit, extracting the multiplex signal and issuing the extracted multiplex signal as a plurality of packet data formed of the corresponding digital signals; and an interface control circuit for receiving the output of the multiplex signal decoding circuit, and issuing the received output after buffering the same.
  • the multiplex signal separating circuit receives the packet stream, and extracts corresponding digital signals in accordance with an externally supplied control signal for outputting the same.
  • the multiplex signal separating circuit includes a demodulating circuit for receiving and demodulating a carrier wave carrying a multiplex signal corresponding to the selected network in accordance with the control signal; a multiplex signal decoding circuit for receiving the output of the demodulating circuit, extracting the multiplex signal and issuing the extracted multiplex signal as a plurality of packet data formed of the corresponding digital signals; and an interface control circuit for receiving the output of the multiplex signal decoding circuit, and issuing the received output after adding identification data to each packet data in accordance with the attribute data.
  • the information reconfiguring circuit includes a network selection control circuit for performing control to repeat first processing of reconfiguring the cyclic program data for at least the first predetermined time and second processing of selecting another network and reconfiguring the program data of the selected network at intervals of the second predetermined time.
  • the display device outputs the display data.
  • the multiplex signal separating circuit receives the packet stream, and extracts corresponding digital signals in accordance with an externally supplied control signal for outputting the same.
  • the multiplex signal separating circuit includes a demodulating circuit for receiving and demodulating a carrier wave carrying a multiplex signal corresponding to the selected network in accordance with the control signal; a multiplex signal decoding circuit for receiving the output of the demodulating circuit, extracting the multiplex signal and issuing the extracted multiplex signal as a plurality of packet data formed of the corresponding digital signals; and an interface control circuit for receiving the output of the multiplex signal decoding circuit, and issuing the received output after buffering the same.
  • the information reconfiguring circuit applies the control signal to the multiplex signal separating circuit, receiving the output of the interface control circuit and reconfiguring display data corresponding to the program data.
  • the display device outputs the display data.
  • Another advantage of the invention is that, for the operation of asynchronously receiving and reconfiguring packet data received by switching a plurality of networks in a multiplex broadcast, the digital signal receiving device can employ a receiver portion and a data reconfiguring portion which have simplified structures and therefore require a low manufacturing cost.
  • Yet another advantage of the invention is that, in the operation of asynchronously receiving and reconfiguring packet data received by switching a plurality of networks in a multiplex broadcast, the digital signal receiving device can efficiently acquire the data over the plurality of networks.
  • Fig. 1 is a schematic block diagram showing a structure of an FM multiplex broadcast receiving device 100 of a first embodiment of the invention.
  • FM multiplex broadcast receiving device 100 includes an antenna 12 receiving FM radio wave, an FM tuner portion 14 which receives and frequency-demodulates the output of antenna 12, an FM multiplex decoding portion 15 which receives the output of FM tuner portion 14 and outputs corresponding digital signals by extracting FM multiplex signals and correcting errors, and a personal computer 120 which receives the digital signals, forms display unit data (page data) and displays corresponding characteristics and others.
  • FM multiplex broadcast receiving device 100 differs from conventional FM multiplex broadcast receiving device 10 shown in Fig. 14 in the following structures.
  • FM multiplex decoding portion 15 extracts the FM multiplex signals from the signals which are FM-demodulated by FM tuner portion 14, and issues the digital signals as packet data to personal computer 120, which reconfigures the packet data into the program data and displays the same.
  • the FM multiplex broadcast signals received by antenna 12 are synchronously detected in an FM demodulating circuit 2 in FM tuner portion 14 with a local oscillating wave issued from a phase-locked loop circuit 4 (which will be referred to as a "PLL circuit” hereinafter), and are issued to FM multiplex decoding portion 15 through a buffer 6.
  • a phase-locked loop circuit 4 which will be referred to as a "PLL circuit” hereinafter
  • FM multiplex decoding portion 15 receives the FM-demodulated signals through a buffer circuit 8, and a band-path filter 18 takes out signal components in a predetermined frequency region from the received signals. Thereafter, demodulation LSI 20 performs LMSK demodulation to extract the FM multiplex signals.
  • a CPU 26 receives the output of demodulation LSI 20, and issues packet data after performing appropriate processing such as block synchronization of the received data and error correction. If packet data containing an uncorrectable error is present, CPU 26 selects and issues only the data required for display after deleting the data containing the uncorrectable error.
  • a RAM 28 functions as a buffer which receives the output of CPU 26 and issues the data to an interface 30.
  • An address decoder 32 operates to issue the data from interface 30 when it detects that CPU 26 accesses personal computer 120.
  • a controller 34 usually receives data sent from interface 30, and sends the data to personal computer 120. During boot-up of the device or the like, however, controller 34 performs initial setting between the interfaces based on data stored in a ROM 36.
  • Personal computer 120 which is a host PC receives the packet data sent from FM multiplex decoding portion 15 through an interface 38.
  • a CPU 40 receives the output data, i.e., packet data from interface 38, and extracts data blocks from the data packet in accordance with a hierarchical structure shown in Fig. 10. Then, CPU 40 reconfigures the data groups from the extracted data blocks, and performs error correction on the data groups. Further, CPU 40 extracts data heads and data unit groups, which correspond to page data, from the data group data in the data group, and reconfigures the program data.
  • CPU 40 sends a channel select instruction to CPU 26 in FM decoding portion 15 through interfaces 38 and 30 in accordance with data applied from an input portion 46 or data stored in a memory 44 as will be described later.
  • CPU 26 controls FM tuner portion 14 to select the intended network based on this channel select instruction.
  • CPU 40 Based on the program data thus reconfigured, CPU 40 issues corresponding display data to a display portion 42, which outputs corresponding character or graphic information based on the received display data.
  • display portion 42 is formed of a liquid crystal flat panel display or the like, and has a display region of a resolution of 640 x 400 dots or more.
  • Fig. 2 schematically shows a notebook-size personal computer 120 and a PC card, which form FM multiplex broadcast receiving device 100 shown in Fig. 1.
  • FM tuner portion 14 and FM multiplex decoding portion 15 may be integrated for improving portability in contrast to the structure shown in Fig. 2, wherein FM tuner portion 14 and FM multiplex decoding portion 15 are connected via the connection code.
  • Fig. 3 schematically shows an example of the structure of the data group shown in Fig. 12.
  • the data group includes at its leading end a heading start code (SOH) indicating start of the data group, and also includes in the subsequent positions a data group link code, which is a flag indicating existence and absence of coupling between data groups, and a data group size data indicating the number of bytes of the data group data.
  • SOH heading start code
  • the data group data which is a main portion of the data to be transmitted, is present in the position following the above, and is followed by an NULL region for length control, which is performed to set the data group length to an integer multiple of the data block length, an end code indicating the end of the data group, and a CRC code for error correction of the data group.
  • the data group data also contains data indicating whether VICS data is dynamic data or static data, as will be described later.
  • Fig. 4 is a flowchart showing an example of the operation of CPU 40.
  • CPU 40 After start of operation (step S102), CPU 40 performs the channel selection in accordance with an instruction externally applied to input portion 46, and more specifically determines whether switching of the network is instructed or not (step S104).
  • CPU 40 When switching is instructed, CPU 40 resets a variable n, which is used for counting the number of packet data applied from FM multiplex decoding portion 15, to 0 (step S106). Subsequently, CPU 40 determines whether interrupt occurs for data transmission from the FM multiplex decoding portion or not (step S108).
  • step S104 CPU 40 advances the process to step S108 (step S104).
  • step S108 If it is determined that the interrupt for data transfer does not occur in step S108, the process returns to step S104.
  • step S108 If it is determined the interrupt for data transfer occurs (step S108), comparison in magnitude between variable n and a predetermined number N is performed (step S110).
  • step S110 CPU 40 determines that the data supplied after this is packet data sent over the new switched or selected network. Based on this determination, CPU 40 reads in the data, and returns the process to step S104 (S112).
  • n > N is not satisfied, i.e., if reading of the packet data of the predetermined number N is not yet completed (step S110), CPU 40 abandons the data already taken (step S114), and returns the processing to step S104 after incrementing the value of variable n by one (step S116).
  • CPU 40 abandons the packet data of the predetermined number N after instruction of the network switching.
  • CPU 40 does not take in data until a predetermined time elapses after instruction of the network switching.
  • CPU 40 After start of the operation (step S102), CPU 40 performs channel select operation in accordance with the instruction externally applied to the input 46 and, in other words, determines whether switching of the network for signal reception is instructed or not.
  • CPU 40 determines whether the interrupt for data transfer from the FM multiplex decoding portion occurs or not (step S108).
  • CPU 40 advances the processing to step S108 (step S104).
  • step 108 If it is determined that the interrupt for data transfer does not occur in step 108, the processing returns to step S104.
  • step S110 CPU 40 determines that the data taken in thereafter is packet data sent over a new selected network, and thereby CPU 40 reads in the data and returns the processing to step S104 (step S112).
  • step S110 If the time t has not elapsed (step S110), CPU 40 returns the processing to step S104 (step S116).
  • the data taken by CPU 40 is the data sent over the last selected network or the data sent over the new selected network, and reconfiguration of the program data from the packet data is not performed until the packet data of the predetermined number are taken in, or before the predetermined tine elapses. Accordingly, even when the device has received data over the new selected network, the received data is unconditionally abandoned in the practical operation. Conversely, the operation cannot be performed stably unless the predetermined number N and the predetermined time t are determined in view of such wasteful data to be abandoned.
  • a digital signal receiving device of a second embodiment has a structure which is basically similar to that of the digital signal receiving device 100 of the first embodiment, but differs therefrom in operation of CPU 26 of FM multiplex decoding portion 15 in the structure of digital signal receiving device 100 shown in Fig. 1 as described below.
  • CPU 26 When CPU 26 receives the data (i.e., data in layer 3 or 4) from demodulation LSI 20 to be transferred to host PC, CPU 26 adds identification data, from which the channel of the received data can be identified, to the received data. CPU 26 mixes units of data, which are sent from the respective channels and carry the identification data added thereto, in the predetermined order, and transfers the same to the host PC.
  • data i.e., data in layer 3 or 4
  • CPU 26 adds identification data, from which the channel of the received data can be identified, to the received data.
  • CPU 26 mixes units of data, which are sent from the respective channels and carry the identification data added thereto, in the predetermined order, and transfers the same to the host PC.
  • such a structure may be employed that only a flag is set on, and in other words, the value of ID is set to "1" only in the first data sent over a new selected network.
  • data which follow the data bearing the ON flag, and thus carry the flags of "0" are determined as the data after the channel selection.
  • CPU 40 can determine a point in time from which data sent over the new selected network starts after instruction of the network switching.
  • the second embodiment has been discussed in connection with the structure for providing a delimiter between the data sent over the new selected network and the data sent over the last selected network in the operation of switching the network for signal reception.
  • the above structure can improve the scanning efficiency by performing the scanning in accordance with properties such as VICS information.
  • a structure of a digital signal receiving device of the third embodiment is basically similar to that of the digital signal receiving device 100 of the first embodiment in that the delimiter is provided in the data, but differs therefrom in operation of CPU 40 in the structure of the host PC shown in Fig. 1.
  • the digital signal receiving device of the third embodiment may have a structure, which is basically similar to that of digital signal receiving device 100 of the second embodiment in that the above data delimiter is detected, but differs therefrom in the operation of CPU 40 in the structure of the host PC.
  • Fig. 6 is a timing chart showing timing for sending VICS information.
  • the VICS information is renewed every five minutes, but sending of dynamic information (i.e., information changing ceaselessly) such as traffic jam information, which indicates degrees of jamming on respective roads, respectively, is completed within first one minute.
  • the remaining time is used for retransmitting static information such as map information, which does not change over time.
  • the purpose of always retransmitting the static information as described above is to allow reproduction of the whole traffic information on the display device whenever the receiving side starts the signal reception.
  • such a structure can be employed that automatically scans the network of dynamic information at a frequency of 5 minutes (or an integer multiple of 5 minutes) after reception of the dynamic information is once confirmed, and returns the operation to reception from the former or initial channel upon every completion of reception of the dynamic information.
  • Fig. 7 is a flowchart showing the operation of CPU 40 for such scanning.
  • CPU 40 selects an A channel transmitting VICS information (step S204).
  • CPU 40 stands by based on the data in the data group data until start of reception of the dynamic data from the A channel (step S204).
  • CPU 40 resets timer 41 (step S208), and starts the counting operation.
  • CPU 40 Until reception of the next dynamic data, CPU 40 keeps the standby state (step S210).
  • CPU 40 detects reception of the dynamic data again (step S210), it acquires the send timing of the dynamic data, i.e., the frequency of the VICS information (step S212).
  • static data is acquired, utilizing a period from step S206 to step S212.
  • CPU 40 stands by until it externally receives the channel select instruction (step S214).
  • CPU 40 sends an instruction to select, e.g., the A channel (step S216).
  • CPU 40 When CPU 40 detects the start of reception of the dynamic data (step S218), CPU 40 resets timer 41 and starts the counting operation (step S220).
  • CPU 40 When CPU 40 detects complete reception of the dynamic data of the A channel, it instructs selection of a B channel (step S224).
  • CPU 40 receives data from the B channel (step S226), and determines whether the count of the timer reaches the send frequency of VICS information or not (step S228). If the count has not yet reached the send frequency, it continues reception of the data from the B channel (step S226). If the count reaches the send frequency, processing returns to step S216.
  • CPU 40 can selectively acquire the information on the new selected network after instructing switching of the network.
  • the send frequency of the VICS information is acquired by monitoring the same for one period after start of the operation of CPU 40.
  • the send frequency is fixed in advance, another structure may be employed.
  • data of the send frequency is stored in advance in memory 44 of the host PC.
  • CPU 26 in the FM multiplex decoding portion in Fig. 1 additionally performs the operation of CPU 40.
  • the third embodiment has been described in connection with the structure, in which only one signal receiving system can be used for scanning the multiple networks because prime importance is placed on acquisition of information and therefore interruption of sound or the like does not cause a problem.
  • the fourth embodiment will now be described below in connection with a structure of a digital signal receiving device 200 which can be effectively used for the above case.
  • Fig. 8 is a schematic block diagram, which shows the structure of the digital signal receiving device 200 of the fourth embodiment, and is comparable to Fig. 15 showing the structure of the digital signal receiving device 80 in the prior art.
  • the structure of digital signal receiving device 200 differs from the structure of the digital signal receiving device 80 in the following two points.
  • digital signal receiving device 200 includes two FM demodulating circuits 17a and 17b, two filters 18a and 18b, and two LMSK demodulating circuits 25a and 25b.
  • a host PC 120 in Fig. 8 includes block 45, CPU 40, timer 41, display portion 42, memory 44 and input portion 46 similarly to the structure in Fig. 1.
  • CPU 52 responds to activation of one of interrupt signals 1 and 2, which are issued from LMSK demodulating circuit 25a and 25b for indicating completion of the data reception, respectively, and thereby issues internal clock CLK1 or CLK2 to the side which issued the active interrupt signal.
  • the LMSK demodulating circuit which receives internal clock CLK1 or CLK2 issues data DATA1 or DATA2 to CPU 52 in synchronization with the received internal dock CLK1 or CLK2.
  • CPU 52 adds the ID already described with reference to Fig. 5 to the received data, and successively outputs the data to I/F circuit 56.
  • the data which are received over the two networks and carry the ID added thereto, are issued from I/F circuit 56 in a mixed fashion and in a time-sharing manner.
  • Fig. 10 conceptually shows an example of a format of data issued from LMSK demodulating circuits 25a and 25b.
  • Data CNT1 which is a parameter indicating the state of signal reception as well as data CNT2 indicating a block number are present before the data in layer 3 of 22 bytes.
  • Fig. 11 is a flowchart showing an operation of CPU 52 shown in Fig. 9.
  • CPU 52 adds ID to the read data (step S308), and stores the same in RAM 54 (step S310).
  • CPU 52 determines whether interrupt from LMSK demodulating circuit 25b is present or not (step S312). If the interrupt is present, data (of 24 bytes) is read from LMSK demodulating circuit 25b (step S314).
  • CPU 52 adds ID to the read data (step S316), and stores the same in RAM 54 (step S318).
  • CPU 52 advances the processing to step S320.
  • CPU 52 determines whether the data is stored in RAM 54 or not (step S320). If the data is stored, the data is transferred to the host PC (step S322).
  • step S320 If the data is not stored, the processing returns to step S304 (step S320).
  • data can be efficiently acquired from the multiple networks by the simple structure, compared with the structure provided with two complete signal receiving systems as shown in Fig. 16, without interrupting the output of information which is being received over the network. Further, even in the case of asynchronously transmitting the data, CPU 40 can selectively acquire the information over the new selected network after sending an instruction of the network switching.

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Circuits Of Receivers In General (AREA)
  • Time-Division Multiplex Systems (AREA)
EP98905792A 1997-03-07 1998-03-06 Empfänger für den empfang von digitalen signalen Withdrawn EP0977386A4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP5348897 1997-03-07
JP5348897 1997-03-07
PCT/JP1998/000929 WO1998039864A1 (fr) 1997-03-07 1998-03-06 Recepteur numerique de signaux

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EP0977386A1 true EP0977386A1 (de) 2000-02-02
EP0977386A4 EP0977386A4 (de) 2006-06-28

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WO2002019578A2 (de) * 2000-08-29 2002-03-07 Trend Network Ag Verfahren zum vorführen von informationen, die in einem computer gespeichert sind, wobei zusatzinformationen mit einem rundfunksignal auf den computer übertragen werden
WO2003088024A2 (en) * 2002-04-04 2003-10-23 Teradyne Diagnostic Solutions Limited Data conversion device for receiving data from a communication bus of a vehicle
EP1475909A1 (de) 2003-05-08 2004-11-10 Harman/Becker Automotive Systems GmbH Hintergrundtuner eines Rundfunkempfängers zum Empfangen von Verkehrs- und Reise-Information und zum Untersuchen von alternativen Frequenzen

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002019578A2 (de) * 2000-08-29 2002-03-07 Trend Network Ag Verfahren zum vorführen von informationen, die in einem computer gespeichert sind, wobei zusatzinformationen mit einem rundfunksignal auf den computer übertragen werden
WO2002019578A3 (de) * 2000-08-29 2002-08-01 Trend Network Ag Verfahren zum vorführen von informationen, die in einem computer gespeichert sind, wobei zusatzinformationen mit einem rundfunksignal auf den computer übertragen werden
WO2003088024A2 (en) * 2002-04-04 2003-10-23 Teradyne Diagnostic Solutions Limited Data conversion device for receiving data from a communication bus of a vehicle
WO2003088024A3 (en) * 2002-04-04 2003-12-31 Teradyne Diagnostic Solutions Data conversion device for receiving data from a communication bus of a vehicle
EP1475909A1 (de) 2003-05-08 2004-11-10 Harman/Becker Automotive Systems GmbH Hintergrundtuner eines Rundfunkempfängers zum Empfangen von Verkehrs- und Reise-Information und zum Untersuchen von alternativen Frequenzen
US7254378B2 (en) 2003-05-08 2007-08-07 Harman Becker Automotive Systems Gmbh Receiver system for decoding data embedded in an electromagnetic signal

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JP3604703B2 (ja) 2004-12-22
EP0977386A4 (de) 2006-06-28

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