Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66409—Unipolar field-effect transistors
  • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
  • H01L29/66742—Thin film unipolar transistors
  • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/28008—Making conductor-insulator-semiconductor electrodes
  • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
  • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
  • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
  • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L29/41725—Source or drain electrodes for field effect devices
  • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate

Definitions

• the present invention relates to a field effect transistor provided with field isolation and contact points self-aligned with respect to its active region, and to a method for producing such a transistor.
• the invention relates more precisely to the manufacture of this transistor on a silicon-on-insulator type substrate, designated in the following text by SOI (Silicon on Insulator).
• SOI Silicon on Insulator
• the invention finds applications in microelectronics for the manufacture of devices of the MOS (Metal Oxide Semiconductor) type and in particular for integrated circuits able to be used in an environment subjected to radiation.
• MOS Metal Oxide Semiconductor
• FIG. 1 The state of the art closest to the invention is illustrated in Figure 1 attached.
• This figure shows schematically and in section the structure of a MOS-type transistor 10 produced on an SOI substrate.
• the active region 12 of the transistor 10 is formed in a thin film of silicon 14 covering a buried layer of silicon oxide S: 0-16 the active region 1? is delimited by thick paves of silicon oxide 17 of the LOCOS type (LOcalized Oxidation of Silicon) formed in the thin film 1 ⁇ ⁇ e silicon.
• Paves 17 isolate each other differently transistors produced on the same SOI substrate.
• a grid structure 18 comprises a stack with, in order, a layer of grid insulation 20, a grid 22, a shunt layer 24 forming a contact on the grid 20 and lateral spacers 26 formed on the flanks of the stack.
• the gate structure 18 is arranged above the channel 28 of the transistor and source 30 and drain 32 regions are formed by doping the thin film 14 on either side of the gate structure.
• a thick layer 34 of ⁇ e type BPSG glass covers the active region 12 and coats the grid structure 18.
• Contact holes 36, 38 made in the glass layer 34, directly above the source 30 and of the drain 32, and a metal 40 formed in the holes 36, 38 form conductive paths connecting the source and the drain respectively to metallic interconnection lines 42, 44 formed on the layer 34.
• a transistor in accordance with FIG. 1 requires a high number of photolithography steps to define its constituent elements.
• a first step is necessary for the formation of the field oxide pavers 17.
• a second photolithography step allows the realization of the grid structure 18.
• Finally, a photolithography step is necessary to practice the holes in the glass layer 34 of contact.
• the formation of the grid structure 18 includes the deposition of the grid insulator layer 20, the grid layer 22 and the shunt ⁇ e layer 24, then the etching of these layers according to a mask defining the shape and the dimensions of the grid structure.
• the positioning of the mask defining the grid relative to the mask used to define the oxide pavers is difficult for highly integrated devices.
• the process does not allow very precise alignment of the grid on the active area and there are problems of inversion of the type of carriers on the sides of the active area. These problems are due in particular to the coupling of the grid with the sides of the active area when the field area is partially hollowed out from the field insulator.
• Another difficulty in producing the transistor of FIG. 1 is due to the alignment of the contact holes on the source and drain regions. This difficulty also constitutes a limitation to the miniaturization of the devices.
• an object of the invention is to provide a transistor and its production process on an SOI substrate which does not present the difficulties mentioned above.
• An object is in particular to propose a method in which the alignment of the grid with respect to the active region comprising the channel, on the one hand, and the alignment of the contact points with respect to the grid, on the other hand , are automatic.
• Another aim of the invention is to propose a process with a minimum of photolithography steps.
• An object of the invention is also to propose a transistor allowing total control in weak inversion.
• the low inversion regime is the conduction regime of the transistor below the conduction threshold under the strong inversion regime. We consider that the total control in low inversion is obtained when there is no current leakage in this operating regime.
• the invention finally aims to provide a transistor capable of operating in a so-called hostile environment, subjected to ionizing radiation.
• the invention more specifically relates to a method for producing a transistor on a SOI type support comprising an insulating silicon oxide layer, called buried oxide layer and a film thin silicon covering the buried oxide layer, the process comprising the following successive steps: a) formation on the thin silicon film of a stack comprising, in order, a layer of gate insulator, and a layer of gate material, b) formation on the stack of a first etching mask in a pattern corresponding to an active region of the transistor, c) etching of the layer of gate material, of the layer of gate insulator, and thin film, to form a column with first flanks defined according to the pattern of the first etching mask, d) formation of a layer of electrical insulating material around the column and flattening of this layer with stop on the column, e ) gra vure of the layer of grid material of the column according to a second mask to form a grid structure with two> flanks, f) electrical insulation of the sides of the grid
• the method of the invention is particularly well suited to SOI type substrates for which the thin film has a thickness less than
• the electrical insulation of the sides of the grid and the formation of self-aligned contact points on the grid makes it possible to avoid the constraint of precise control of the position of contact holes in the layer of electrical insulating material. .
• the method of the invention requires only two photolithography steps to form the transistor.
• the method can also comprise, during step a), the formation of a protective layer above the layer of grid material, the protective layer also being etched during from step c), and forming a stop layer during the planarization of the layer of insulating material in step d).
• the protective layer is removed after step d).
• a function of the protective layer is also to protect the upper part of the grid from any oxidation. So, after removing the protective layer, making contact on the grid with a connecting line or with a layer of conductive material called shunt is facilitated.
• the method may further comprise, after step d) and the exposure of the gate material, the formation of a layer known as a shunt covering the layer of electrical insulating material. and coming into contact with the grid material, the shunt layer also being etched during step e) according to the second etching mask, and second flanks of the snunt layer, formed during step e), also being electrically isolated during step f).
• a layer known as a shunt covering the layer of electrical insulating material. and coming into contact with the grid material, the shunt layer also being etched during step e) according to the second etching mask, and second flanks of the snunt layer, formed during step e), also being electrically isolated during step f).
• the shunt layer preferably made of a metal polysilicon, forms a connection line for addressing the grid.
• step d) oxidation of the sides of the column formed in step c), to cover them with a layer known as oxide of flanks.
• This oxidation makes it possible to round the edges of the active region of the future transistor and promotes the control of its characteristic in low inversion.
• the flank oxide layer also serves as an etching stop layer during step e.
• the formation of contact points on the source and drain regions does not require an additional photolithography step.
• the contacts are formed, for example, by the conformal deposit of a metal layer, self-aligned with respect to the grid structure, and by the polishing of this metal layer.
• the absence of a photolithography step for taking the shots contact avoids delicate alignment problems and allows miniaturization of devices.
• the method can also include the elimination of the grid oxide layer exposed on either side of the grid during step e) and a self-aligned siliciding. of the metal layer with the thin film exposed by the removal of the gate oxide layer. Thanks to this measure, good contact between the source and drain regions and the metal layer is guaranteed.
• the subject of the invention is also a field effect transistor comprising a source, a channel and a drain formed in a portion of silicon film of a structure of silicon on insulator (SOI) type, a field insulation layer. laterally surrounding the portion of silicon film, a grid structure with isolated sides formed above the channel, and source and drain contacts formed on the portion of silicon film between the field insulation layer and the structure grid.
• the source and drain contacts are self-aligned on the grid structure and on the field insulation layer and are directly disposed against the sides of the grid structure.
• the contacts are delimited by a layer, called flank oxide, substantially perpendicular to the portion of silicon film and self-aligned on the field insulation layer.
• FIG. 1 is a schematic longitudinal section of an MOS field effect transistor of a known type
• FIG. 2 is a diagrammatic section of a stack of layers on a SOI type substrate, from which a transistor is produced in accordance with the method of the invention
• FIG. 3 is a schematic section showing the formation of a column by etching the stack of Figure 2
• FIG. 4 and 5 are schematic sections of the stack illustrating a coating of the column with a layer of insulating material and flattening the layer of insulating material,
• FIG. 6 is a schematic section of the stack illustrating the formation of a shunt layer on the structure of FIG. 5,
• FIGS 7 and 8 are sections along a plane VI-VI, indicated in Figure 6, making an angle of 90 ° with the cutting plane of Figures 1 to 6, and illustrate the manufacture of a grid structure
• - Figures 9, 10 and 11 are sections of the stack according to the section plane of Figures 7 and 8 and illustrate the formation of contact points on source and drain regions of the transistor
• - Figure 12 is a sectional view of a particular embodiment of a transistor according to one invention. Detailed description of an embodiment of the invention
• Figure 2 shows the starting structure for manufacturing a transistor.
• the transistor is produced on an SOI substrate
• the buried layer 104 comprising a thin surface film of silicon 102 integral with an insulating silicon oxide layer, known as the buried layer 104.
• the thin film 102 preferably has a thickness less than or equal to 50 nm.
• a first oxide layer 106 is formed by oxidation of silicon on the free surface of the thin layer 102.
• Layer 106 constitutes the gate insulator layer of the transistor that is produced.
• a layer 108 called polyc ⁇ stallm or amorphous silicon grid material, for example, is deposited on the grid insulator layer 106.
• a protective layer 110 for example, of silicon nitride, or of oxide is deposited on the layer 108 of grid material in order to cover the free face thereof.
• This protective layer subsequently serves as a polishing stop layer.
• the stack formed by layers 106, 108 and 110 is designated by the general reference 112.
• a first etching mask 114 is formed on the stack 112 according to photolithography methods known per se.
• the mask 114 defines the dimensions of the active area of the transistor that is produced.
• the following description relates specifically to the production of a single transistor a field effect. However, it is possible to produce simultaneously on the same substrate a plurality of such transistors forming, for example, an integrated circuit.
• a mask is formed on the stack 112 with a plurality of patterns similar to the pattern 114 and defining the active regions of the plurality of transistors.
• the layers 110, 108, 106 of the stack and the film 102 of the substrate 100 are etched.
• the buried oxide layer 104 serves, during this etching, as a stop layer.
• a column 116 visible in FIG. 3 is obtained.
• the column comprises, respectively, portions of the thin film 102, of the layer of gate oxide 106, of the layer of gate 108 and of the protective layer 110.
• the thin film portion 102 of the column 116 corresponds substantially to the active part of the transistor.
• the sides of column 116 are indicated with the reference 118.
• the flanks 118 are oxidized. This oxidation relates in particular to the thin silicon film] 02 and the grid material 108 of the column 116.
• the protective layer 110 limits, in the case of the oxide, and even prevents, in the case silicon nitride, the oxidation of the upper surface of the grid material layer, which it covers.
• Figure 4 shows in section the structure obtained.
• a first characteristic shape is a bird's beak shape at the height of the grid oxide layer 106.
• Another characteristic shape is a rounding of the lower edges of the remaining thin film portion of the column 116.
• Oxidation at high temperature and / or at high pressure is understood to mean oxidation taking place at a temperature above 1000 ° C. and at a pressure above 10 5 Pa.
• oxidation at high pressure reference may be made to the document. "High Pressure Oxidation of Silicon in Dry Oxygen" by Liang N. Lie et al. in Solid-State Science and Technology, December 1982, pages 2828-2833.
• the rounded shape of the thin film portion that is to say of the future active region of the transistor, it is possible to limit the leakage currents of the transistor in a low inversion regime.
• the control of leakage currents in a low inversion regime that is to say below the conduction threshold, makes it possible to reduce the consumption at rest of the transistor.
• the flank oxide layer which covers the flanks 118 of the column 116 is designated by the reference 120. Its thickness is comprised, for example between 5 and 20 nm.
• a next step in the process consists in forming a layer 122 of electrical insulating material around the column 116 to coat it. Layer 120 is shown in Figure ⁇ .
• the electrical insulating material is for example an oxide layer (glass) doped with phosphorus of the PSG or BPSG type. After the deposition of the layer 122 of insulating material, a heat treatment allows its stabilization and its creep.
• the function of the insulating material layer is to mutually isolate different transistors or components produced on the same substrate. Another function is to harden the transistors to ionizing radiation.
• the layer of grid material 108 is exposed and is exposed substantially in the plane of the leveling surface 124 of Ja layer 122.
• doping can be carried out by implantation of the silicon of the gate layer. Impurities are implanted leading to an n or p type conductivity.
• the process continues, as shown in FIG. 6, by the formation above the layer of grid material of a layer 126 called shunt.
• the shunt layer deposited in full plate also covers the planarizing surface of the insulating layer 122.
• the shunt layer 126 is preferably made of a polysilicon of refractory metal. It is covered with a layer of deposited oxide 128, not doped.
• the shunt layer makes it possible to improve the contact on the gate and thus increase the operating speed of the transistor.
• This layer when it is shaped, can also constitute an access line for the polarization of the grid, such as, for example, a line of words.
• a second etching mask 130 formed on the deposited oxide layer 128 defines the location and dimensions of a gate structure 132 above the active region of the transistor.
• the successive etching of the oxide layer 128, the shunt layer 126 and the material layer 108, with stopping on the gate oxide layer 102 and on the side oxide layer 120 makes it possible to obtain the structure of figure 7.
• FIG. 7 and the following figures correspond to a section plane VI-VI, indicated in FIG. 6, and which makes an angle of 90 ° with the section planes of the preceding figures.
• the lateral extension of the etchings according to the second mask 130 is limited in the zone situated above the portion of thin film 102 by the oxidation of flanks 120.
• the etchings according to the mask 130 thus make it possible to release the grid structure 132 which is therefore necessarily aligned with the remaining portion of thin film 102, that is to say aligned with the future active region of the transistor.
• the grid structure includes the grid material layer 108, the shunt layer 126 and the shaped oxide layer 128, shaped.
• the process is continued by an oxidation of the sides 134 of the grid structure, that is to say, in particular, the layers of grid material 103, and the layer of shunt 126. It is also possible directly deposit a fine oxide on the sides.
• a first implantation of ions is carried out in the thin film 102 using the grid structure 132 as implantation mask.
• the doped regions formed during the first implantation are shown in FIG. 7. And indicated by the reference 135.
• a second implantation is carried out at a higher dose. The implantation is carried out with impurities leading to a conductivity n + or p + depending on the type of transistor channel produced.
• FIG. 8 After implantation, annealing is carried out and the structure shown in FIG. 8 is obtained.
• the source and drain regions bear the references 140 and 142 respectively.
• the lateral spacers 136 are obtained by depositing a layer which makes it possible to isolate the grid from the contact zones 150 and 152, then by attacking this layer by an anisotropic etching, selective with respect to the oxide on the flanks.
• this layer is made of silicon nitride. It can be made of oxide but its selectivity during the etching of the spacers is less good.
• the lateral spacers 136 have the function not only of forming gradual source and drain regions but also of protecting 1 - these regions in the vicinity of the grid and on the edge of contact points made subsequently. In particular, the spacers 136 make it possible to avoid or limit a lateral attack on the layer 122 of insulating material (PSG) during cleaning operations which precede the formation of contact points on the drain and source regions.
• PSG insulating material
• the formation of contact points on the source and drain regions is preceded by the elimination of the residual gate oxide layer around the gate structure, to expose a part of the thin film 102 corresponding to the source. and to the drain.
• the oxide sides of the grid structure and the oxide sides 120 covering laterally the layer 122 of insulating material, are protected by the lateral spacers 136.
• a layer of metal 148 for example of tungsten, is then formed by chemical vapor deposition on the entire structure. As shown in FIG. 9, the metal layer 148 comes into contact with the exposed source and drain regions 140, 142 and coats the grid structure 132
• the technique of metal deposition in the vapor phase (CVDj) allows obtain a compliant deposit.
• the free surface 124 of the layer 122 of insulating material can be covered with a layer 125 of titanium / tungsten and advantageously a two-layer system whose composition makes it possible to perform the functions diffusion barrier and ⁇ e contact barrier It is for example a layer of Ti-W in a composition close to stoichiometry.
• This layer represented in FIG. 9, constitutes a layer metal attachment and also serves as a diffusion barrier of the metal in the insulation.
• the source and drain 140, 142 are silicided before the deposition of the layer 125 using selective siliciding on the bare silicon. Siliconization makes it possible to reduce the resistance at the metal-semiconductor interface and thus improve the contacts made on the source and drain.
• the silicided parts are indicated with the reference 149.
• the metal layer is polished in order to flatten it up to the silicon oxide layer 128 of the grid structure 132.
• the layer 125 is also polished to the following.
• the metal layer and the bonding layer can, as shown in FIG. 11, be etched for the shaping of contacts 150, 152.
• Other conventional operations ae depositing metals or insulators make it possible to carry out interconnections of the transistor with an integrated circuit. These operations, known per se, are not detailed here.
• FIG. 11 also shows the characteristics of the transistor which is the subject of the invention.
• the main characteristics of this transistor are: an active region, formed in layer 102, the edges of which are rounded, a gate 108, 132 self-aligned on the channel in the active region, an active region protected by an insulation layer 122, and contacts 150, 152 self-aligned on both the grid and the insulation layer.
• the flank oxide layer 120 which extends substantially perpendicular to the active region makes it possible to avoid any risk of covering the metal of the contacts on the edges of the active zone, that is to say on the sides of the thin film portion forming the active area.
• the insulating materials forming the flank oxide layer 120 and the insulation layer 122 are different.
• the sidewall oxide layer is formed by oxidation while the insulation layer 122 is formed by deposition.
• FIG. 11 illustrates the production of a transistor with a symmetrical structure
• FIG. 12 shows a transistor, according to the invention, in which the gate structure 132 is not centered relative to the sides of the insulating layer 122.
• the gate is however always perfectly aligned with respect to the channel ⁇ e the active region Sur Figures 11 and 12, the channel is indicated with the reference 103.
• the contact sockets 150, 152 formed on the sources and drain 140, 142, are self-aligned on the grid and the active area and are arranged directly against the grid structure, in contact with the lateral spacers
• the contact points 150, 152 constitute in a way raised and metallized source and drain.
• the method and the transistor of the invention make it possible to increase the density of integration and, as indicated here or now, to make the economy of an expensive and critical masking step for making the contacts on the source and drain.

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• Engineering & Computer Science (AREA)
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• 1996
  • 1996-06-27 FR FR9608007A patent/FR2750534B1/fr not_active Expired - Fee Related
• 1997
  • 1997-06-26 WO PCT/FR1997/001146 patent/WO1997050118A1/fr active Application Filing
  • 1997-06-26 JP JP10502458A patent/JP2000514241A/ja active Pending
  • 1997-06-26 US US09/147,438 patent/US6150241A/en not_active Expired - Lifetime
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