EP0951738A1 - Agencement pour commander les lignes paralleles d'un dispositif a cellules de memoire - Google Patents

Agencement pour commander les lignes paralleles d'un dispositif a cellules de memoire

Info

Publication number
EP0951738A1
EP0951738A1 EP97951073A EP97951073A EP0951738A1 EP 0951738 A1 EP0951738 A1 EP 0951738A1 EP 97951073 A EP97951073 A EP 97951073A EP 97951073 A EP97951073 A EP 97951073A EP 0951738 A1 EP0951738 A1 EP 0951738A1
Authority
EP
European Patent Office
Prior art keywords
lines
threshold voltage
voltage value
mos transistors
bln
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP97951073A
Other languages
German (de)
English (en)
Inventor
Franz Hofmann
Josef Willer
Hans Reisinger
Paul Werner Von Basse
Wolfgang Krautschneider
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0951738A1 publication Critical patent/EP0951738A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/38—Doping programmed, e.g. mask ROM
    • H10B20/383—Channel doping programmed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/60—Peripheral circuit regions
    • H10B20/65—Peripheral circuit regions of memory structures of the ROM only type

Definitions

  • Bit lines and word lines are used to control the individual memory cells in memory cell arrangements. Each bit line and word line crossing is uniquely assigned a memory cell which can be selected via the latter. This applies to all memory cell arrangements, in particular for dynamic and static memory cell arrangements, for read-only memory cell arrangements and for electrically programmable memory cell arrangements.
  • bit lines and word lines are usually implemented as a family of parallel lines.
  • selection switches or decoder circuits are provided in the periphery of the memory cell arrangement, which are electrically connected to each of the lines.
  • the electrical connection between the bit or word lines and the selection switch or the decoder circuit is implemented technologically via contact holes filled with contacts and a metallization level.
  • the invention is based on the problem of specifying an arrangement for controlling parallel lines of a memory cell arrangement in which an increased packing density is achieved.
  • the parallel lines that are to be driven comprise doped regions arranged in a semiconductor substrate.
  • the parallel lines are bit lines.
  • the parallel lines are formed, for example, in the area of the cell array as strip-shaped doped regions which connect a plurality of adjacent memory cells to one another.
  • the parallel lines in the memory cell field are designed as series-connected MOS transistors which are driven in the sense of a NAND architecture. Memory cell arrangements with such parallel lines have been proposed, for example, in DE-PS 44 37 581, DE-OS 195 10 042 and DE-PS 443 47 25.
  • a predetermined number of the parallel lines are electrically connected to one another and to a common node. This is done, for example, via a further doped area that overlaps the relevant parallel lines.
  • the parallel lines each have a plurality of MOS transistors which are connected in series. These MOS transistors are arranged in the area of the intersection points of the selection lines with the parallel lines.
  • the gate electrode of these MOS transistors is formed by one of the selection lines.
  • the gate electrode is formed in each case by the selection line, which runs above the respective MOS transistor.
  • These MOS transistors are arranged outside the actual cell field.
  • the MOS transistors connected in series are each arranged in the extension of the corresponding parallel line outside the cell field.
  • the different threshold voltage values can be realized by different channel doping or by different thicknesses of the gate dielectric.
  • the second threshold voltage value is preferably realized by providing the MOS transistors with the second threshold voltage value in the channel region with an additional channel doping.
  • the selection lines are acted on with two different levels.
  • a first level lies between the first threshold voltage value and the second threshold voltage value, the amount of the second level is greater than the first threshold voltage value.
  • the MOS transistors with the second threshold voltage value conduct both when the first level is present and when the second level is present. They therefore act as resistors.
  • the MOS transistors with the first threshold voltage value conduct only if the second level is present on the selection line which forms their gate electrode.
  • the individual parallel lines are selected by applying appropriate levels to the selection lines and by arranging the MOS transistors with the first threshold voltage value in the parallel lines. This eliminates the need to open contact holes for the individual parallel lines, which limits the packing density in the known selection switches and decoder circuits.
  • the arrangement for controlling parallel lines of a memory cell arrangement can be implemented both as a selection switch and as a decoder.
  • the number of selection lines and the number of parallel lines connected to one of the common nodes are the same.
  • Each of the parallel lines is clearly assigned to one of the selection lines.
  • a MOS transistor with the first threshold voltage value is arranged only at the crossing point of the parallel lines with the associated selection.
  • each decoder 2 n (2 high n) parallel lines are connected to one of the common nodes.
  • 2 n (2 times n) selection lines are provided, each of which is complementary in pairs with respect to the arrangement of the MOS transistors with the first threshold voltage value and the second threshold voltage value.
  • i is a serial number with which the selection line pairs are counted.
  • the design as a decoder circuit has the advantage that, since fewer selection lines are required, the circuit requires less space.
  • training as a selector switch has the advantage that several of the parallel lines can be controlled simultaneously by applying the levels to the respectively assigned selector line. This is advantageous when applying a common voltage, for example when deleting or programming.
  • FIG. 1 shows a plan view of a section of a memory cell arrangement with a 1 out of 8 selection switch.
  • FIG. 2 shows the section designated II-II in FIG. 1
  • FIG. 3 shows a plan view of a section of a memory cell arrangement with an 1 out of 8 decoders.
  • FIG. 4 shows the section designated IV-IV in FIG. 3.
  • Parallel word lines WL run at right angles to this.
  • the bit lines Bin each comprise MOS transistors connected in series, the gate electrode of which is formed by the crossing word lines WL (see FIG. 2).
  • Each of the MOS transistors is formed from two source / drain regions 1, the channel region arranged between them, a gate dielectric 2 arranged above them and the corresponding word line WL.
  • Adjacent MOS transistors that are connected to one another have a common source / drain region 1.
  • selection lines ALn, n 0.1,... 7 run across the bit lines BLn (see FIG. 1).
  • the selection lines ALn run on the surface of a semiconductor substrate in which the source / drain regions 1 are arranged.
  • the selection lines ALn are strip-shaped and consist of conductive material, for example doped polysilicon, metal silicide or metal.
  • An n-channel MOS transistor is arranged at the points of intersection of the selection lines ALn with the bit lines BLn.
  • Eight bit lines BLn are electrically connected to one another and to a common node K. This connection is realized, for example, by a doped contact area in the substrate.
  • the number of selection lines ALn is equal to the number of interconnected bit lines BLn, that is eight.
  • a selection line ALn is uniquely assigned to each of the bit lines BLn.
  • a MOS transistor Ml with a first threshold voltage value is arranged at the intersection of the bit lines BLn and ALn assigned to each other.
  • the remaining MOS transistors M2 have a second threshold voltage value. The amount of the second threshold voltage value is less than the first threshold voltage value.
  • Each of the MOS transistors M1, M2 has two source / drain regions 3, an intermediate channel region, a gate dielectric 4 and one of the selection lines ALn as a gate electrode.
  • MOS transistors adjacent along a bit line BLn are connected to one another via a common source / drain region 3.
  • the MOS transistors M1, M2 arranged along a bit line BLn are also connected in series with the MOS transistors arranged in the cell array.
  • the connection between the MOS transistors arranged in the cell array and the first of the MOS transistors arranged in the area of the selection lines ALn is realized in that the source / drain region 1 and the source / drain region 3 overlap so that they form a common doped area (see Figure 2).
  • the channel doping 5 is formed, for example, by implantation with A5 with a dose of 1 ⁇ 10 14 cm -2 and an energy of 40 keV.
  • the channel doping 5 is preferably dimensioned such that the second threshold voltage value is less than zero.
  • the assigned selection line is used to control one of the bit lines Bin, for example BL3, for example to read out a memory cell or to apply a potential
  • Aln for example AL3, is subjected to a voltage level that is greater than the first threshold voltage value.
  • the remaining selection lines are supplied with a voltage level which lies between the first threshold voltage value and the second threshold voltage value.
  • all MOS transistors with the second threshold voltage value conduct. They act as resistors.
  • the MOS transistors Ml with the first threshold voltage value on the other hand, only the one whose gate electrode is connected to the selected selection line ALn, for example AL3, conducts.
  • the selected bit line BLn for example BL3 is electrically connected to the node K.
  • the remaining bit lines BLn are electrically isolated from the node, since the associated MOS transistors Ml block with the first threshold voltage value.
  • the first threshold voltage value is set to + 0.5 V
  • the second threshold voltage value is set to - 2.0 V, for example.
  • 0 V and 2 V are used as voltage levels.
  • the described embodiment corresponds to a selection switch.
  • the bit lines BL'n have a strip-shaped doped region 6 which runs along a ner bit line BL'n connects adjacent memory cells to one another (see FIG. 4).
  • the selection lines AL'n also contain conductive material, for example doped polysilicon, metal silicide or metal.
  • n-channel MOS transistors are arranged, the two source / drain regions 7, a channel region arranged in between, a gate dielectric 8 arranged above the channel region and one of the selection lines AL'n as the gate electrode (see FIG. 4).
  • MOS transistors adjacent to one another along a bit line BL'n are connected to one another in that they have a common source / drain region 7.
  • the source / drain region 7 of the last MOS transistor overlaps the strip-shaped doped region 6 and forms a common doped region with it. In this way, the series-connected MOS transistors are electrically connected to the strip-shaped region 6.
  • the node K ' is designed as a doped region in the semiconductor substrate and overlaps the last source / drain region 7 of the MOS transistors connected in series, so that it forms a continuous doped region with this (see FIGS. 3 and 4).
  • n_1 MOS transistors Ml 'with a first threshold voltage value and 2 n_1 MOS transistors M2' with a second threshold voltage value are arranged alternately along the selection lines AL'n, the second threshold voltage value being smaller than the first threshold voltage.
  • the arrangement of the MOS transistors along the selection lines of one of the selection line pairs is complementary.
  • a MOS transistor Ml 'with a first threshold voltage value and a MOS transistor M2' with the second threshold voltage value are alternately arranged in the selection lines AL'O, AL'l.
  • Two MOS transistors Ml 'with the first threshold voltage value and two MOS transistors M2' with the second threshold voltage value are alternately arranged along the selection lines AL'2 and AL'3.
  • Four MOS transistors Ml 'with the first threshold voltage value and four MOS transistors M2' with the second threshold voltage value are alternately arranged along the selection lines AL'4 and AL'5.
  • the second threshold voltage value is implemented by an additional channel doping 9 in the channel region of the MOS transistors M2 '(see FIG. 4).
  • the additional channel doping 9 is effected by an implantation with A5 with a dose of 1 x 10 14 cm " 2 and an energy of 40 keV.
  • the selection line pairs are each supplied with complementary selection signals. Two selection signals are used, one of which is greater in magnitude than the first threshold voltage value and the other between the first threshold voltage value and the second threshold voltage value.
  • the higher level is applied to the selection lines AL'O, AL'2 and AL'5, for example of the selection signal, to the selection lines AL'l, AL'3 and AL'4 the lower level of the selection line signal is applied.
  • the bit line BL'4 is connected to the node K ', while the other bit lines BL'n are interrupted by blocking MOS transistors Ml' with the first threshold voltage value with respect to the node K '.
  • the MOS transistors M2 'with the second threshold voltage value also conduct when their gate electrode is driven with the lower level of the selection signal. They act as resistors.
  • the first threshold voltage value becomes + 0.5 V
  • the second threshold voltage value preferably becomes less than zero, for example - 2.0 V
  • the higher level of the selection signal becomes, for example, 2 V
  • the low level of the selection signal for example set to 0 V.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)

Abstract

Afin de commander des lignes parallèles, par exemple les lignes de transmission de bits (BLn) dans un dispositif à cellules de mémoire avec des zones dopées dans un substrat semi-conducteur, plusieurs lignes (BLn) sont électriquement connectées les unes aux autres et à un noeud commun (K). Plusieurs lignes de sélection (ALn) sont disposées transversalement aux lignes (BLn). Des transistors MOS (M1, M2) câblés en série le long d'une des lignes (BLn) et dont l'électrode de grille est formée par la ligne de sélection correspondante (ALn) sont situés aux points d'intersection entre les lignes (BLn) et les lignes de sélection (ALn). Au moins un transistor MOS (M1) dans chacune des lignes parallèles (BL1) présente une tension d'utilisation plus élevée que les autres.
EP97951073A 1996-12-17 1997-11-12 Agencement pour commander les lignes paralleles d'un dispositif a cellules de memoire Withdrawn EP0951738A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19652538 1996-12-17
DE19652538 1996-12-17
PCT/DE1997/002654 WO1998027593A1 (fr) 1996-12-17 1997-11-12 Agencement pour commander les lignes paralleles d'un dispositif a cellules de memoire

Publications (1)

Publication Number Publication Date
EP0951738A1 true EP0951738A1 (fr) 1999-10-27

Family

ID=7815043

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97951073A Withdrawn EP0951738A1 (fr) 1996-12-17 1997-11-12 Agencement pour commander les lignes paralleles d'un dispositif a cellules de memoire

Country Status (6)

Country Link
US (1) US6125050A (fr)
EP (1) EP0951738A1 (fr)
JP (1) JP2001506409A (fr)
KR (1) KR100408575B1 (fr)
TW (1) TW363266B (fr)
WO (1) WO1998027593A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7971130B2 (en) 2006-03-31 2011-06-28 Marvell International Ltd. Multi-level signal memory with LDPC and interleaving

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2683078A1 (fr) * 1991-10-29 1993-04-30 Samsung Electronics Co Ltd Memoire morte a masque de type non-et.
JP2851962B2 (ja) * 1992-01-21 1999-01-27 シャープ株式会社 半導体読み出し専用メモリ
JP3190091B2 (ja) * 1992-02-21 2001-07-16 富士通株式会社 記憶装置とその情報読み出し方法および情報書き込み方法
GB9217743D0 (en) * 1992-08-19 1992-09-30 Philips Electronics Uk Ltd A semiconductor memory device
KR960009994B1 (ko) * 1992-10-07 1996-07-25 삼성전자 주식회사 반도체 메모리 장치 및 그 제조방법
JPH06318683A (ja) * 1993-05-01 1994-11-15 Toshiba Corp 半導体記憶装置及びその製造方法
JPH0729999A (ja) * 1993-07-15 1995-01-31 Mitsubishi Electric Corp 不揮発性半導体記憶装置およびその製造方法
US5535156A (en) * 1994-05-05 1996-07-09 California Institute Of Technology Transistorless, multistable current-mode memory cells and memory arrays and methods of reading and writing to the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9827593A1 *

Also Published As

Publication number Publication date
JP2001506409A (ja) 2001-05-15
KR100408575B1 (ko) 2003-12-06
WO1998027593A1 (fr) 1998-06-25
KR20000057660A (ko) 2000-09-25
TW363266B (en) 1999-07-01
US6125050A (en) 2000-09-26

Similar Documents

Publication Publication Date Title
EP0025130B1 (fr) Mémoire morte intégrée très dense
DE3842511C2 (fr)
DE3936676C2 (fr)
DE4028575C2 (de) Speicheranordnung mit einer Vielzahl elektrisch programmier- und löschbarer Speicherzellen
DE3305056C2 (de) Halbleiterspeicher
DE3779705T2 (de) Integrierte speicherschaltung mit blockadressierung.
DE69122065T2 (de) Programmierbare integrierte Schaltung
DE3037315C2 (fr)
DE2937337C2 (de) Elektrisch schaltbares energieunabhängiges Speicherstem
DE2731873A1 (de) Serien-festspeicher-struktur
DE3311923A1 (de) Duennfilmtransistoranordnung
DE69829092T2 (de) Festwertspeicher
DE2601622A1 (de) Programmierbarer und loeschbarer festwertspeicher
DE2261786C3 (fr)
DE2011794A1 (de) Halbleiterspeicheranordnung
DE2655999A1 (de) Speicherzelle mit transistoren, die mit verschiedenen schwellenwertspannungen arbeiten
DE3046524C2 (de) Halbleitervorrichtung
DE2153284C3 (de) Schaltungsanordnung zur Einstellung gewählter Feldeffektbauelemente einer Speichermatrix ohne Störung der nicht gewählten Elemente
DE2705992C3 (fr)
DE3046376A1 (de) Halbleiter-speichervorrichtung
DE68916855T2 (de) Nichtflüchtige Halbleiterspeicheranordnung.
WO1998027593A1 (fr) Agencement pour commander les lignes paralleles d'un dispositif a cellules de memoire
EP0075739B1 (fr) Cellule de mémoire comportant un transistor à effet de champ à deux électrodes de porte et son mode de fonctionnement
DE102004044413A1 (de) Halbleiterspeicherbauelement
DE2439986C3 (de) Halbleiterfestwertspeicher

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19990607

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB IT

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: INFINEON TECHNOLOGIES AG

17Q First examination report despatched

Effective date: 20071011

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20080911