EP0916162A1 - Procede de fonctionnement d'un ensemble de cellules memoire - Google Patents

Procede de fonctionnement d'un ensemble de cellules memoire

Info

Publication number
EP0916162A1
EP0916162A1 EP97937412A EP97937412A EP0916162A1 EP 0916162 A1 EP0916162 A1 EP 0916162A1 EP 97937412 A EP97937412 A EP 97937412A EP 97937412 A EP97937412 A EP 97937412A EP 0916162 A1 EP0916162 A1 EP 0916162A1
Authority
EP
European Patent Office
Prior art keywords
silicon oxide
threshold voltage
oxide layer
layer
voltage value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP97937412A
Other languages
German (de)
English (en)
Inventor
Hans Reisinger
Reinhard Stengl
Ulrike GRÜNING
Hermann Wendt
Josef Willer
Martin Franosch
Herbert Schäfer
Wolfgang Krautschneider
Franz Hofmann
Volker Lehmann
Thomas Böhm
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0916162A1 publication Critical patent/EP0916162A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • Non-volatile EEPROM cells are usually used for the permanent storage of data.
  • Various technologies have been proposed for realizing EEPROM cells (see, for example, Lai et al, IED Tech. Dig. 1986, pages 580-586).
  • MOS transistors are used as memory cells in the so-called SONOS or MNOS cells.
  • the MOS transistor includes a gate dielectric that includes at least one silicon nitride layer below the gate electrode and a silicon oxide layer between the silicon nitride layer and the channel region. Charge carriers are stored in the silicon nitride layer to store the information.
  • the thickness of the silicon oxide layer is a maximum of 2.2 nm.
  • the thickness of the silicon nitride layer in modern SONOS memories is usually about 10 nm.
  • a further silicon oxide layer is usually provided, which has a thickness of 3 to 4 nm.
  • the gate electrode is wired so that the charge carriers stored in the silicon nitride layer tunnel through the 2.2 nm thick silicon oxide layer into the channel region and from the channel region charge carriers of the opposite conductivity type tunnel through the silicon oxide layer into the silicon nitride layer.
  • SONOS cells have a data retention time of ⁇ 10 years. This time is too short for many applications, for example for storing data in computers.
  • EEPROM cells with a floating gate are used as an alternative to the SONOS cells. These are suitable for applications in which longer times are required for data retention.
  • a floating gate electrode which is completely surrounded by dielectric material, is arranged in these memory cells between a control gate electrode and the channel region of the MOS transistor. The information is stored in the form of charge carriers on the floating gate electrode.
  • These memory cells which are also referred to as FLOTOX cells, can be electrically written and erased.
  • the control gate electrode is connected to such a potential that charge carriers flow (write) from the channel region onto the floating gate electrode or charge carriers flow from the floating gate electrode into the channel region (erase).
  • These FLOTOX cells have data retention times of less than 150 years.
  • the space requirement of the FLOTOX cells is greater than that of the SONOS cells, since the control gate electrode must overlap the floating gate electrode on the side.
  • Radiation hardness refers to the insensitivity of the stored charge to external radiation sources and / or electromagnetic fields.
  • the invention is based on the problem of specifying a method for operating a memory cell arrangement in which a time for data retention of at least 150 years is reached and in which digital information stored in the memory cell arrangement can be changed electrically.
  • This problem is solved according to the invention by a method according to claim 1. Further developments emerge from the subclaims.
  • a memory cell arrangement which, as memory cells, each comprises a MOS transistor with source region, channel region, drain region, gate dielectric and gate electrode, which has a dielectric triple layer as the gate dielectric.
  • the dielectric triple layer comprises a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer.
  • the silicon nitride layer is arranged between the two silicon oxide layers.
  • the first silicon oxide layer and the second silicon oxide layer each have a thickness of at least 3 nm.
  • the memory cell used in the method according to the invention differs from conventional SONOS cells in that the first silicon oxide layer, which is arranged between the channel region of the MOS transistor and the silicon nitride layer, has a thickness of at least 3 nm. In conventional SONOS cells, this thickness is a maximum of 2.2 nm.
  • the knowledge is exploited that in conventional SONOS cells the charge is transported through the first silicon oxide layer mainly via direct tunneling and modified Fowler-Nordheim tunneling.
  • the tunnel probability for direct tunneling and modified Fowler-Nordheim tunneling and thus that
  • the thickness of the tunnel barrier that is, the thickness of the first silicon oxide layer
  • the electric field Since in conventional SONOS cells the first silicon oxide layer is a maximum of 2.2 nm and the second silicon oxide layer is 3 to 4 nm thick, the current through direct current always prevails in electrical fields below 10 MV / cm Tunneling through the first silicon oxide layer. This direct tunnel current is used to write and erase the information by connecting the gate electrode accordingly.
  • the method according to the invention takes advantage of the fact that the tunnel probability for direct tunneling decreases sharply with increasing thickness of the first silicon oxide layer and becomes very small with a thickness of at least 3 nm. At a thickness of 3 nm, the tunneling probability for direct tunneling is more than a factor 10 6 below that at 2 nm.
  • the first silicon oxide layer and the second silicon oxide layer are each at least 3 nm thick in the memory cell which is used in the method according to the invention, charge carrier transport from the silicon nitride layer to the gate electrode or to the channel region is largely avoided in this memory cell by direct tunneling. This means that the charge stored in the silicon nitride layer remains practically indefinitely. The time for data retention in this memory cell is therefore significantly longer than in conventional SONOS cells. It is> 1000 years instead of 10 years for conventional SONOS cells.
  • the tunneling probability for direct tunneling of charge carriers through the two silicon oxide layers is very high small.
  • Charge carrier transport through the first silicon oxide layer or second silicon oxide layer takes place only through Fowler-Nordheim tunnels.
  • the current intensity of the charge carrier transport through Fowler-Nordheim tunnels only depends on the strength of the applied electric field. It is not explicitly dependent on the thickness of the tunnel barrier, that is to say the thickness of the first silicon oxide layer or second silicon oxide layer.
  • Fowler-Nordheim tunneling of electrons dominates charge transport regardless of the polarity of the field. This means that both when a positive voltage is applied and when a negative voltage is applied to the gate electrode, Fowler-Nordheim tunneling of electrons into the silicon nitride layer. If a positive voltage is present at the gate electrode, electrons tunnel from the channel region through the first silicon oxide layer into the silicon nitride layer. If, however, there is a negative voltage at the gate electrode, electrons tunnel through the second silicon oxide layer into the silicon nitride layer through Fowler-Nordheim tunnels from the gate electrode.
  • a first write voltage is used to write a first logic value into the memory cell, and a second voltage is used to write a second logic value Write voltage applied to the gate electrode of the memory cell.
  • the current intensity of the charge carrier transport through the first silicon oxide layer is greater than the current strength of the charge carrier transport through the second silicon oxide layer because the amount of charge stored in the silicon nitride layer is that distorted electrical field.
  • the amount of charge stored in the silicon nitride layer causes the electric field which acts over the first silicon oxide layer between the channel region and the silicon nitride layer to be greater than the electric field which acts over the second silicon oxide layer between the gate electrode and the silicon nitride layer.
  • a positive voltage is applied to the gate electrode, for example, if the logical value was stored, to which the smaller of the two charges in the gate dielectric is assigned. If the logical value to which the higher of the two charge quantities is assigned was stored, a negative voltage is applied to the gate electrode.
  • a negative voltage is applied to the gate electrodes by several memory cells at the same time.
  • the memory cells in which the other logical value is to be stored are then written in the manner described above.
  • This method makes use of the fact that the amounts of charge stored in the gate dielectric hardly change when the associated writing voltage is applied again. This procedure has the advantage of being a change of the stored information is possible more quickly, since the change in the amount of charge to the lower value, which is time-consuming, takes place in blocks for several memory cells at the same time.
  • the difference in the thicknesses of the first silicon oxide layer and the second silicon oxide layer is preferably in the range between 0.5 nm and 1 nm.
  • the smaller of the thicknesses of the first silicon oxide layer and the second silicon oxide layer is in the range between 3 nm and 5 nm Silicon nitride layer is at least 5 nm.
  • the MOS transistor has a gate electrode made of n-doped silicon.
  • the lower value of the first threshold voltage value and the second threshold voltage value is set to be 0.5 to 1.5 V, preferably 1 V, lower.
  • a read voltage is applied which lies between the first threshold voltage value and the second threshold voltage value and which is preferably just above, for example 0.1 to 0.5 V, above the lower threshold voltage value.
  • the first amount of charge and the second amount of charge are preferably dimensioned such that they both bring about a positive shift in the threshold voltage. You can quickly switch back and forth between the first threshold voltage value and the second threshold voltage value, which are stable due to the layer thicknesses.
  • the gate electrode can be formed both from n-doped silicon and from metal, metal silicide or p + -doped silicon.
  • the use of p + -doped silicon for the gate electrode has the advantage that the energy stored in the memory cell arrangement can be changed more quickly.
  • the MOS transistors in the memory cells can be designed as both planar and vertical MOS transistors.
  • a source region 2 and a drain region 3, which are n-doped, for example, are provided in a substrate 1 which comprises monocrystalline silicon at least in the region of a memory cell.
  • a channel region 4 is arranged between the source region 2 and the drain region 3.
  • Source region 2, channel region 4 and drain region 3 are arranged, for example, next to one another on the surface of the substrate 1. Alternatively, they can also be arranged as a vertical layer sequence.
  • a dielectric triple layer Arranged above the channel region 4 is a dielectric triple layer, which comprises a first SiO 2 layer 51, an Si3N 4 layer 52 and a second SiO 2 layer 53.
  • the first SiO 2 layer 51 is arranged on the surface of the channel region 4 and has a thickness of 3 to 6 nm, preferably 4 nm.
  • the Si 3 N 4 layer 52 is on the surface of the first SiO 2 layer 51 arranged. It has a thickness of at least 5 nm, preferably 8 nm.
  • the second SiO 2 layer 53 is arranged on the surface of the Si3N 4 layer 52, the thickness of which is 0.5 to 1 nm greater than the thickness of the Most SiO 2 layer 52 is, that is in the range between 3.5 and 6 nm, preferably 4.5 to 5 nm.
  • a gate electrode 6 made of, for example, n-doped polysilicon is arranged on the surface of the dielectric triple layer 5.
  • the gate electrode 6 has a thickness of, for example, 200 nm and a dopant concentration of, for example, 10 21 cm "3.
  • the gate electrode 6 can alternatively also be made of metal, for example aluminum, a metal silicide, for example TiSi2, or of p + -doped Polysilicon are formed.
  • a positive voltage is applied to the gate electrode of the memory cell for the first time that information is written into one of the memory cells.
  • a first write voltage of + 14 V is applied to the gate electrode in order to write in a first logic value to which a threshold voltage of the MOS transistor of 3 V is assigned.
  • Write time is 1 ms.
  • a second write voltage of + 15.5 V is applied to the gate electrode.
  • the write time is 1 ms.
  • a read voltage of 3.1 V is applied to the gate electrode. If the first logic value assigned to a threshold voltage of 3 V is stored in the memory cell, the MOS transistor does not conduct. If, on the other hand, the second logic value is assigned, which is assigned a threshold voltage of 4 V, a current flows through the MOS transistor.
  • a voltage of + 15.5 V for 1 ms is applied to the gate electrode of the memory cell, if the second logic value was stored in the memory cell. This changes the threshold voltage of the MOS transistor from 3 V to 4 V, so that the second logic value is now stored in the memory cell.
  • the memory cell has a threshold voltage of 4 V
  • a voltage of -14 V is applied to the gate electrode for 300 ms to change the stored information. Since at this voltage the current intensity through Fowler-Nordhei tunnels from the silicon nitride layer into the channel area is greater than from the gate electrode into the silicon nitride layer, the threshold voltage of the MOS transistor changes from 4 V to 3 V, so that after the Write operation in the memory cell the first logical value is stored. This asymmetry of the current strengths is caused by the amount of charge stored in the silicon nitride layer, which leads to a distortion of the electric field.
  • the time for data retention is more than 1000 years. Extrapolation found that even after 1000 years with a first threshold voltage value of 3 V and a second threshold voltage value of 4 V, the difference between the first threshold voltage value and the second threshold voltage value is greater than 0.8 V. This difference is called the memory window. This means that even after 1000 years, by applying a read voltage of 3.1 V, a distinction can be made between the first logic value and the second logic value.

Abstract

L'invention concerne un ensemble de cellules mémoire comprenant des transistors MOS en tant que cellules mémoire, qui présentent, en tant que diélectrique de la grille, une triple couche diélectrique (5) constituée d'une première couche d'oxyde de silicium (51), d'une couche de nitrure de silicium (52) et d'une deuxième couche d'oxyde de silicium (53), les couches d'oxyde de silicium présentant chacune une épaisseur d'au moins 3 nm. Pour le stockage de données numériques dans ces cellules mémoire, une première valeur de tension de seuil du transistor MOS est affectée à une première valeur logique, et une seconde valeur de tension de seuil est affectée à une seconde valeur logique. Les informations stockées dans la cellule mémoire peuvent être modifiées par application d'un niveau de tension correspondant, bien que l'élimination complète de la charge stockée dans la couche de nitrure de silicium soit impossible en raison de l'épaisseur des couches d'oxyde de silicium. Le fait que le champ électrique dans la triple couche diélectrique est distordu par la charge stockée dans la couche de nitrure de silicium, est utilisé lors de la modification de la tension de seuil.
EP97937412A 1996-08-01 1997-07-29 Procede de fonctionnement d'un ensemble de cellules memoire Withdrawn EP0916162A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19631155 1996-08-01
DE19631155 1996-08-01
PCT/DE1997/001601 WO1998006140A1 (fr) 1996-08-01 1997-07-29 Procede de fonctionnement d'un ensemble de cellules memoire

Publications (1)

Publication Number Publication Date
EP0916162A1 true EP0916162A1 (fr) 1999-05-19

Family

ID=7801542

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97937412A Withdrawn EP0916162A1 (fr) 1996-08-01 1997-07-29 Procede de fonctionnement d'un ensemble de cellules memoire

Country Status (6)

Country Link
US (1) US6040995A (fr)
EP (1) EP0916162A1 (fr)
JP (1) JP2000515328A (fr)
KR (1) KR20000029664A (fr)
TW (1) TW355796B (fr)
WO (1) WO1998006140A1 (fr)

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Publication number Priority date Publication date Assignee Title
WO1999049517A1 (fr) * 1998-03-24 1999-09-30 Siemens Aktiengesellschaft Ensemble de cellules memoires et son procede de realisation
EP1068645B1 (fr) * 1998-03-24 2014-05-07 Infineon Technologies AG Ensemble de cellules memoires et son procede de realisation
JP3973819B2 (ja) 1999-03-08 2007-09-12 株式会社東芝 半導体記憶装置およびその製造方法
JP4198903B2 (ja) * 2001-08-31 2008-12-17 株式会社東芝 半導体記憶装置
US6630384B1 (en) * 2001-10-05 2003-10-07 Advanced Micro Devices, Inc. Method of fabricating double densed core gates in sonos flash memory
KR100432888B1 (ko) * 2002-04-12 2004-05-22 삼성전자주식회사 비휘발성 메모리 소자 및 그 제조방법
KR100432889B1 (ko) * 2002-04-12 2004-05-22 삼성전자주식회사 2비트 기입가능한 비휘발성 메모리 소자, 그 구동방법 및그 제조방법
US6919251B2 (en) * 2002-07-31 2005-07-19 Texas Instruments Incorporated Gate dielectric and method
US6900098B1 (en) * 2002-10-15 2005-05-31 Halo Lsi, Inc. Twin insulator charge storage device operation and its fabrication method
US7382659B2 (en) * 2002-10-15 2008-06-03 Halo Lsi, Inc. Twin insulator charge storage device operation and its fabrication method
US7391653B2 (en) 2002-10-15 2008-06-24 Halo Lsi, Inc. Twin insulator charge storage device operation and its fabrication method
JP4040534B2 (ja) * 2003-06-04 2008-01-30 株式会社東芝 半導体記憶装置
US6878991B1 (en) * 2004-01-30 2005-04-12 Micron Technology, Inc. Vertical device 4F2 EEPROM memory
JP5001578B2 (ja) * 2005-06-30 2012-08-15 ラピスセミコンダクタ株式会社 半導体記憶装置及び半導体記憶装置の製造方法
US7569086B2 (en) * 2006-04-24 2009-08-04 Thermochem Recovery International, Inc. Fluid bed reactor having vertically spaced apart clusters of heating conduits
JP4965948B2 (ja) * 2006-09-21 2012-07-04 ルネサスエレクトロニクス株式会社 半導体装置
US9391084B2 (en) 2014-06-19 2016-07-12 Macronix International Co., Ltd. Bandgap-engineered memory with multiple charge trapping layers storing charge

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JPH02126498A (ja) * 1988-07-08 1990-05-15 Hitachi Ltd 不揮発性半導体記憶装置
US4953928A (en) * 1989-06-09 1990-09-04 Synaptics Inc. MOS device for long-term learning
US5436481A (en) * 1993-01-21 1995-07-25 Nippon Steel Corporation MOS-type semiconductor device and method of making the same
US5666307A (en) * 1995-11-14 1997-09-09 Programmable Microelectronics Corporation PMOS flash memory cell capable of multi-level threshold voltage storage
EP0843360A1 (fr) * 1996-11-15 1998-05-20 Hitachi Europe Limited Dispositif de mémoire

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Also Published As

Publication number Publication date
WO1998006140A1 (fr) 1998-02-12
US6040995A (en) 2000-03-21
JP2000515328A (ja) 2000-11-14
KR20000029664A (ko) 2000-05-25
TW355796B (en) 1999-04-11

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