EP0902954A1 - Condensateur multicouche a film mince - Google Patents

Condensateur multicouche a film mince

Info

Publication number
EP0902954A1
EP0902954A1 EP97925839A EP97925839A EP0902954A1 EP 0902954 A1 EP0902954 A1 EP 0902954A1 EP 97925839 A EP97925839 A EP 97925839A EP 97925839 A EP97925839 A EP 97925839A EP 0902954 A1 EP0902954 A1 EP 0902954A1
Authority
EP
European Patent Office
Prior art keywords
layer
electrode
layers
capacitor
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP97925839A
Other languages
German (de)
English (en)
Inventor
Rainer Bruchhaus
Dana Pitzer
Robert Primig
Wolfram Wersing
Wolfgang HÖNLEIN
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0902954A1 publication Critical patent/EP0902954A1/fr
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H01G4/306—Stacked capacitors made by thin film techniques

Definitions

  • Known multilayer capacitors are ceramic components in which electrode layers and thin ceramic layers are alternately arranged one above the other. One ceramic layer each with the two adjacent electrode layers forms an individual capacitor. The individual capacitors are electrically connected in parallel by appropriate contacting of the electrode layers.
  • "wet" processes are used, for example green films being produced with the aid of a slip or a sol-gel process and then printed with electrode material. Stacking such printed green films and sintering together results in compact components obtained, which are provided with electrical connections in a last process step.
  • the number of individual capacitors that is to say the number of layers of the multilayer capacitor, can be increased.
  • Multilayer capacitors with a high capacitance in the range of a few ⁇ F can, however, only be realized in this way with a high manufacturing outlay.
  • electrolytic capacitors can be realized with such high capacities in the range of a few ⁇ F, but often have unsatisfactory electrical properties.
  • electrolytic capacitors can be improved with regard to the frequency response, the switching current behavior (internal resistance), the leakage current and the temperature range in which they can be used.
  • this object is achieved by a multilayer capacitor according to claim 1.
  • Preferred embodiments of the invention and a method for producing the multilayer capacitor can be found in further claims.
  • the multilayer capacitor comprises a multilayer structure arranged on a substrate, in which electrode layers and dielectric layers are alternately arranged one above the other as a thin layer.
  • the electrode layers are alternately connected to a first and a second contact layer, each of which is arranged laterally along the layer structure and approximately vertically to the layer planes.
  • the number n of dielectric layers is chosen to be greater than 1 and less than 100. It is preferably 5 to 20 layers.
  • the ceramic dielectric layers which are applied using conventional thin-film processes, have a maximum layer thickness of approximately 1 ⁇ m. Compared to known wet-ceramic multilayer capacitors, the dielectric layers of which can be reduced to about 5 ⁇ m in the best case, this means at least a reduction in the layer thickness by a factor of 5. However, with known thin-layer processes, thin layers are already used today of up to 0.1 ⁇ m can be reached reliably and reproducibly, the invention reduces the layer thickness by up to Factor of 50 possible.
  • the invention allows the specific capacitance to be increased by up to a factor of 2500 compared to the best known multilayer capacitors.
  • the invention therefore saves material compared to known ceramic multilayer capacitors and, compared to all other known capacitors, achieves a considerably flatter design and a significantly smaller space requirement with at least constant capacitance.
  • the electrode layers are alternately formed from two different electrode materials, which also have a different oxidation potential.
  • This structure is particularly favorable for the production method of the multilayer capacitor, which is also according to the invention, since it avoids complex photolithographic steps for structuring or contacting the electrode layers with the first and second contact layers.
  • the dielectric layers of the multilayer capacitor are formed from at least two different dielectric materials.
  • the temperature behavior or the temperature characteristic of the electrical values of the multilayer capacitor the so-called temperature response of the capacitor, can be set. Since the temperature behavior, in addition to the absolute level of the capacitor capacitance, is of great importance for the usability of the multilayer capacitor as a component in electrical and electronic circuits, the invention opens up a wide field of application for multilayer capacitors according to the invention dielectric layers to produce a material that would result in poor temperature characteristics in a single-layer capacitor.
  • the only decisive factor is the temperature characteristic of the entire multilayer capacitor, which is obtained as a mean value in the parallel connection of single-layer capacitors in the layer structure according to the invention.
  • a suitable combination can be used to put together a temperature behavior with minimal changes in the electrical values in the multilayer capacitor from individual dielectric layers which have a large change in their electrical values in a given temperature range.
  • the dielectric layers are paraelectric layers, that is to say they include ferroelectric materials.
  • the particularly unfavorable temperature behavior of individual ferroelectric or para-electric layers in 1-layer capacitors is particularly advantageously compensated for in the multilayer capacitor according to the invention as just described.
  • Ferroelectric layers show a transition from ferroelectric to paraelectric behavior at the Curie temperature. In a capacitor, this causes an extreme change in the electrical properties at the Curie temperature.
  • a suitable layer structure therefore has a plurality of ferroelectric materials whose Curie temperatures are evenly distributed over the desired temperature range desired for an application.
  • the thin-film processes with which the ferroelectric or dielectric layers of the multilayer capacitor are produced allow a simple variation of the composition in the components which are decisive for the properties.
  • the composition of the growing dielectric can be changed by exchanging the targets, by covering target surfaces or more elegantly by changing the power on the targets. see or ferroelectric layers can be varied from layer to layer in a simple manner.
  • suitable dielectric layers are all dielectric materials which can be produced using thin-film processes and whose dielectric properties result in the desired overall properties on the basis of known laws and dependencies in the multilayer capacitor.
  • the dielectric strength at the given layer thickness compared to a desired threshold voltage is of particular importance.
  • Corresponding materials are already used in conventional ceramic multilayer capacitors.
  • Capacitor would be unsuitable per se, but could serve to round off its properties in the multilayer capacitor according to the invention.
  • the electrode layers comprise electrode materials which survive the relatively high process temperatures up to approximately 600 ° C without damage. Suitable materials are, for example, platinum, iridium, ruthenium, RuO 2, SrRuC> 3 or (LaSr) CoC> 3.
  • the electrode layers are also produced using thin-film processes such as CVD or sputtering. Electron beam evaporation is also suitable. Pairs with different oxidation potentials, such as are required in the manufacturing process according to the invention, can be put together from the specified electrode materials.
  • the electrode materials consisting of ceramic compounds have the advantage that the oxidation potential can be adjusted particularly easily by varying the composition.
  • Figure 1 shows a usable substrate in plan view
  • Figure 2 shows a layer structure in cross section
  • FIGS. 3 to 9 show different process stages in the manufacture of the electrical circuit according to the invention.
  • FIG. 10 shows temperature responses for various ceramic compositions
  • Figure 11 shows the temperature response of a multilayer capacitor according to the invention.
  • General principle for the production of a multilayer capacitor :
  • FIGS 1 and 2 An inexpensive substrate is preferably used, for example Al2O3, silicon or glass. Metallic substrates are also possible.
  • the substrate 1 is coated with a conventional adhesion promoter layer 6, which ensures both a homogeneous growth of the first electrode layer E1 and good adhesion thereof.
  • a known adhesion promoter layer for glass is, for example, titanium oxide TiO 2.
  • the multilayer capacitor is preferably produced on a large-area substrate 1 which, in order to support the subsequent division into the individual capacitors of the desired base area, already has a trench pattern made of grooves or furrows.
  • a pattern of horizontal trenches 2 and vertical trenches 4 is shown by way of example in FIG. 1, which divide the substrate surface into rows 3 and columns 5.
  • Substrates are preferably used
  • Standard formats are used, for example in the 8 '' format, which are well suited for conventional thin-film deposition devices.
  • FIG. 2 already shows the complete layer structure using a schematic cross section (see line F2 in FIG. 1) through the substrate 1 parallel to the horizontal trenches 2.
  • a layer structure is shown with a first electrode layer E1 made of an electrode material with a first oxidation potential.
  • This first electrode layer E1 is preferably formed from such an electrode material which exhibits good adhesion to the substrate 1 or to the adhesion promoter layer 6 and can also be deposited homogeneously and with as flat and smooth a surface as possible.
  • a well-suited material for the first electrode layer E1 is, for example, platinum.
  • a first dielectric layer D1 was deposited thereover, for example likewise using a thin-film method.
  • the second electrode layer E'2 made of a second electrode material which has a second oxidation potential which is lower than the oxidation potential of the first electrode layer E1.
  • Well-suited combinations with the first Pt electrode E1 form, for example, IR or (LaSr) C0O3.
  • ⁇ S more layers followed by a second dielectric layer D2, which consists of the same material as the first dielectric layer Dl or under ⁇ thereof is different.
  • a third electrode layer E3 is produced, which again consists of the first electrode material with the first oxidation potential.
  • dielectric layers D and electrode layers E and E ' are arranged one above the other in a correspondingly alternating sequence.
  • the upper limit for the number n of the dielectric layers is, on the one hand, the possibly decreasing homogeneity and, on the other hand, the increased process outlay, which is not least reflected in the costs.
  • the final layer on the layer structure is a protective layer 7, which in the exemplary embodiment consists of a dielectric material.
  • the substrates 1 with the layer structure applied over them are divided along the horizontal trenches 2 into capacitor rows 3.
  • Ion beam etching can be used as the removal method to separate the layer structure.
  • the substrate however, can be sawn or broken along the vertical trenches 4.
  • FIG. 3 shows a further schematic cross section through the layer structure.
  • the surface facing upwards in the figure represents a side surface of the layer structure from FIG. 2.
  • FIG. 4a shows the layer structure after the etching step, in which a depression 8 is formed in the side surface by removing part of the electrode E'2.
  • the side surface can be treated in an electrolyte containing additional metal ions (e.g. electrode material with a higher oxidation potential).
  • additional metal ions e.g. electrode material with a higher oxidation potential.
  • the electrode material with the lower oxidation potential goes into solution, while a metal deposition 9 takes place over the electrode material with the higher oxidation potential.
  • Figure 4b shows the arrangement after this step.
  • the depression 8 is filled with insulation material in order to isolate the etched-on electrode layers E'2 from the subsequent electrical contact.
  • an insulation layer is preferably applied to the entire surface of the side surface
  • Figures 5a and 5b show the arrangement after this step.
  • the electrode layers E1 and E3 with the higher oxidation potential are exposed.
  • the electrode layer E'2 with the lower oxidation potential is now in the recess 8 with a strip
  • a first contact layer 12 is now applied to the surface.
  • This can comprise an adhesion promoter layer consisting of chromium and / or nickel, a sputtered diffuser barrier layer made of platinum and also such further electrode layers (for example made of gold) which enable connection by soldering.
  • a part of the electrode material is detached from the electrode layers E1 and E3 on the side surface opposite the contact layer 12. This is done in a simple manner by anodically supported electrochemical etching, in which the contact layer 12 is connected to the anode in an electrolytic etching bath.
  • Figure 8 shows the arrangement after the electrolytic etching.
  • these depressions 13 are now also filled with insulation material 14, the surface of the electrode layer E'2 is exposed by chemical mechanical polishing and electrically connected to a second contact layer 15 deposited thereover.
  • the method steps described with reference to FIGS. 3 to 9 can advantageously be carried out simultaneously for several capacitor rows 3.
  • several rows of capacitors are preferably stacked on top of one another in such a way that all side surfaces of the rows of capacitors form a common surface.
  • the capacitor rows 3 are divided by dividing them along the trenches 4 into the individual multilayer capacitors with the desired base area.
  • the composition that is to say by varying the parameters u or x, several different dielectric layers D1 to Dn are realized in the layer structure.
  • FIG. 10 uses the BST system (Ba ⁇ _ u Sr u ) Ti ⁇ 3 to show how the temperature response of the value ⁇ r can be changed by varying the parameter u over a temperature range of over 160 ° C. Representative are seven measurement curves for different parameters u, the maxima of which are evenly distributed over the temperature range shown from - 50 to + 110 ° C. The figure is only intended to show an example that a uniform distribution of the maxima is possible.
  • Suitable compositions for the desired standard X7R can also be achieved with BST compositions with a different barium / strontium ratio or other material systems.
  • BST compositions with a different barium / strontium ratio or other material systems For fine tuning, it is also possible to use different compositions or material systems in the multilayer capacitor, although several layers can also have the same composition.
  • the critical temperature range of an individual dielectric layer D is the range in which the greatest relative changes in properties occur. In the case of ferroelectric layers, this critical range is a sharply defined temperature range around the Curie Temperature, in contrast, a relatively broad range around the point of the ferroelectric phase transition in the case of relaxor systems.
  • the temperature behavior of the complete multilayer capacitor results to a certain extent as an average or by superimposing the corresponding temperature profiles of the individual dielectric layers and can thus be adjusted to the desired specifications for X7R.
  • FIG. 11 shows the temperature response of a multilayer capacitor according to the invention, which fulfills the X7R standard.
  • the measurement curve for the temperature response still has the maxima which correspond to the maxima of the measurement curves for the individual layers, only a slight deviation from the mean is observed overall, as is required by the standard.
  • the relative capacitance changes ⁇ C / C of the multilayer capacitor may reach values of ⁇ 15 percent between -55 ° and + 125 ° C.
  • a multilayer capacitor with the temperature response Y5V can be produced in a simple manner from relaxer materials, it being possible for all the dielectric layers D to consist of the same relaxer material. It can do that in the previous
  • the dielectric layers D can also be produced from different relaxation materials, in order to replace a Y5V characteristic of the above-mentioned system PMN-PT with a Z5V
  • ⁇ C / C of the multilayer capacitor may not exceed +22% / - 82% for Y5V in the interval from - 30 ° to + 85 ° C, and for Z5V in the interval of + 10 ° to 85 ° C + 22% / -56%.
  • the temperature response COG can be realized according to the invention with a multilayer capacitor, the layer structure of which essentially comprises dielectric layers D with low permittivity ⁇ r .
  • these are non-ferroelectric materials.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

L'invention a pour objet un condensateur multicouche du type à couches minces, de capacité accrue et/ou d'encombrement réduit, dont les couches diélectriques sont disposées en alternance entre des couches d'électrodes sur un substrat. En réalisant une liaison, également en alternance, des couches d'électrodes, on obtient un montage en parallèle des couches individuelles du condensateur. De cette façon, les capacités individuelles s'additionnent, cependant que le comportement à la température peut être optimisé en sélectionnant ou combinant de façon appropriée les différentes couches diélectriques.
EP97925839A 1996-05-21 1997-05-05 Condensateur multicouche a film mince Ceased EP0902954A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19620434 1996-05-21
DE19620434 1996-05-21
PCT/DE1997/000914 WO1997044797A1 (fr) 1996-05-21 1997-05-05 Condensateur multicouche a film mince

Publications (1)

Publication Number Publication Date
EP0902954A1 true EP0902954A1 (fr) 1999-03-24

Family

ID=7794899

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97925839A Ceased EP0902954A1 (fr) 1996-05-21 1997-05-05 Condensateur multicouche a film mince

Country Status (8)

Country Link
US (1) US6108191A (fr)
EP (1) EP0902954A1 (fr)
JP (1) JP3226548B2 (fr)
KR (1) KR20000015822A (fr)
CN (1) CN1219277A (fr)
BR (1) BR9709333A (fr)
UA (1) UA41477C2 (fr)
WO (1) WO1997044797A1 (fr)

Families Citing this family (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7005695B1 (en) * 2000-02-23 2006-02-28 Micron Technology, Inc. Integrated circuitry including a capacitor with an amorphous and a crystalline high K capacitor dielectric region
DE50104838D1 (de) 2000-03-13 2005-01-20 Siemens Ag Keramikmasse, verfahren zur herstellung der keramikmasse und verwendung der keramikmasse
US7164329B2 (en) 2001-04-11 2007-01-16 Kyocera Wireless Corp. Tunable phase shifer with a control signal generator responsive to DC offset in a mixed signal
US7221243B2 (en) * 2001-04-11 2007-05-22 Kyocera Wireless Corp. Apparatus and method for combining electrical signals
US7394430B2 (en) * 2001-04-11 2008-07-01 Kyocera Wireless Corp. Wireless device reconfigurable radiation desensitivity bracket systems and methods
US7746292B2 (en) 2001-04-11 2010-06-29 Kyocera Wireless Corp. Reconfigurable radiation desensitivity bracket systems and methods
US6690251B2 (en) * 2001-04-11 2004-02-10 Kyocera Wireless Corporation Tunable ferro-electric filter
US7174147B2 (en) * 2001-04-11 2007-02-06 Kyocera Wireless Corp. Bandpass filter with tunable resonator
US7154440B2 (en) * 2001-04-11 2006-12-26 Kyocera Wireless Corp. Phase array antenna using a constant-gain phase shifter
US7071776B2 (en) 2001-10-22 2006-07-04 Kyocera Wireless Corp. Systems and methods for controlling output power in a communication device
US7184727B2 (en) * 2002-02-12 2007-02-27 Kyocera Wireless Corp. Full-duplex antenna system and method
US7180467B2 (en) * 2002-02-12 2007-02-20 Kyocera Wireless Corp. System and method for dual-band antenna matching
US7176845B2 (en) * 2002-02-12 2007-02-13 Kyocera Wireless Corp. System and method for impedance matching an antenna to sub-bands in a communication band
US6898070B2 (en) * 2002-12-19 2005-05-24 Avx Corporation Transmission line capacitor
US20060115672A1 (en) * 2003-02-20 2006-06-01 N.V. Bekaert S.A. Method of manufacturing a laminated structure
US7720443B2 (en) 2003-06-02 2010-05-18 Kyocera Wireless Corp. System and method for filtering time division multiple access telephone communications
US7125781B2 (en) 2003-09-04 2006-10-24 Micron Technology, Inc. Methods of forming capacitor devices
US7067385B2 (en) * 2003-09-04 2006-06-27 Micron Technology, Inc. Support for vertically oriented capacitors during the formation of a semiconductor device
US20060001068A1 (en) * 2004-06-30 2006-01-05 Mosley Larry E Multi-layer capacitor using dielectric layers having differing compositions
US7387939B2 (en) * 2004-07-19 2008-06-17 Micron Technology, Inc. Methods of forming semiconductor structures and capacitor devices
US7202127B2 (en) * 2004-08-27 2007-04-10 Micron Technology, Inc. Methods of forming a plurality of capacitors
US7439152B2 (en) * 2004-08-27 2008-10-21 Micron Technology, Inc. Methods of forming a plurality of capacitors
US20060046055A1 (en) * 2004-08-30 2006-03-02 Nan Ya Plastics Corporation Superfine fiber containing grey dope dyed component and the fabric made of the same
US7547945B2 (en) 2004-09-01 2009-06-16 Micron Technology, Inc. Transistor devices, transistor structures and semiconductor constructions
US7320911B2 (en) * 2004-12-06 2008-01-22 Micron Technology, Inc. Methods of forming pluralities of capacitors
US7557015B2 (en) 2005-03-18 2009-07-07 Micron Technology, Inc. Methods of forming pluralities of capacitors
JP2006278566A (ja) * 2005-03-28 2006-10-12 Tdk Corp 積層電子部品及びその製造方法
US7544563B2 (en) * 2005-05-18 2009-06-09 Micron Technology, Inc. Methods of forming a plurality of capacitors
US7517753B2 (en) * 2005-05-18 2009-04-14 Micron Technology, Inc. Methods of forming pluralities of capacitors
US7282401B2 (en) 2005-07-08 2007-10-16 Micron Technology, Inc. Method and apparatus for a self-aligned recessed access device (RAD) transistor gate
US7199005B2 (en) * 2005-08-02 2007-04-03 Micron Technology, Inc. Methods of forming pluralities of capacitors
US7867851B2 (en) 2005-08-30 2011-01-11 Micron Technology, Inc. Methods of forming field effect transistors on substrates
US7548762B2 (en) * 2005-11-30 2009-06-16 Kyocera Corporation Method for tuning a GPS antenna matching network
US7700441B2 (en) 2006-02-02 2010-04-20 Micron Technology, Inc. Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates
US7557013B2 (en) * 2006-04-10 2009-07-07 Micron Technology, Inc. Methods of forming a plurality of capacitors
US7602001B2 (en) 2006-07-17 2009-10-13 Micron Technology, Inc. Capacitorless one transistor DRAM cell, integrated circuitry comprising an array of capacitorless one transistor DRAM cells, and method of forming lines of capacitorless one transistor DRAM cells
US7772632B2 (en) 2006-08-21 2010-08-10 Micron Technology, Inc. Memory arrays and methods of fabricating memory arrays
US7589995B2 (en) 2006-09-07 2009-09-15 Micron Technology, Inc. One-transistor memory cell with bias gate
US7902081B2 (en) * 2006-10-11 2011-03-08 Micron Technology, Inc. Methods of etching polysilicon and methods of forming pluralities of capacitors
US7785962B2 (en) * 2007-02-26 2010-08-31 Micron Technology, Inc. Methods of forming a plurality of capacitors
US7772879B1 (en) * 2007-04-11 2010-08-10 Actel Corporation Logic module including versatile adder for FPGA
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US7682924B2 (en) * 2007-08-13 2010-03-23 Micron Technology, Inc. Methods of forming a plurality of capacitors
US7663400B1 (en) * 2007-12-21 2010-02-16 Actel Corporation Flexible carry scheme for field programmable gate arrays
US8388851B2 (en) 2008-01-08 2013-03-05 Micron Technology, Inc. Capacitor forming methods
US8244791B1 (en) 2008-01-30 2012-08-14 Actel Corporation Fast carry lookahead circuits
US9324071B2 (en) 2008-03-20 2016-04-26 Visa U.S.A. Inc. Powering financial transaction token with onboard power source
US8274777B2 (en) 2008-04-08 2012-09-25 Micron Technology, Inc. High aspect ratio openings
JP2009295683A (ja) * 2008-06-03 2009-12-17 Tdk Corp チップ型電子部品
US7759193B2 (en) 2008-07-09 2010-07-20 Micron Technology, Inc. Methods of forming a plurality of capacitors
US8518788B2 (en) 2010-08-11 2013-08-27 Micron Technology, Inc. Methods of forming a plurality of capacitors
JP5766011B2 (ja) * 2011-05-06 2015-08-19 京セラ株式会社 静電容量素子
US10601074B2 (en) 2011-06-29 2020-03-24 Space Charge, LLC Rugged, gel-free, lithium-free, high energy density solid-state electrochemical energy storage devices
US9853325B2 (en) * 2011-06-29 2017-12-26 Space Charge, LLC Rugged, gel-free, lithium-free, high energy density solid-state electrochemical energy storage devices
US11527774B2 (en) 2011-06-29 2022-12-13 Space Charge, LLC Electrochemical energy storage devices
US9076680B2 (en) 2011-10-18 2015-07-07 Micron Technology, Inc. Integrated circuitry, methods of forming capacitors, and methods of forming integrated circuitry comprising an array of capacitors and circuitry peripheral to the array
US8946043B2 (en) 2011-12-21 2015-02-03 Micron Technology, Inc. Methods of forming capacitors
CN103319167A (zh) * 2012-03-22 2013-09-25 禾伸堂企业股份有限公司 介电陶瓷材料及其所制成的积层陶瓷电容
US8652926B1 (en) 2012-07-26 2014-02-18 Micron Technology, Inc. Methods of forming capacitors
CN103208415B (zh) * 2013-03-22 2016-08-24 上海华虹宏力半导体制造有限公司 电容及其形成方法
JP2017120853A (ja) * 2015-12-28 2017-07-06 Tdk株式会社 セラミック電子部品
EP3762989A4 (fr) 2018-03-07 2021-12-15 Space Charge, LLC Dispositifs d'accumulation d'énergie à électrolyte solide à film mince
CN111223669B (zh) * 2020-01-10 2021-08-03 河南理工大学 一种高储能密度的固态电介质薄膜电容器及其制备方法
US20220122771A1 (en) * 2020-10-19 2022-04-21 Imagine Tf, Llc Layered capacitor with two different types of electrode material

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3210607A (en) * 1961-09-07 1965-10-05 Texas Instruments Inc Ferroelectric capacitor apparatus
US4219866A (en) * 1979-01-12 1980-08-26 Sprague Electric Company Ceramic capacitor having a dielectric of (Pb,La) (Zr,Ti)O3 and BaTiO3
DE3442790A1 (de) * 1984-11-23 1986-06-05 Dieter Prof. Dr. Linz Bäuerle Verfahren zur herstellung von duennschichtkondensatoren
FR2617631A1 (fr) * 1987-06-30 1989-01-06 Thomson Csf Condensateur multicouche a base de polymere ferroelectrique
JPH0666219B2 (ja) * 1989-02-22 1994-08-24 株式会社村田製作所 積層セラミックスコンデンサ
JP2800017B2 (ja) * 1989-04-05 1998-09-21 株式会社村田製作所 積層セラミックスコンデンサ
JPH0650701B2 (ja) * 1989-05-18 1994-06-29 松下電器産業株式会社 積層コンデンサ素子とその製造方法
DE4300808C1 (de) * 1993-01-14 1994-03-17 Siemens Ag Verfahren zur Herstellung eines Vielschichtkondensators
DE69401826T2 (de) * 1993-03-25 1997-06-12 Matsushita Electric Ind Co Ltd Dünnschichtkondensator und Verfahren zu seiner Herstellung
JPH07142288A (ja) * 1993-11-18 1995-06-02 Asahi Glass Co Ltd 積層薄膜コンデンサの製造方法
JPH07161223A (ja) * 1993-12-10 1995-06-23 Murata Mfg Co Ltd 導電性ペーストおよび積層セラミックコンデンサ
GB9401226D0 (en) * 1994-01-22 1994-03-16 Oxley Dev Co Ltd Fabrication of capacitors and electrostrictive devices
JP3498190B2 (ja) * 1994-06-06 2004-02-16 株式会社村田製作所 薄膜積層電極の製造方法
WO1996013046A1 (fr) * 1994-10-19 1996-05-02 Tdk Corporation Condensateur pastille en ceramique multicouche
JPH10139536A (ja) * 1996-11-12 1998-05-26 Murata Mfg Co Ltd 誘電体磁器組成物

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9744797A1 *

Also Published As

Publication number Publication date
WO1997044797A1 (fr) 1997-11-27
CN1219277A (zh) 1999-06-09
KR20000015822A (ko) 2000-03-15
UA41477C2 (uk) 2001-09-17
JPH11511906A (ja) 1999-10-12
US6108191A (en) 2000-08-22
BR9709333A (pt) 1999-08-10
JP3226548B2 (ja) 2001-11-05

Similar Documents

Publication Publication Date Title
WO1997044797A1 (fr) Condensateur multicouche a film mince
DE69633367T2 (de) Verfahren zur Herstellung eines in einer Halbleitervorrichtung integrierten Kondensators
EP0043001B1 (fr) Jauge d'humidité et procédé pour sa fabrication
DE19902029A1 (de) Spannungsfester Dünnschichtkondensator mit Interdigitalstruktur
DE19903572A1 (de) Monolithischer Kondensator
WO2003030187A2 (fr) Composant electroceramique comportant plusieurs surfaces de contact
EP2517218B1 (fr) Varactor et sa methode de fabrication
DE19649670C2 (de) Verfahren zur Herstellung eines Kondensators einer Halbleitervorrichtung und auf diese Weise hergestellter Kondensator
DE19903500A1 (de) Dünnschichtschaltkreis mit Bauteil
DE19915247A1 (de) Spannungsabhängiger Dünnschichtkondensator
DE10040414B4 (de) Dielelektrisches Keramikmaterial und elektrisches Bauelement
EP1048082A1 (fr) Circuiterie comprenant au moins un condensateur, et production
DE19901540A1 (de) Verfahren zur Feinabstimmung eines passiven, elektronischen Bauelementes
DE10161286A1 (de) Integriertes Halbleiterprodukt mit Metall-Isolator-Metall-Kondensator
WO2001018830A1 (fr) Condensateur en couche mince
DE19825266B4 (de) Verfahren zur Herstellung eines Kondensators für eine Halbleitereinrichtung
DE19640218C2 (de) Integrierte Halbleiterspeicheranordnung mit Speicherkondensatoren
DE19620833A1 (de) Verfahren zur Herstellung eines Kondensators einer Halbleitereinrichtung
WO2000049648A1 (fr) Condensateur multicouche en ceramique a couches minces
DE10103529B4 (de) Ferroelektrischer Kondensator, Verfahren zur Herstellung und Verwendung des Kondensators
EP1527659A1 (fr) Procede de production de structures conductrices electriques pouvant etre utilisees dans le domaine de la technologie haute frequence
EP4182959A1 (fr) Condensateur multicouche
DE102018213050A1 (de) Spannungskontrollierbarer Kondensator und Verfahren zum Herstellen eines spannungskontrollierbaren Kondensators
DE102018213051A1 (de) Spannungskontrollierbarer Kondensator mit ferroelektrischer Schicht und Verfahren zum Herstellen des spannungskontrollierbaren Kondensators mit ferroelektrischer Schicht
DE4410753A1 (de) Kondensator-Array

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19981105

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT CH DE ES FR GB IT LI

17Q First examination report despatched

Effective date: 19990510

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: INFINEON TECHNOLOGIES AG

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN REFUSED

18R Application refused

Effective date: 20020809