Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
  • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
  • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
  • H10D84/85—Complementary IGFETs, e.g. CMOS
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
  • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
  • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
  • H10D84/85—Complementary IGFETs, e.g. CMOS
  • H10D84/858—Complementary IGFETs, e.g. CMOS comprising a P-type well but not an N-type well

Definitions

• the present invention relates to a CMOS arrangement according to the preamble of claim 1, i.e. a CMOS arrangement which has at least one NMOS region and at least one PMOS region and which is provided on its surface with substrate contacts, via which respective substrate sections of the CMOS arrangement can be subjected to predetermined voltage values.
• CMOS arrangements have long been known and are used on a large scale.
• a practical embodiment of such an arrangement is shown in FIG. 2.
• Figure 2 is a schematic cross-sectional view of a conventional CMOS device.
• the CMOS arrangement shown has a p " substrate 1, in which an NMOS region 2 and a PMOS region 3 are formed.
• An NMOS transistor 21 is formed in the NMOS region 2, the source section 22 and the drain section 23 thereof being formed as n + regions provided within the p " substrate 1.
• an n ⁇ substrate 30 embedded in the form of a trough is provided within the p ⁇ substrate 1.
• a PMOS transistor 31 is formed in this PMOS region 3, the source section 32 and the drain section 33 thereof being formed as p + regions provided within the n " substrate 30.
• the gate sections as well as the mode of operation and the function of the respective transistors are guides are not of interest - they are therefore not illustrated in FIG. 2 nor are they explained in more detail in the description.
• the starting point for the further considerations is the pnpn zone sequence in the CMOS arrangement shown in FIG. 2, which is determined by the sequence of (1) source and drain sections 32 and 33 of the PMOS transistor 31, (2) n ⁇ - substrate 30 of the PMOS transistor 31, (3) p " substrate 1 of the CMOS arrangement or de ⁇ NMOS transistor 21 and (4) source or drain section 22 or 23 of the NMOS transistor 21 gebil ⁇ det.
• the pnpn zone sequence mentioned is the zone sequence of a thyristor.
• zone (2) and zone (3) ie the junction between the n " substrate 30 of the PMOS transistor 31 and the p ⁇ substrate 1 of the CMOS arrangement or the NMOS transistor 21 is blocking the thyristor is also blocked, and its presence does not affect the function of the respective transistors.
• zones (1) and (4) i.e. the source or drain section 32 or 33 of the PMOS transistor 31 and the source or drain section 22 or 23 of the NMOS transistor 21 are electrically connected to one another, which leads to malfunction or even destruction of the respective transistor ren leads.
• CMOS arrangements In order to avoid such undesirable thyristor effects in CMOS arrangements, i.e. In order to increase the so-called latch-up strength, the surface of the CMOS arrangement is covered with
• substrate contacts are realized in the NMOS area 2 as p * sections 24 connected to ground, and in the PMOS area 3 as n * sections 34 connected with a positive voltage. In this way, free movement of the charge carriers in question in the respective substrates, which make the pn junction conductive, is prevented, so that unintentional ignition of the thyristor is precluded.
• a typical maximum value for the distance between adjacent substrate contacts is approximately 50 ⁇ m, and a typical maximum value for the distance between the substrate contacts and the source and drain sections of the respective transistors is approximately 25 ⁇ m.
• CMOS arrangements are usually covered by a uniform grid of substrate contacts. Such a structure is illustrated in Figure 3.
• FIG. 3 illustrates the arrangement of the substrate contacts on the surface of a conventional CMOS arrangement.
• the substrate contacts identified by an * are evenly distributed over the entire CMOS arrangement, the distance between adjacent substrate contacts being substantially constant approximately 50 ⁇ m.
• the present invention is therefore based on the object of developing the CMOS arrangement in accordance with the preamble of patent claim 1 in such a way that it can be further miniaturized while maintaining its latch-up strength.
• the average number of substrate contacts per unit area and / or the average substrate contact area per unit area within at least one NMOS range is substantially less than within at least one PMOS range.
• FIG. 1 shows a schematic representation of a top view of a CMOS arrangement designed according to the invention for illustrating the arrangement of substrate contacts on the surface thereof
• FIG. 2 shows a schematic cross-sectional view of a conventional CMOS arrangement
• FIG. 3 shows a schematic representation of a top view of a conventional CMOS arrangement for illustrating the arrangement of the substrate contacts on the surface thereof.
• the CMOS arrangement shown in FIG. 1 has the same basic structure as the conventional CMOS arrangement illustrated in FIG. 2.
• it comprises at least one NMOS area 2 and at least one PMOS area 3, which can be constructed essentially as shown in FIG. 2 and which can adjoin one another as shown in FIG.
• substrate contacts are again provided on the connection side of the CMOS arrangement shown in plan view in FIG. 1.
• the number and arrangement of the substrate contacts is modified according to the invention in such a way that the average number of contacts Substrate contacts per unit area and / or the average substrate contact area per unit area within the at least one NMOS area is substantially less than within the at least one PMOS area.
• a possible embodiment of the measure according to the invention consists in that, as shown in FIG. at least one PMOS area 3 is provided with substrate contacts in a known manner as described at the beginning, while the NMOS area 2 is only provided with substrate contacts at the edge.
• the PMOS area 3 has substrate contacts 34 in the known density and size, i.e. with a mutual distance of, for example, approximately 50 ⁇ m; the reduction of the more usually provided number of substrate contacts and / or substrate contact area (sum of the areas of the individual substrate contacts) in the NMOS area makes it not necessary to simultaneously increase the number of substrate contacts and / or the substrate contact area within the PMOS area.
• a higher packing density of the electrical components can elements within the NMOS area can be provided, which leads to a considerable reduction in area of the arrangement.
• the area reduction was several ten percent.
• the provision of the measure according to the invention also enables a simpler and cheaper production of CMOS arrangements (fewer layout restrictions, fewer number of contact points to be connected or contacted, lower material consumption).

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• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
• Electrodes Of Semiconductors (AREA)

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• 1995
  • 1995-12-06 DE DE19545554A patent/DE19545554A1/de not_active Withdrawn
• 1996
  • 1996-11-18 CN CNB961997869A patent/CN1230903C/zh not_active Expired - Lifetime
  • 1996-11-18 RU RU98112593/28A patent/RU2170475C2/ru not_active IP Right Cessation
  • 1996-11-18 EP EP96945730A patent/EP0865669A2/de not_active Ceased
  • 1996-11-18 UA UA98062924A patent/UA56148C2/uk unknown
  • 1996-11-18 WO PCT/DE1996/002189 patent/WO1997021240A2/de not_active Ceased
  • 1996-11-18 US US09/091,152 patent/US6160295A/en not_active Expired - Lifetime
  • 1996-11-18 KR KR10-1998-0704162A patent/KR100415129B1/ko not_active Expired - Fee Related
  • 1996-11-18 JP JP52084597A patent/JP3357069B2/ja not_active Expired - Fee Related
  • 1996-12-02 IN IN2071CA1996 patent/IN190506B/en unknown

Non-Patent Citations (1)

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