EP0865669A2 - Cmos device - Google Patents

Cmos device

Info

Publication number
EP0865669A2
EP0865669A2 EP96945730A EP96945730A EP0865669A2 EP 0865669 A2 EP0865669 A2 EP 0865669A2 EP 96945730 A EP96945730 A EP 96945730A EP 96945730 A EP96945730 A EP 96945730A EP 0865669 A2 EP0865669 A2 EP 0865669A2
Authority
EP
European Patent Office
Prior art keywords
area
substrate
substrate contacts
nmos
cmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP96945730A
Other languages
German (de)
French (fr)
Inventor
Holger Sedlak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0865669A2 publication Critical patent/EP0865669A2/en
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0927—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising a P-well only in the substrate

Definitions

  • the present invention relates to a CMOS arrangement according to the preamble of claim 1, i.e. a CMOS arrangement which has at least one NMOS region and at least one PMOS region and which is provided on its surface with substrate contacts, via which respective substrate sections of the CMOS arrangement can be subjected to predetermined voltage values.
  • CMOS arrangements have long been known and are used on a large scale.
  • a practical embodiment of such an arrangement is shown in FIG. 2.
  • Figure 2 is a schematic cross-sectional view of a conventional CMOS device.
  • the CMOS arrangement shown has a p " substrate 1, in which an NMOS region 2 and a PMOS region 3 are formed.
  • An NMOS transistor 21 is formed in the NMOS region 2, the source section 22 and the drain section 23 thereof being formed as n + regions provided within the p " substrate 1.
  • an n ⁇ substrate 30 embedded in the form of a trough is provided within the p ⁇ substrate 1.
  • a PMOS transistor 31 is formed in this PMOS region 3, the source section 32 and the drain section 33 thereof being formed as p + regions provided within the n " substrate 30.
  • the gate sections as well as the mode of operation and the function of the respective transistors are guides are not of interest - they are therefore not illustrated in FIG. 2 nor are they explained in more detail in the description.
  • the starting point for the further considerations is the pnpn zone sequence in the CMOS arrangement shown in FIG. 2, which is determined by the sequence of (1) source and drain sections 32 and 33 of the PMOS transistor 31, (2) n ⁇ - substrate 30 of the PMOS transistor 31, (3) p " substrate 1 of the CMOS arrangement or de ⁇ NMOS transistor 21 and (4) source or drain section 22 or 23 of the NMOS transistor 21 gebil ⁇ det.
  • the pnpn zone sequence mentioned is the zone sequence of a thyristor.
  • zone (2) and zone (3) ie the junction between the n " substrate 30 of the PMOS transistor 31 and the p ⁇ substrate 1 of the CMOS arrangement or the NMOS transistor 21 is blocking the thyristor is also blocked, and its presence does not affect the function of the respective transistors.
  • zones (1) and (4) i.e. the source or drain section 32 or 33 of the PMOS transistor 31 and the source or drain section 22 or 23 of the NMOS transistor 21 are electrically connected to one another, which leads to malfunction or even destruction of the respective transistor ren leads.
  • CMOS arrangements In order to avoid such undesirable thyristor effects in CMOS arrangements, i.e. In order to increase the so-called latch-up strength, the surface of the CMOS arrangement is covered with
  • substrate contacts are realized in the NMOS area 2 as p * sections 24 connected to ground, and in the PMOS area 3 as n * sections 34 connected with a positive voltage. In this way, free movement of the charge carriers in question in the respective substrates, which make the pn junction conductive, is prevented, so that unintentional ignition of the thyristor is precluded.
  • a typical maximum value for the distance between adjacent substrate contacts is approximately 50 ⁇ m, and a typical maximum value for the distance between the substrate contacts and the source and drain sections of the respective transistors is approximately 25 ⁇ m.
  • CMOS arrangements are usually covered by a uniform grid of substrate contacts. Such a structure is illustrated in Figure 3.
  • FIG. 3 illustrates the arrangement of the substrate contacts on the surface of a conventional CMOS arrangement.
  • the substrate contacts identified by an * are evenly distributed over the entire CMOS arrangement, the distance between adjacent substrate contacts being substantially constant approximately 50 ⁇ m.
  • the present invention is therefore based on the object of developing the CMOS arrangement in accordance with the preamble of patent claim 1 in such a way that it can be further miniaturized while maintaining its latch-up strength.
  • the average number of substrate contacts per unit area and / or the average substrate contact area per unit area within at least one NMOS range is substantially less than within at least one PMOS range.
  • FIG. 1 shows a schematic representation of a top view of a CMOS arrangement designed according to the invention for illustrating the arrangement of substrate contacts on the surface thereof
  • FIG. 2 shows a schematic cross-sectional view of a conventional CMOS arrangement
  • FIG. 3 shows a schematic representation of a top view of a conventional CMOS arrangement for illustrating the arrangement of the substrate contacts on the surface thereof.
  • the CMOS arrangement shown in FIG. 1 has the same basic structure as the conventional CMOS arrangement illustrated in FIG. 2.
  • it comprises at least one NMOS area 2 and at least one PMOS area 3, which can be constructed essentially as shown in FIG. 2 and which can adjoin one another as shown in FIG.
  • substrate contacts are again provided on the connection side of the CMOS arrangement shown in plan view in FIG. 1.
  • the number and arrangement of the substrate contacts is modified according to the invention in such a way that the average number of contacts Substrate contacts per unit area and / or the average substrate contact area per unit area within the at least one NMOS area is substantially less than within the at least one PMOS area.
  • a possible embodiment of the measure according to the invention consists in that, as shown in FIG. at least one PMOS area 3 is provided with substrate contacts in a known manner as described at the beginning, while the NMOS area 2 is only provided with substrate contacts at the edge.
  • the PMOS area 3 has substrate contacts 34 in the known density and size, i.e. with a mutual distance of, for example, approximately 50 ⁇ m; the reduction of the more usually provided number of substrate contacts and / or substrate contact area (sum of the areas of the individual substrate contacts) in the NMOS area makes it not necessary to simultaneously increase the number of substrate contacts and / or the substrate contact area within the PMOS area.
  • a higher packing density of the electrical components can elements within the NMOS area can be provided, which leads to a considerable reduction in area of the arrangement.
  • the area reduction was several ten percent.
  • the provision of the measure according to the invention also enables a simpler and cheaper production of CMOS arrangements (fewer layout restrictions, fewer number of contact points to be connected or contacted, lower material consumption).

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

Described is a CMOS device with at least one NMOS zone (2) and at least one PMOS zone (3) and, located on its surface, contacts (24, 34) by means of which pre-determined voltages are applied to particular areas (1, 30) of the substrate of the device. The CMOS device described is characterized in that the average number of contacts (24, 34) per unit surface area and/or the average contact area per unit surface area within the at least one NMOS zone (2) is significantly lower than within the at least one PMOS zone (3).

Description

Beschreibungdescription
CMOS-AnordnungCMOS arrangement
Die vorliegende Erfindung betrifft eine CMOS-Anordnung gemäß dem Oberbegriff des Patentanspruchs 1, d.h. eine CMOS-Anord¬ nung, welche mindestens einen NMOS-Bereich und mindestenε ei¬ nen PMOS-Bereich aufweist, und welche an ihrer Oberfläche mit Substratkontakten versehen ist, über welche jeweilige Substratabschnitte der CMOS-Anordnung mit vorbestimmten Spannungswerten beaufschlagbar sind.The present invention relates to a CMOS arrangement according to the preamble of claim 1, i.e. a CMOS arrangement which has at least one NMOS region and at least one PMOS region and which is provided on its surface with substrate contacts, via which respective substrate sections of the CMOS arrangement can be subjected to predetermined voltage values.
Derartige CMOS-Anordnungen sind seit langem bekannt und wer¬ den in großem Umfang verwendet. Eine praktische Ausführungs- form einer derartigen Anordnung ist in Figur 2 gezeigt.Such CMOS arrangements have long been known and are used on a large scale. A practical embodiment of such an arrangement is shown in FIG. 2.
Die Figur 2 ist eine schematische Querschnittsansicht einer herkömmlichen CMOS-Anordnung.Figure 2 is a schematic cross-sectional view of a conventional CMOS device.
Die gezeigte CMOS-Anordnung weist ein p"-Substrat 1 auf, in dem ein NMOS-Bereich 2 und ein PMOS-Bereich 3 ausgebildet sind.The CMOS arrangement shown has a p " substrate 1, in which an NMOS region 2 and a PMOS region 3 are formed.
Im NMOS-Bereich 2 ist ein NMOS-Transistor 21 ausgebildet, dessen Sourceabschnitt 22 und dessen Drainabschnitt 23 als innerhalb des p"-Substrates l vorgesehene n+-Bereiche ausge¬ bildet sind.An NMOS transistor 21 is formed in the NMOS region 2, the source section 22 and the drain section 23 thereof being formed as n + regions provided within the p " substrate 1.
Zur Realisierung des PMOS-Bereiches 3 ist innerhalb des p~- Substrats l ein wannenartig eingebettetes n~-Substrat 30 vor¬ gesehen. In diesem PMOS-Bereich 3 ist ein PMOS-Transistor 31 ausgebildet, dessen Sourceabschnitt 32 und dessen Drainab¬ schnitt 33 als innerhalb des n"-Substrates 30 vorgesehene p+- Bereiche ausgebildet sind.In order to implement the PMOS region 3, an n ~ substrate 30 embedded in the form of a trough is provided within the p ~ substrate 1. A PMOS transistor 31 is formed in this PMOS region 3, the source section 32 and the drain section 33 thereof being formed as p + regions provided within the n " substrate 30.
Die Gateabschnitte sowie die Wirkungsweise und die Funktion der jeweiligen Transistoren sind für die nachfolgenden Aus- führungen nicht von Interesse,- sie sind daher weder in der Figur 2 veranschaulicht noch werden sie in der Beschreibung näher erläutert.The gate sections as well as the mode of operation and the function of the respective transistors are guides are not of interest - they are therefore not illustrated in FIG. 2 nor are they explained in more detail in the description.
Ausgangspunkt für die weiteren Betrachtungen ist vielmehr die pnpn-Zonenfolge in der in der Figur 2 gezeigten CMOS-Anord¬ nung, die durch die Aufeinanderfolge von (1) Source- bzw. Drainabschnitt 32 bzw. 33 des PMOS-Transistors 31, (2) n~- Substrat 30 des PMOS-Transistors 31, (3) p"-Substrat 1 der CMOS-Anordnung bzw. deε NMOS-Transistors 21 und (4) Source- bzw. Drainabschnitt 22 bzw. 23 des NMOS-Transistors 21 gebil¬ det wird.Rather, the starting point for the further considerations is the pnpn zone sequence in the CMOS arrangement shown in FIG. 2, which is determined by the sequence of (1) source and drain sections 32 and 33 of the PMOS transistor 31, (2) n ~ - substrate 30 of the PMOS transistor 31, (3) p " substrate 1 of the CMOS arrangement or deε NMOS transistor 21 and (4) source or drain section 22 or 23 of the NMOS transistor 21 gebil¬ det.
Die genannte pnpn-Zonenfolge ist die Zonenfolge eines Thyri- stors.The pnpn zone sequence mentioned is the zone sequence of a thyristor.
Solange der pn-Übergang zwischen Zone (2) und Zone (3), d.h. der Übergang zwischen dem n"-Substrat 30 des PMOS-Transistors 31 und dem p~-Substrat 1 der CMOS-Anordnung bzw. dem NMOS- Transistor 21 sperrend ist, ist auch der Thyristor gesperrt, und dessen Vorhandensein wirkt sich auf die Funktion der je¬ weiligen Transistoren nicht auε.As long as the pn junction between zone (2) and zone (3), ie the junction between the n " substrate 30 of the PMOS transistor 31 and the p ~ substrate 1 of the CMOS arrangement or the NMOS transistor 21 is blocking the thyristor is also blocked, and its presence does not affect the function of the respective transistors.
Wird dieser Übergang allerdings (infolge von in den jeweili- gen Substraten unerwünscht umherwandernden Ladungsträgern) leitend, so sind die Zonen (1) und (4), d.h. der Source- bzw. Drainabschnitt 32 bzw. 33 des PMOS-Transistors 31 und der Source- bzw. Drainabschnitt 22 bzw. 23 des NMOS-Transistors 21 elektrisch miteinander verbunden, was zu einer Fehlfunk- tion oder sogar zu einer Zerstörung der jeweiligen Transisto¬ ren führt.However, if this transition becomes conductive (as a result of charge carriers moving around undesirably in the respective substrates), zones (1) and (4), i.e. the source or drain section 32 or 33 of the PMOS transistor 31 and the source or drain section 22 or 23 of the NMOS transistor 21 are electrically connected to one another, which leads to malfunction or even destruction of the respective transistor ren leads.
Um derartige unerwünschte Thyristoreffekte in CMOS-Anordnun¬ gen zu vermeiden, d.h. um die sogenannte latch-up-Festigkeit zu erhöhen, wird die Oberfläche der CMOS-Anordnung mitIn order to avoid such undesirable thyristor effects in CMOS arrangements, i.e. In order to increase the so-called latch-up strength, the surface of the CMOS arrangement is covered with
Substratkontakten versehen. Diese Substratkontakte sind im NMOS-Bereich 2 als mit Masse verbundene p*-Abschnitte 24, und im PMOS-Bereich 3 als mit einer positiven Spannung verbundene n*-Abschnitte 34 reali¬ siert. Auf diese Weise wird ein freies Umherwandern von den in Rede stehenden pn-Übergang leitend machenden Ladungsträ¬ gern in den jeweiligen Substraten verhindert, so daß ein un¬ beabsichtigtes Zünden des Thyristors ausgeschlossen ist.Provide substrate contacts. These substrate contacts are realized in the NMOS area 2 as p * sections 24 connected to ground, and in the PMOS area 3 as n * sections 34 connected with a positive voltage. In this way, free movement of the charge carriers in question in the respective substrates, which make the pn junction conductive, is prevented, so that unintentional ignition of the thyristor is precluded.
Um diesen Effekt zuverlässig zu gewährleisten, müssen jedoch bestimmte Maximalabstände zwischen benachbarten Substratkon¬ takten und zwischen den Subεtratkontakten und den Source- und Drainabschnitten der jeweiligen Transistoren eingehalten wer¬ den. Ein typischer Maximalwert für den Abstand zwischen be¬ nachbarten Substratkontakten beträgt ca. 50 μm, und ein typi- scher Maximalwert für den Abstand zwischen den Substratkon¬ takten und den Source- und Drainabschnitten der jeweiligen Transistoren beträgt ca. 25 μm.In order to reliably ensure this effect, however, certain maximum distances between adjacent substrate contacts and between the substrate contacts and the source and drain sections of the respective transistors must be observed. A typical maximum value for the distance between adjacent substrate contacts is approximately 50 μm, and a typical maximum value for the distance between the substrate contacts and the source and drain sections of the respective transistors is approximately 25 μm.
Um diese Bedingungen zuverlässig einzuhalten, sind die be- kannten CMOS-Anordnungen in der Regel von einem gleichmäßigen Raster von Substratkontakten überzogen. Ein derartiger Aufbau ist in Figur 3 veranschaulicht.In order to reliably maintain these conditions, the known CMOS arrangements are usually covered by a uniform grid of substrate contacts. Such a structure is illustrated in Figure 3.
Die Figur 3 veranschaulicht die Anordnung der Substratkon- takte auf der Oberfläche einer herkömmlichen CMOS-Anordnung.FIG. 3 illustrates the arrangement of the substrate contacts on the surface of a conventional CMOS arrangement.
Die jeweils durch einen * gekennzeichneten Substratkontakte sind dabei über die gesamte CMOS-Anordnung gleichmäßig ver¬ teilt, wobei der Abstand zwischen benachbarten Substratkon- takten im wesentlichen konstant ca. 50 μm beträgt.The substrate contacts identified by an * are evenly distributed over the entire CMOS arrangement, the distance between adjacent substrate contacts being substantially constant approximately 50 μm.
Es liegt auf der Hand, daß daε Vorsehen derartiger Substrat¬ kontakte zu einer nicht unerheblichen Vergrößerung der CMOS- Anordnung führt bzw. einer weiteren Miniaturisierung dersel- ben Grenzen setzt. Der vorliegenden Erfindung liegt daher die Aufgabe zugrunde, die CMOS-Anordnung gemäß dem Oberbegriff deε Patentanεpruchε 1 derart weiterzubilden, daß diese unter Beibehaltung ihrer latch-up-Festigkeit weiter miniaturisierbar iεt.It is obvious that the provision of such substrate contacts leads to a not inconsiderable enlargement of the CMOS arrangement or sets a further miniaturization of the same limits. The present invention is therefore based on the object of developing the CMOS arrangement in accordance with the preamble of patent claim 1 in such a way that it can be further miniaturized while maintaining its latch-up strength.
Diese Aufgabe wird erfindungsgemäß durch daε im kennzeichnen¬ den Teil deε Patentanspruchs 1 beanspruchte Merkmal gelöst.This object is achieved by the feature claimed in the characterizing part of claim 1.
Demnach ist vorgesehen, daß die durchschnittliche Anzahl der Substratkontakte pro Flächeneinheit und/oder die durch¬ schnittliche Substratkontaktfläche pro Flächeneinheit inner¬ halb deε mindeεtens einen NMOS-Bereiches weεentlich geringer iεt alε innerhalb deε mindestenε einen PMOS-Bereieheε.Accordingly, it is provided that the average number of substrate contacts per unit area and / or the average substrate contact area per unit area within at least one NMOS range is substantially less than within at least one PMOS range.
Das Vorεehen dieεeε Merkmals bewirktThe provision of this feature brings about
(1) daß sich die Gesamtanzahl der auf einer CMOS-Anord¬ nung vorzusehenden Substratkontakte und/oder die von diesen benötigte Substratkontaktfläche verringern kann, und(1) that the total number of substrate contacts to be provided on a CMOS arrangement and / or the substrate contact area required by them can decrease, and
(2) daß die innerhalb der CMOS-Anordnung auεgebildeten elektroniεchen Bauelemente an den Stellen, an denen eine ge¬ ringe Anzahl von Subεtratkontakten pro Flächeneinheit und/oder eine geringe Subεtratkontaktfläche pro Flächenein¬ heit vorgesehen iεt, dichter gepackt werden können.(2) that the electronic components formed within the CMOS arrangement can be packed more tightly at the points at which a small number of substrate contacts per unit area and / or a small substrate contact area per unit area is provided.
Dieε erlaubt eε, eine gegebene, in CMOS-Technik aufzubauende Schaltung auf einer kleineren Fläche zu realisieren als dies bisher der Fall war.This allows a given circuit to be constructed using CMOS technology on a smaller area than was previously the case.
Untersuchungen haben ergeben, daß sich die latch-up-Festig- keit durch daε Vorεehen der erfindungεgemäßen Maßnahme nicht verschlechtert. Eε wurde mithin eine CMOS-Anordnung geschaf¬ fen, die unter Beibehaltung ihrer latch-up-Festigkeit weiter miniaturisierbar ist.Studies have shown that the latch-up strength does not deteriorate due to the provision of the measure according to the invention. A CMOS arrangement was therefore created, which can be further miniaturized while maintaining its latch-up strength.
Vorteilhafte Weiterbildungen der Erfindung sind Gegenstand der Unteransprüche . Die Erfindung wird nachfolgend anhand von Ausfuhrungsbeispie¬ len unter Bezugnahme auf die Zeichnung näher erläutert. Es zeigen:Advantageous developments of the invention are the subject of the dependent claims. The invention is explained in more detail below on the basis of exemplary embodiments with reference to the drawing. Show it:
Figur 1 eine schematische Darstellung einer Draufsicht auf eine erfindungsgemäß ausgebildete CMOS-Anordnung zur Veran¬ schaulichung der Anordnung von Substratkontakten auf der Oberfläche derselben,FIG. 1 shows a schematic representation of a top view of a CMOS arrangement designed according to the invention for illustrating the arrangement of substrate contacts on the surface thereof,
Figur 2 eine schematiεche Querεchnittεanεicht einer herkömm¬ lichen CMOS-Anordnung, undFIG. 2 shows a schematic cross-sectional view of a conventional CMOS arrangement, and
Figur 3 eine εchematiεche Darstellung einer Draufsicht auf eine herkömmliche CMOS-Anordnung zur Veranεchaulichung der Anordnung der Substratkontakte auf der Oberfläche derselben.FIG. 3 shows a schematic representation of a top view of a conventional CMOS arrangement for illustrating the arrangement of the substrate contacts on the surface thereof.
Die in der Figur 1 gezeigte CMOS-Anordnung weist abgesehen von den Subεtratkontakten den selben grundsätzlichen Aufbau wie die in der Figur 2 veranschaulichte herkömmliche CMOS- Anordnung auf. D.h., sie umfaßt mindestens einen NMOS-Bereich 2 und mindeεtenε einen PMOS-Bereich 3, die im wesentlichen wie in der Figur 2 gezeigt aufgebaut sein können und die wie in der Figur l gezeigt aneinandergrenzen können.Apart from the substrate contacts, the CMOS arrangement shown in FIG. 1 has the same basic structure as the conventional CMOS arrangement illustrated in FIG. 2. In other words, it comprises at least one NMOS area 2 and at least one PMOS area 3, which can be constructed essentially as shown in FIG. 2 and which can adjoin one another as shown in FIG.
Zur Erhöhung der latch-up-Festigkeit sind auf der (in der Fi¬ gur 1 in der Draufsicht gezeigten Anschlußseite der CMOS-An¬ ordnung wiederum Substratkontakte vorgesehen. Die Anzahl und Anordnung der Substratkontakte ist jedoch erfindungsgemäß derart modifiziert, daß die durchschnittliche Anzahl der Subεtratkontakte pro Flächeneinheit und/oder die durch¬ schnittliche Substratkontaktfläche pro Flächeneinheit inner¬ halb des mindeεtenε einen NMOS-Bereicheε weεentlich geringer iεt alε innerhalb des mindestens einen PMOS-Bereiches.To increase the latch-up strength, substrate contacts are again provided on the connection side of the CMOS arrangement shown in plan view in FIG. 1. However, the number and arrangement of the substrate contacts is modified according to the invention in such a way that the average number of contacts Substrate contacts per unit area and / or the average substrate contact area per unit area within the at least one NMOS area is substantially less than within the at least one PMOS area.
Eine mögliche Ausführungsform der erfindungsgemäßen Maßnahme besteht darin, daß, wie in der Figur 1 gezeigt ist, der min- destens eine PMOS-Bereich 3 in bekannter Art und Weise wie eingangs beschrieben mit Substratkontakten versehen ist, wäh¬ rend der NMOS-Bereich 2 nur am Rand mit Substratkontakten versehen ist.A possible embodiment of the measure according to the invention consists in that, as shown in FIG. at least one PMOS area 3 is provided with substrate contacts in a known manner as described at the beginning, while the NMOS area 2 is only provided with substrate contacts at the edge.
Eε hat εich herausgestellt, daß entgegen der bisherigen Auf¬ fassung der Fachwelt bei Vorsehen ausreichend vieler und/oder großer Substratkontakte im PMOS-Bereich auf die Substratkon¬ takte innerhalb des NMOS-Bereicheε ganz oder wenigstens wei- testgehend verzichtet werden kann, ohne nennenswerte Einbußen bei der latch-up-Festigkeit in Kauf nehmen zu müsεen.It has been found that, contrary to the previous view of the specialist world, if enough and / or large substrate contacts are provided in the PMOS area, the substrate contacts within the NMOS area can be completely or at least largely dispensed with, without any significant loss have to accept the latch-up strength.
Gemäß der Figur 1 εind in dem dort gezeigten NMOS-Bereich 2 nur wenige Subεtratkontakte vorgeεehen, wohingegen der PMOS- Bereich 3 Substratkontakte 34 in der bekannten Dichte und Größe, d.h. mit einem gegenseitigen Abstand von bei- spielsweiεe ca. 50 μm aufweiεt; die Verringerung der biεher üblicherweiεe vorgeεehenen Subεtratkontaktanzahl und/oder Subεtratkontaktfläche (Summe der Flächen der einzelnen Subεtratkontakte) im NMOS-Bereich macht eε nicht erforder¬ lich, gleichzeitig die Substratkontaktanzahl und/oder die Substratkontaktfläche innerhalb des PMOS-Bereiches zu erhö¬ hen.According to FIG. 1, only a few substrate contacts are provided in the NMOS area 2 shown there, whereas the PMOS area 3 has substrate contacts 34 in the known density and size, i.e. with a mutual distance of, for example, approximately 50 μm; the reduction of the more usually provided number of substrate contacts and / or substrate contact area (sum of the areas of the individual substrate contacts) in the NMOS area makes it not necessary to simultaneously increase the number of substrate contacts and / or the substrate contact area within the PMOS area.
Daε Vorεehen von Substratkontakten an der Bereichsgrenze führt weitgehend unabhängig von der vorgeεehenen Anzahl und/oder der belegten Fläche allenfalls zu einer geringfügig verringerten Verkleinerbarkeit der CMOS-Anordnung, weil die in dem in Rede stehenden NMOS-Bereich realisierten elektroni- sehen Bauelemente aus Gründen der Sicherheit und Zuverlässig¬ keit ohnehin nicht beliebig nahe an die Bereichsgrenze ge¬ setzt werden können.The provision of substrate contacts at the area boundary largely leads to a slightly reduced scalability of the CMOS arrangement, regardless of the number provided and / or the occupied area, because the electronic components realized in the NMOS area in question, for reasons of security and reliability cannot anyway be set arbitrarily close to the range limit.
Unabhängig von der gewählten Realisierungεform der erfin- dungsgemäßen Maßnahme kann infolge der absoluten Einsparbar- keit von Substratkontakten bzw. der belegten Substratkontakt- fläche eine höhere Packungsdichte der elektrischen Bauele- mente innerhalb deε NMOS-Bereicheε vorgesehen werden, was zu einer erheblichen Flächenreduzierung der Anordnung führt. Bei Versuchεanordnungen mit auεgewählten reinen NMOS-Gebieten, z.B. ROMε betrug die Flächenreduzierung mehrere zehn Prozent.Regardless of the selected form of implementation of the measure according to the invention, owing to the absolute savings on substrate contacts or the occupied substrate contact area, a higher packing density of the electrical components can elements within the NMOS area can be provided, which leads to a considerable reduction in area of the arrangement. In test arrangements with selected pure NMOS areas, for example ROMε, the area reduction was several ten percent.
Abgesehen davon ermöglicht das Vorsehen der erfindungsgemäßen Maßnahme auch eine einfachere und billigere Herstellung von CMOS-Anordnungen (weniger Einschränkungen beim Layout, gerin¬ gere Anzahl von zu verbindenden bzw. zu kontaktierenden Kon- taktstellen, geringerer Materialverbrauch) . Apart from this, the provision of the measure according to the invention also enables a simpler and cheaper production of CMOS arrangements (fewer layout restrictions, fewer number of contact points to be connected or contacted, lower material consumption).

Claims

Patentansprüche claims
1. CMOS-Anordnung, welche mindestens einen NMOS-Bereich (2) und mindestens einen PMOS-Bereich (3) aufweist, und welche an ihrer Oberfläche mit Subεtratkontakten (24, 34) versehen iεt, über welche jeweilige Substratabschnitte (1, 30) der CMOS- Anordnung mit vorbeεtimmten Spannungεwerten beaufschlagbar sind, d a d u r c h g e k e n n z e i c h n e t , daß die durchschnittliche Anzahl der Substratkontakte (24, 34) pro Flächeneinheit und/oder die durchschnittliche Substratkontaktfläche pro Flächeneinheit innerhalb deε min¬ deεtenε einen NMOS-Bereicheε (2) weεentlich geringer iεt alε innerhalb des mindeεtenε einen PMOS-Bereicheε (3) .1. CMOS arrangement, which has at least one NMOS region (2) and at least one PMOS region (3), and which is provided on its surface with substrate contacts (24, 34) via which respective substrate sections (1, 30) Predetermined voltage values can be applied to the CMOS arrangement, characterized in that the average number of substrate contacts (24, 34) per unit area and / or the average substrate contact area per unit area within the minimum one NMOS area (2) is substantially less than within at least one PMOS area (3).
2. CMOS-Anordnung nach Anεpruch 1, d a d u r c h g e k e n n z e i c h n e t , daß der mindeεtenε eine NMOS-Bereich (2) im weεentlichen frei von Substratkontakten (24, 34) ist.2. CMOS arrangement according to claim 1, so that the at least one NMOS area (2) is essentially free of substrate contacts (24, 34).
3. CMOS-Anordnung nach Anεpruch 1 oder 2, d a d u r c h g e k e n n z e i c h n e t , daß die Anzahl der Subεtratkontakte (24, 34) pro Flächenein¬ heit in dem mindestenε einen NMOS-Bereich (2) an der Be- reichεgrenze höher iεt alε im Bereichεzentrum. 3. CMOS arrangement according to claim 1 or 2, so that the number of substrate contacts (24, 34) per area unit in the at least one NMOS area (2) at the area limit is higher than in the area center.
EP96945730A 1995-12-06 1996-11-18 Cmos device Ceased EP0865669A2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19545554A DE19545554A1 (en) 1995-12-06 1995-12-06 CMOS arrangement
DE19545554 1995-12-06
PCT/DE1996/002189 WO1997021240A2 (en) 1995-12-06 1996-11-18 Cmos device

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EP0865669A2 true EP0865669A2 (en) 1998-09-23

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DE (1) DE19545554A1 (en)
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GB1549130A (en) * 1977-06-01 1979-08-01 Hughes Microelectronics Ltd Cm Monolithic integrated circuit
JPS5591162A (en) * 1978-12-27 1980-07-10 Fujitsu Ltd Semiconductor device
JPS58223362A (en) * 1982-06-21 1983-12-24 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device
JPH0669086B2 (en) * 1983-03-29 1994-08-31 株式会社日立製作所 Semiconductor device
EP0197730A3 (en) * 1985-03-29 1987-08-19 Advanced Micro Devices, Inc. Latch-up resistant integrated circuit and method of manufacture
ATE75877T1 (en) * 1985-08-26 1992-05-15 Siemens Ag INTEGRATED CIRCUIT USING COMPLEMENTARY CIRCUIT TECHNOLOGY WITH A SUBSTRATE PRE-VOLTAGE GENERATOR AND A SCHOTTKY DIODE.
US5336911A (en) * 1988-05-10 1994-08-09 Seiko Epson Corporation Semiconductor device
JPH0396272A (en) * 1989-09-08 1991-04-22 Toshiba Micro Electron Kk Cmos semiconductor device
KR0120572B1 (en) * 1994-05-04 1997-10-20 김주용 Semiconductor device and manufacture of the same

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JP3357069B2 (en) 2002-12-16
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US6160295A (en) 2000-12-12
RU2170475C2 (en) 2001-07-10
JP2000501247A (en) 2000-02-02
KR19990071877A (en) 1999-09-27
UA56148C2 (en) 2003-05-15
IN190506B (en) 2003-08-02
WO1997021240A3 (en) 1997-07-31
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DE19545554A1 (en) 1997-06-12
KR100415129B1 (en) 2004-04-13

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