DE2744114A1 - Storage FET modified to reduce waste - incorporates auxiliary zone, with additional channel and selection gate - Google Patents

Abstract

The storage FET has the known structure modified to reduce waste. There is an auxiliary zone (HS) which is of the same doping as the source and drain. It is introduced between the source (S) and the drain (D) in series with the channel (K). Behind this auxiliary zone is a further channel (Ka) with an isolated selection gate (Ga2). The further channel is very much wider than the normal channel (K). A third gate is used as a control gate (G2). The presence of this gate is optional and if present it acts capacitively on the storage gate (G1).

Description

SDeicher-FET with at least one gate.

The invention relates to a development of the in the main application / in Main patent P 24 45 079.1-33 specified objects, which a certain memory FET with a p-channel or n-channel concern, namely a memory FET with least a gate, namely with a floating gate surrounded on all sides by an insulator Storage gate in which the charge carriers inject the charge carriers to recharge the storage gate Sewer injection - d. H. Reloading through strongly accelerated in its own conductive channel and charge carriers that are heated as a result, which because of their heating up by an in Electric field acting in the source-drain direction sets the energy threshold to the conductivity band of the insulator in the case of electron injection or to the valence band of the insulator Overcome in the case of hole injection and thereby get to the storage gate - is utilized, its channel located between the drain region and the source region one acting in the source-drain current direction, when programming an increased field strength and thus the acceleration that delivers the heated load carriers has stretch, which by a mounted in the area of this sewer point considerable Structural inhomogeneity of the memory FET is caused and whereby when programming the storage gate is charged by the KanalinJektion, namely in the case of an n-channel storage FET by means of electron injection or in the case of of a p-channel memory FET by means of hole injection that the memory gate after this Charging by influence in the source-drain current in an inhibiting manner on the source-drain path acts. Such a memory FET can have a particularly low source-drain voltage be programmed what the reject rate in the production of such Memory FETs are allowed to decrease. The memory FET has an n-channel when Electrons should be injected, and a p-channel if holes in the memory gate should be injected. Such a memory FET has been used several times previously known and proposed, see e.g. in the non-prepublished Registration P 26 43 932.7 = VPA 76P6262 proposed memory FET with approximated nasal canal, its narrowing or canal inhomogeneity on the drain side End of the channel is attached.

The memory FET further developed by the invention is thus by the charging of its storage gate is controlled in the strongly blocking state, so that there are no 2-FET memory cells per se for its use in memory matrices, but only 1-FET memory cells are actually required, as in particular in the DT-OS 24 45 137 = VPA 74/6185 is explained above all on the basis of FIG. 4 there. Just in this particularly simple, space-saving structure of the 1-FET memory cell seen an important advantage of such a memory FET, as can be seen from it.

2-FET memory cells in which in particular a floating Memory FETs having a memory gate each have a selection FET or read FET connected is when using FAMOS memory FETs and SAMOS memory FETs and also in the case of MNOS memory FETs described in a large number of literature references, cf. in particular the DT-OS 24 45 077 = VPA 74/6186 as well as the one there and the one in the DT-OS 24 45 078 X VPA 74/6187 considered the state of the art.

It turns out that, surprisingly, the reject rate in the production of the above-cited memory FET described in the main application / in the main patent can be reduced if the memory FET in question is contrary to the other Customarily one further canal area in series with its source-drain route, which in turn is influenced by a controllable selection gate.

The invention is based on what is cited in the main application Main patent specified Speieher FET. The Speieher EET according to the invention is characterized in that between the source and the drain in series with its First an auxiliary area with the same doping as the source and the channel Drain and behind it another channel area with this additional channel area influencing, controllable selection gate isolated from this further channel area are inserted. The invention relates because of the additional attachment of the Select gate a storage FET with at least two gates, namely with the select gate and the storage gate. Because of the AND [NR] link of the other channel range and of the canal, the invention represents, as it were, a tetrode of a special kind, whereby the invention in terms of its structure and in terms of its effect has some similarities with the known 2-FET memory cells. An essential one The difference to the known 2-FET storage cells can be seen in the fact that the from Storage gate influenced channel when the storage gate was charged in its blocking State is controlled, so that it initially had the impression that the further channel area would be superfluous, because a memory gate chargeable in this way permits, alone the Speleher FET without any further channel area within a 1-FET storage cell to use.

By the measure according to the invention, however, the reject rate of highly integrated storage with n-channel storage cher FETs in particular can be further reduced by the fact that an unprogrammed n-channel memory E13T, whose storage gate is therefore uncharged due to statistical fluctuations in the manufacture and operation of such n-channel memory FETs e.g. instead of the frequently intended enhancement type characteristic even one that is not intended per se, conductive channel between its source-drain junction like a depletion type FET without endangering the operation of the storage tank. Namely, if a first memory FET and yet another memory FET - possibly even several others - each without the measure according to the invention are connected to the same read line, and if this other memory FET has a conductive channel and thereby a conductive connection to a power source, although it is only unprogrammed and therefore in the "O" state is, this conductive channel may mistakenly be in the "O" state first memory F "ET selected for reading when its memory gate is negatively charged and so is in the ~ 1 ~ state, pretend. The selected first memory FET supplies then namely as a read ~ 1 "status signal correctly ~ no power", however the other - or the other - memory FETs with inadvertently conducting channel unintentionally deliver the simulated, superimposed "O" status signal ~ Current flows ", so that apparently a" 1 "state signal from the first memory FET is read. The reject rate in the manufacture of the memory FET is thus at of the invention is reduced by the fact that statistical fluctuations in the properties the other memory FET can be made harmless by adding another one to itself Controlled channel range in series with the memory gate influenced channel of the memory FET is appropriate. The other channel area of the other memory FET is namely at Reading of the first memory FET, as is known per se from 2-FET memory cells, in its non-conductive state controlled, so that a per se unintentional conducting channel of this other memory FET not a false one because of the t1ND link read signal can simulate more.

Especially in the case of a - e.g. with UV - ~ light - deleted, so again Unprogrammed memory FET is made possible by the invention without interference the storage operation one - e.g. by the DT-OS 25 13 207 = VPA 75P6039 for itself known - excessive deletion of the memory gate is permitted, so that by the Invention of the channel is allowed to conduct even at zero source slope voltage, i.e. Z.3. the storage gate not after unloading, as estl. intended to be electrically neutral, but may be positively charged with holes or in traps of the insulator Holes may be trapped, yes that even an impoverishment-type canal through a thin one n-doped layer attached between the source and the drain or the auxiliary region may be - even if a main line connection, e.g. the source, is constantly on dz a power source, e.g. wet, is connected. The one shown in DT-OS 25 13 207 Corrective Action to Allow Excessive Discharge of the Storage Gate namely to install the storage gate only under a certain part of the control gate, namely affects the reject rate, because it sets relatively high requirements the tolerances of the production of masks used and the tolerances the adjustment of these masks during the manufacture of the memory FET - requirements, which can be less high in the invention, even if an additional one Control gate is placed over the memory gate as described below Process for producing such a development of the invention can be seen.

Another circumstance lowers the reject rate when applying the measure according to the invention. Especially if a channel with a particularly short channel length is used, a certain threshold current often occurs unintentionally on as soon as a high positive bias voltage at the drain relative to the source potential is related, especially if a control gate is also attached to which there is no bias voltage on the source potential, e.g. ground is particularly important if the Storage FET in one Memory array is attached, with a first, selected memory FET just is programmed and one or more other memory FETs connected to the drain with are connected to the drain of the first memory FET and which in turn are not programmed and which in themselves should not be programmed. Such non-programmed ones other memory FETs then exhibit - especially because of the statistical fluctuations the characteristics of the plurality of memory FETs mounted in memory - sometimes quite considerable sub-threshold currents.

In the case of such other memory FETs, what is known as ~ Punch-through "another source-drain current undesirably occur. Such cause thiter threshold currents and punch-through currents of the other memory FETs, that the total currents that flow in the connecting line connecting the drains, sometimes become considerably large, e.g. often a multiple of the source-drain current of the first memory FET to be programmed. By virtue of the fact that according to the invention between the source and the drain another channel region in series with the source-drain path of the memory w T is attached, this further channel area if not selected Memory FETs during the programming process of the first memory FET by themselves can be controlled in the non-conductive state, such sub-threshold currents and punch-through currents can be effectively suppressed. So this is how it flows because of the invention in the relevant connecting line connecting the drains to one another only the source-drain current of the first memory FET required for programming, so that the voltage drop across the FETs of the edge electronics that are effective in series such a memory remains relatively small.

The smaller this voltage drop in the edge electronics, the more so the first memory FET is programmed more reliably.

The one placed between the source and the drain in the invention Auxiliary area allows particularly simple manufacturing processes to the Fabrication of the gates apply as from the fabrication process examples described below emerges.

The invention thus improves the reject rate in particular by that despite inevitable statistical fluctuations in the properties of the various Memory FETs of a large memory matrix disturbances are rendered harmless, which otherwise in particular due to high demands on tolerances, due to excessive Extinction, through threshold currents and / or through punch-through currents, can still occur can.

The invention and further developments thereof are illustrated with the aid of the figures 1 and 2 described in more detail, which show a longitudinal section and a plan view of an embodiment show the invention. By using the same reference symbols as in the main application Main patent, the present description can essentially be based on the further education Features that relate to the invention and its developments restrict.

Figure 1 shows that surrounded on all sides by an insulator, in electrical Regarding floating memory gate GI and the source-drain path S-D. Between the Auxiliary area HS and the drain D is influenced by the memory gate GI, as Inhomogeneity containing the mostly particularly favorable constriction on the drain side Channel K, the length of which in the present example is used to reduce the programming required voltage is also relatively short, namely here is only 3 / u. then however, this channel is still so long that the demands on the tolerances the masks in the manufacture of this example are therefore relatively small.

The memory EfET shown in FIG. 1, which incidentally has an n-channel contains, also contains the one in series with channel K. effective further Channel area Ka, which in this case is also only 3 / u long. This further channel area In the exemplary embodiment shown, Ka lies between the source 5 and the auxiliary region HS. This auxiliary area itself does not have any to the outside in this exemplary embodiment own connection on in contrast to the source 5 and the drain D, as in the figure is indicated. Also the control gate G2, which is not always provided in the invention and that which is always provided in the invention and which influences the further channel region Ka Selection gates Ga2 can be controlled from the outside, as is also indicated in FIG. 1.

The embodiment shown thus represents a tetrode in particular Art, namely having two separate gates Ga2 and GI, the one of these Gates influenced areas K, Ka are electrically in series with one another and therefore exercise an AND link in the source-drain path S-D. Because this source-drain route S-D only conducts if each of the two areas influenced by the gates Ga2, Ol K and Ka conducts independently, the memory FET shown corresponds to a 2-FET memory cell. An essential difference to known 2-FET memory cells, however, is that that the invention is a memory FET whose memory gate GI when programming with the help of channel injection is charged in such a way that its Channel K is controlled by charging into the blocking state instead of the conducting state will.

The other channel area Ka prevents due to the AND link in its non-conductive state, that in the event of excessive erasure of the memory gate GI a current flows through the source-drain path S-D, which, as described above, to simulate ~ O "states during the reading process of other memory FETs could lead. The further channel area Ka also prevents due to the AND links in its locking state that unintentional Sub-threshold currents or punch-through currents flow in channel K and thus in source-drain path S-D, which could interfere with the programming of other memory FETs.

It is favorable that the one shown in FIG. 2, not shown in FIG. 1, is advantageous The width of the further channel region Ka is as large as possible compared to that in FIG. 2 shown, not shown in Fig. 1 width of the channel K so that during When programming this memory FET, the lowest possible voltage drop on the further channel area Ka occurs and thus as possible the entire voltage over of the conductive source-drain path S-D then occurs via the channel K. The lower namely the voltage drop at the further channel area Ka compared to the voltage drop is on channel K, the more intense the heating of the charges in the conductive channel K during programming, so that the intended charge of the memory gate G1 then occurs particularly reliably. For example, a ratio of the channel widths can be used think of 10: 1 and even more, so that the space required for this training, such as Fig. 2 shows, however, essentially through the width of the further channel region Ka is only insignificantly caused by the space requirement of channel K of the memory FET. This dimensioning is particularly recommended if the storage FET is in a memory chip is attached, the relatively few such memory FETs contains, so that the space requirement is less important than the high reliability and than is the reduced reject rate. This embodiment is therefore suitable especially for memory chips with only e.g. 1024 or 256 memory cells that are used for Storing short programs are often sufficient.

If the invention only has the floating memory gate G1, but not also has the control gate G2 shown in Fig. 1, the structure is special simple. This execution example is relatively quick with Can be erased with the help of ultraviolet light because there is no overlying a shadow G2 throwing control gate is available. To such an embodiment especially To be able to operate reliably as a storage cell, it is sometimes advisable to a sufficiently increased capacitive coupling between the memory gate and GI to the drain D, e.g. by particularly large overlapping of these two areas. In this way it is ensured that, when programming it at the beginning the charge, the storage gate potential by means of the drain potential in the case of electron injection is made so positive or, in the case of hole injection, so negative that the channel K is reliable controls in the conductive state and that the memory gate Ol also controls in the channel K attracts heated charge carriers and thus promotes their charging. By a such sufficient capacitive coupling between the drain D and the memory gate GI, this channel K is particularly reliable when reading and when starting programming in the unprogrammed state of the memory FET - at least weakly - conductive, but when reading in the programmed state this memory FET is reliably non-conductive, even if the channel K is of the enhancement type due to its doping or structure is - but especially if he is of the impoverishment type.

However, if the memory FET, as shown in Fig. 1, an additional, Having controllable control gate G2, it is not necessary to have a capacitive coupling between the drain D and the memory gate GI and / or a depletion type channel K to attach in the unprogrammed state during the reading process the ~ O "state signal ~ Current flows "or a conductive state of the channel at the beginning of programming K to get. A suitable potential can then be applied to this control gate G2 be placed through which the channel K is conductive, if the memory FET each is not programmed, and channel K is non-conductive if the memory FET programmed. How still are the requirements to the tolerances of masks in the manufacture of the precisely stacked ones Gates GI and G2 pleasantly low. The manufacture of the memory FET with control gate is also simple because the channel K can be of the enrichment type, i.e. of the same type Type, like the wide channel area Ka shown in FIG. 1.

Because the control gate G2 and the selection gate Ga2 are not immediate The clock frequency can be conductively connected to one another but can be controlled separately to operate such a memory FET and therefore also to operate from such Memory FETs built up memories are increased. The overall effective capacity on the connecting lines of the memory, which the relevant selection gate Ga2 or supply corresponding potentials to the relevant control gates G2 namely reduced, so that the transient state between two consecutive Clocking is correspondingly short in time. The shortening of the respective settling time allows the clock frequency to be increased when operating such memories.

It also allows the two controllable ones to be controlled separately Gates G2, Ga2 to supply both gates with different potentials. In particular one can in such a case between the auxiliary area HS or the source 5 on the one hand and the selection gate Ga2 on the other hand, significantly higher voltages than between the Drain D on the one hand and the control gate G2 on the other hand during the programming process invest. This has the advantage that the other Channel area Ka is then particularly good conductive and thus often even with low Channel width has a particularly low voltage drop, so that the heating of the electrons in the conductive channel K are particularly strong during the channel injection fails, which makes it easier to charge the storage gate GI.

Because the auxiliary area HS is used to limit the channel at the same time K as well as to limit the further K- nal area Ka exploited by being immediately adjacent to these two areas, as shown in the figure you can save special conductive connections that would have to be made, if one has the channel K on the one hand and the further channel region Ka on the other hand, respectively would limit what would be possible in itself through various, own areas of assistance. In addition, this brings the channel K and the further channel area Ka together limiting single auxiliary area HS has the advantage of particularly little space on the surface of the substrate HT to need. In addition, a such a single auxiliary area HS, relatively simple masks in the production of the Use memory FET.

Especially when the capacity between the auxiliary area HS and the Substrate HT - for whatever reason, e.g. 3. because of the large width of the canal area Ka-is large, when programming another memory FET, its drain with is directly connected to the drain of the first memory FET, a disturbance occur: During the programming of the other memory FET is namely on Drain D of the first memory FET also has the corresponding positive or negative Potential - depending on the type of channel, i.e. whether it is an n-channel memory FET or a p-channel memory FET - while the auxiliary area HS this first memory FET still approximately at the potential of the substrate HT, i.e. e.g. on mass potential. Even if the wider channel area is Ka during this time is controlled in its non-conductive state, flows between the auxiliary area HS and the drain D in the channel K a powerful, the high capacity between the auxiliary area HS and substrate HT charging current if the channel K is conductive, e.g. if so during this operating state - for whatever reason - additionally the potential of the control gate G2 later in the positive or negative direction, depending on the channel type is changed. Because of the conductivity of channel K namely can through which the high capacitance between the auxiliary area HS and the substrate HT charges Current a channel injection and thus a partial charging of the storage gate G1, to be triggered.

The problem is that with each programming one other memory FET even unintentionally a partial multiple times in a row Charging of the storage gate ol of the first storage FET with heated charge carriers can occur until this memory gate GI is finally charged quite heavily and simulates an intentional programming of this first memory FET. This disruption can be reduced or avoided in particular by the fact that between the auxiliary area HS and the drain D, in electrical terms parallel to the channel K, or a high-value resistor between the auxiliary area HS and a voltage source is inserted, over which the HilSsbereich HS to the potential of the drain D in is charged harmlessly as long as the further channel area Ka at least is largely controlled in its non-conductive state.

The one shown schematically in the figures, having a control gate G2 Embodiment can be produced, for example, in the following way: On the conductive Substrate HT is first allowed to grow a thick oxide layer.

Then you etch a window in the thick oxide layer along the entire length Area and length OL of the source-drain path S-D of the memory FET, so that the substrate HT is openly accessible again there. This also results in the narrowing shown in FIG. 2 V generated. A first insulating layer, namely a thin oxide layer, is then left II grow on this entire area of the window, e.g. with a thickness of 6002. A first polysilicon layer is then allowed to grow, which is then doped and which are then etched away again with high permissible tolerances, with the exception the to the memory gate Ol and the adjacent, protruding edge layers G1 ', which are not yet etched away. So the storage gate Ol remains together with provisionally adjoining edge layers G1 ', these edge layers Ol' Now cover parts of the later auxiliary area HS and the later drain D, but do not have to have a certain size themselves. These protruding edge layers Ol 'will only be etched away later, as will be described later.

Next, one leaves on the polysilicon areas G1, Ol 'as well as on the parts of the first insulating layer Ii that are still exposed, a second insulating layer 12, e.g. with a thickness of 50. On this second insulating layer 12 one leaves a second polysilicon layer grow, from which by etching away by means of a Mask the control gate G2 and the select gate Ga2 is formed. By taking advantage of the The same mask can also be used for those areas of the insulating layers I1, 12 and etch away the protruding edge layers G1 ', which were previously the later areas of drain D, source 5 and auxiliary area HS covered, so that the memory gate ol and the control gate G2 are particularly exactly layered on top of each other, what also for the reject rate is reduced.

One can then use, for example by means of ion implantation of the control gate G2 and the selection gate Ga2 as well as the thick oxide layer Du as a mask, generate the doping of the areas D, S, HS. At the same time, the polysilicon is used of the control gate G2 and the selection gate Ga2 doped in the same way and thus well conductive. Instead of using ion implantation, one can also use diffusion generate the doping of the areas D, S, HS in a manner known per se, in which at the same time a doping of the parts of the polysilicon layer that form the control gate G2 and form the select gate Ga2 is achieved.

The manufacturing state now reached is shown in FIG. 1.

The n-doped regions are in the p-conductive substrate HT here D, S, HS generated. Between the selection gate Ga2 and the further channel area Ka is composed of parts of the first and second insulating layers I1, 12 Insulator.

Between the control gate G2 and the channel K is one after the other remaining part of the second insulating layer 12, the first polysilicon layer ol and the first insulating layer I1. The source-drain path S-D of this n-channel memory FET is surrounded by the thick oxide layer Du. A variety of such n-channel memory FETs can be attached to the substrate HT at the same time and form a memory. By using the mask that forms the control gate G2 to etch the source free 5 and the drain D is, as already mentioned, also achieved in an elegant way, that the control gate G2 is mounted very precisely over the memory gate ol, wherein these two gates, as shown in FIG. 1, are each the same in this example are long, namely about 31u long.

On the entire disk with the state shown in FIG. 1, one can let a first protective oxide layer grow, in which one can use a window Attaches contacts for the areas 5 and D and for the controllable gates Ga2 and G2.

Then you can use metal vapor deposition to connect the connecting lines of the module, as well as create a second protective oxide layer on top.

Such a production of the control gate G2, the memory gate G1 and the channel K together with the areas H5 and D is already through for itself the DT-OS 24 45 030 = VPA 74/1129 known.

If you have a memory FET according to the invention without a control gate G2 produces, you can still reduce the number of process steps. One can namely after growing up the first layer of polysilicon immediately this first polysilicon layer with the exception of the one to the memory gate by means of a mask Etch away the oil and the parts of this layer belonging to the selection gate Ga2 - In this case, the insulator between the substrate HT is on the one hand and the two gates G1, Ga2, on the other hand, each have the same thickness, e.g. 6002 thick.

Then you can by means of ion implantation, taking advantage of the gates Ol and Ga2 and the thick oxide layer Du as masks a doping of the areas Generate S, HS, D, Ga2 and Oil. Instead of this ion implantation, one can also use Use of the same mask with which the gates G1, Ga2 were formed, the insulating layers Etch away over the later areas S, HS, 5 and use these areas S, HD, D Generate diffusion, with a doping of the gates G1, Ga2 occurring at the same time. A first protective oxide layer can then be applied over the entire pane by means of window contacts of the areas S, D, Ga2, as well as by means of metal vapor deposition still generate connecting lines. After all, you can do the whole disc with one cover the second protective oxide layer.

In the case of the memory FET with control gate G2, the thickness of the insulator between the selection gate Ga2 and the further channel region Ka can be reduced should, you can modify the manufacturing process described in that one between the formation of the regions G1, Ol 'from the first polysilicon layer and the subsequent application of the second insulating layer 12, a further process step inserts, namely an etching away of all now exposed parts of the first insulating layer II by means of Cl, G1 'or by means of the mask used to form G1, Cl'. then the insulator exists between the selection gate Ga2 and the further channel area Ka only from the second insulating layer 12, whereby the control potentials at the selection gate Ga2 in the out Shot diminishing way more intense the further Channel area Ka can influence 10 patent claims 2 figures Blank page

Claims (10)

Memory FET with at least one gate, namely with a floating memory gate surrounded on all sides by an insulator, in which the Reloading of the storage gate the charge carrier injecting channel injection - d. H. ttcharge through strongly accelerated and thereby heated up in its own conductive channel Charge carriers which, because of their heating, act in the source-drain direction electric field the energy threshold to the conductivity band of the insulator in the event the electron injection or to the valence band of the insulator in the case of hole injection overcome and thereby get to the memory gate - is exploited, being between Drain area and source area located channel one in the source-drain current direction acting, exhibiting an increased field strength during programming and thus the having heated charge carrier delivering acceleration path through a considerable structural inhomogeneity of the Memory FET is caused and whereby when programming the memory gate through the channel injection is thus charged, namely in the case of an n-channel memory FET by means of electron injection or, in the case of a p-channel memory FET, by means of hole injection, that the memory gate after this charging by influencing the source-drain current acts inhibitory way on the source-drain path, especially for program memory of a telephone switching system that is not indicated that between the source (5) and the drain (D) in series with its channel (K) first an auxiliary region (Hs) with the same doping as the source and drain and behind it another canal area (Ka) with an influencing this further canal area, controllable selection gate (Ga2) isolated from this further channel area are. 2. Memory FET according to claim 1, d a d u r c h g e k e n n -z e i c h n e t that the width of the further channel region (Ka) is very much greater than is the width of the channel (K). 3. Memory FET according to claim 1 or 2, d a d u r c h g e -k e n n indicates that it only has the select gate (Ga2) and the memory gate (ei), but has no further gate (G2). 4. Memory FET according to claim 1 or 2, d a d u r c h g e -k e n n indicates that it has an additional, one connection, controllable Control gate (G2) has that capacitive effect on the memory gate (G1). 5. memory FET according to any one of the preceding claims, d a -d u r c h g e k e n n n e i c h n e t that the auxiliary area (H5) both to the other Channel area (Ka) as well as directly adjacent to the channel (K). 6. memory FET according to any one of the preceding claims, d a -d u notices that the Hilis area tHS) is attached to a special, high resistance is connected. 7. A method for manufacturing the memory FET according to claim 3, g e I do not like the sequence of the following process steps: a. on one in the case of a p-channel memory FET n-conducting, in the case of an n-channel memory FET p-type silicon wafer as a substrate (HT) is a relatively thick oxide layer (Du) applied, in the one up to the substrate (HT) continuous window, in which the source-drain path is intended to be etched; b. in the window there will be a relative thin first insulating layer (11) produced; c. there will be a first on the whole disc Polysilicon layer deposited; d. the first polysilicon layer using a mask down to the required areas of the selection gate (Ga2) and etched away the memory gate (G1); e. it becomes doping through ion implantation the selection gate (Ga2), the memory gate (ei), the source (5), the auxiliary area (HS) and the drain (D) generated; f. a first protective oxide layer is applied over the entire pane, furthermore by means of contact windows contacts for the drain (D), the source (5) and the Selection gate (Ga2), as well as the necessary connecting lines by means of metal vapor deposition manufactured; G. A second protective oxide layer is made over the entire pane. 8. The method according to claim 7, g e k e n n z e i c h n e t d u r c h the following change in the process ear e: el. by means of the same mask that was used to form the gates (G1, Ga2) in process step d, the Over the later source (5), the later auxiliary area (HS) and the later drain (D) lying parts of the first insulating layer (11) are etched away; e2. a doping the memory gate (G1), the selection gate (Ga2), the drain (D), the auxiliary area (H5) and the source (5) is generated by means of diffusion. 9. A method for manufacturing the memory FET according to claim 4 or 5, g e k e n n n z e i c h n e t d u r c h the following process steps: a. On an n-channel in the case of a p-channel memory FET, and in the case of an n-channel memory FET p-type silicon wafer as a substrate (HT) is a relatively thick oxide layer (Du) applied, into which a window that extends to the substrate (Ht), in which the source-drain path is intended to be etched; b. in the window there will be a relative thin first insulating layer (11) produced; c. all over the disc a first polysilicon layer is deposited, which is additionally doped; d. the first polysilicon layer is essentially down to what is required Area of the memory gate (G) etched away, however, being adjacent to the memory gate (G1) first a protruding edge layer (G1 ') into the one above the later one Auxiliary area (HS) and the later drain (D) located areas extends into it; e. a relatively thin second insulating layer is formed on the first polysilicon layer (12) generated; r. a second polysilicon layer is deposited over the entire wafer; G. the second polysilicon layer is down to the required level by means of a mask Areas of the control gate (G2) and the selection gate (Ga2) etched away; H. with the to Forming the control gate (G2) and the selection gate (Ga2) used in the process step g Mask are the over the later auxiliary area (HS) and the later drain (s) extending> edge layer (Gl ') of the first polysilicon layer and not required parts of the first and second insulating layers (11, I2) etched away; i. one Doping of the parts corresponding to the control gate (G2) and the selection gate (Ga2) the second polysilicon layer and a doping of the substrate (HT) on it exposed surfaces for producing the source (5), the auxiliary area (HS), and the drain (D) is attached; k. A first protective oxide layer is applied over the entire pane, Furthermore, contacts for the drain (D), the selection gate, are established by means of contact windows (Ga2) and the control gate (G2), as well as by means of metal vapor deposition, the required Connecting lines made; 1. A second protective oxide layer is applied over the entire pane manufactured. 10. The method according to claim 9, g e k e n n z e i c h n e t d u r c h the insertion of a further process step between the process steps d and e: di. The remaining parts of the first polysilicon layer (C1, G1 ') uncovered parts of the first insulating layer (11) are etched away.