DE2445079B2 - Storage field effect transistor - Google Patents

Description

As indicated in the preamble of claim 1, the invention relates to a memory field effect transistor (memory FET) with a memory gate that is surrounded on all sides by an insulator, and with a semiconductor substrate in which a source region and a drain region are arranged and delimit a channel region in the longitudinal direction, and in which the charge state of the memory gate is changed by supplying charge carriers from the channel region during operation by applying such a voltage between the source region and the drain region that charge carriers from the conductive Passage through the insulator to the memory gate (channel injection). Such a memory FET is already described in IEEE ₁ J. of Solid State Ciruits SC-7, Oct. 1972, No. 5, pp. 369-375. The memory FET according to the invention was developed primarily for use in the program memories of a telephone switching system, but is also particularly suitable for read-only memories in an electronic data processing system.

Memory FETs with a floating insulated gate, that is to say with a memory gate - specifically with η-channels or p-channels - whose memory gate, which is insulated from the channel, has no electrical, lead-out contact, are already known several times per se. Such memory FETs are / .. B. in US-PS 36 60 819 and in DF-OS 21 29 181 described, and in Proc. of the 4th Conf. of Solid State Devices Tokyo 1972 / Suppl. to the lournal of the japan Society of Appl.Phys. 42 (1973) pp. 158-166.

Such memory FETs with memory gates are particularly suitable as memory elements in an electrical one programmable ROM. as the charge on the storage galley is reduced when the appropriate Choice of the insulator often does not change for years, so that this charge of the .Speichergate over a long period of time the conduction state of the between the drain-source area lying canal. These memory FETs can be used because of the storage elements it is possible. affecting that potential of the memory gate. As is well known, you can go through Applying appropriate voltages between the drain area or source area on the one hand and the Substrate, on the other hand, charge the storage gate, namely because some of the charge carriers are blocked pn-junction is heated and thereby penetrate from below through the insulator to the memory gate can. In the case of the known memory FETs, the amount required to charge the memory gate is high Speed of the charge carriers penetrating the insulator by applying the breakdown voltage to the blocking pn junction between the substrate on the one hand and the drain area or source area on the other hand generated. According to DE-OS 22 35 5 33, page 16, paragraph 2, such a charge of the Storage of these storage FHTs also by applying voltages between the drain area and the source area can be achieved.

If the drain-source voltage is too low to charge the memory gate, then the memory gate potential changes not - such relatively small drain-source voltages cn are used for reading, i.e. H. to check the Line country of the K; m; ils. if the memory FF.T used as electronic storage. Since the state of the memory FET built according to the present invention in the same way as in known memory FETs due to relatively small drain-source voltages can be read, will not go into this further.

As is known, a discharge of the storage gate is also possible if required, e.g. B. by irradiation of the Isclator with ultraviolet light whereby the charge carriers of the storage gate over the Insulator to the Can drain substrate.

The object of the invention is to provide a memory FET of the type mentioned in the preamble of claim 1 create in which the required to change the charge state of the memory gate Voltage between the source region and the drain region is particularly low.

The invention is based on the knowledge. that by generating a high field strength at a locally limited point in the conductive channel itself, that is, between the source region and the drain region the charge carriers there can be accelerated and thus heated in the longitudinal direction of the channel in such a way that some of these charge carriers penetrate perpendicular to the channel, i.e. through the insulator, to the memory gate can, at least as long as there is no disruptive high braking voltage between the memory gate on the one hand and the exit point of the charges is at the boundary between the insulator and the channel on the other hand; - in the In general, it is even advantageous if, instead of such a braking voltage, the storage gate is charged a corresponding acceleration voltage / between the memory gate and the exit point is a part the load carrier can, for. B. caused by bumps in the channel surface and because of impacts Distractions, also move perpendicular to the canal. In doing so, these heated load carriers should be used The object according to the invention can be achieved solely by the longitudinal field strength in the channel.

In the case of the memory FET mentioned at the beginning and in the preamble, this task is carried out by the im Characteristics of claim 1 mentioned additional measures solved.

The structural inhomogeneity can, for. B. by a local limited thickening of the insulator / wipe the channel and the memory gate are formed, so that at this point of the channel by the memory gate-channel voltage less free charges are induced than at the other points of the channel. Through the Inhomogeneity arises in the adjacent, only a few frc'c charge carriers containing point of the channel an acceleration path in which because of the Low load the longitudinal field thickness in the sewer is greater than in the other sewer sections.

However, the inhomogeneity of the structure can - instead of through an insulator thickening or in addition to the Insulator thickening - formed by a narrowing of the duct, the duct width in the Narrowing no more than half the width of the canal other sewer points. The acceleration of the charge carriers aimed at in the invention is within the constriction, the larger the smaller the channel width in the constriction according to and / or depending the insulator thickening is made thicker in relation to the thickness of the insulator at the remaining channel locations.

Particularly high field strengths occur in the longitudinal direction within the acceleration paths generated in this way of the channel, so that the charge carriers are accelerated particularly strongly there. Most heated charge carriers flow / was further along the channel. Part of the heated load carriers but can also penetrate perpendicular to the channel through the insulator to the memory gate and charge it.

ke not a too high rating, but if possible even additional acceleration voltage, which in turn attracts the heated load carrier. The storage gate can then be charged until Such a strong braking voltage arises between the memory gate and the acceleration path that none are heated up More charge carriers can penetrate the insulator.

The invention is explained in more detail with reference to the schemes of exemplary embodiments shown in the figures explained, where

Fig. 1 shows a cross section through an embodiment of the memory FET according to the invention,

FIGS. 2 to 4 are views from below of various embodiments of the in FIG. 1 memory FET shown,

5 and 6 views from below of particular embodiments of the memory FET according to the invention,

FIG. 7 shows a view from below of a further embodiment of the in FIG. 1 memory FET and

8 and 9 cross sections through two further embodiments of the memory FET according to the invention demonstrate.

Fi g. I schematically shows a cross section through an embodiment of the invention. Between the drain area D and the source area 5 lies the area K of the substrate in which the channel of this enhancement-type FET is formed, namely by the fact that the charge of the memory gate is only, for example, 0 , 1 μηι thick SiOi-lsola'.or is generated by means of influence, a channel consisting of movable charges on the surface of the substrate region K. The shape of the channel, seen from below, see. Fig. 2, therefore corresponds to the shape of this only 0.1 μίτι removed portion of the storage gate g, see FIG. F i g. I. By selecting the shape of the .Speichergate g can therefore determine the corresponding shape of the channel.

The memory FET WCiJt shown in FIG. I has an η-channel, that is η-doped areas D and S. The memory gate G, which is surrounded on all sides by the insulator A and is therefore electrically, is located above the substrate area or channel K lying in between Respect floats. The memory gate G has no electrical contact whatsoever with the channel K and there is also no connection for this memory gate via which an electrical charge could be supplied from the outside to the memory gate. The in F i g. The memory FET shown in FIG. 1 thus has a drain connection DA and a source connection SA , but no memory gate connection.

The channel K has an acceleration section V. which in the case of the FIG. 1 cross section shown was only hinted at. This acceleration section V generated by an inhomogeneity is better z. B. in F i g. 2 and 4, which show different configurations of such acceleration paths V formed by constrictions. These in the F i g. The configurations shown in FIGS. 2 to 4 are also missing with dimensioning information. In the exemplary embodiment shown in FIG. 2, the channel K has a trapezoidal shape, as a result of which a constriction V, here directly at the channel end in the vicinity of the drain region D, is provided. The narrowing here is approx. 50% of the maximum channel width. In Fig. J is the constriction K, which is also attached to the channel endc in the vicinity of the drain region D. particularly strong - here it is only 17% of the maximum channel width. In Fig. 4 the constriction V is asymmetrical

If a voltage is applied between the drain area D and the source area S, a voltage gradient arises in the channel K in the longitudinal direction of the channel K, i.e. directed from the drain area D to the source area 5 or vice versa from the source area 5 to the drain Area D directed. As a result, a particularly high voltage gradient, ie longitudinal field strength in the channel, will occur in a locally limited manner directly in the constriction V and in the vicinity of this constriction. In the remaining sections of the channel K , the voltage gradient is smaller.

Due to the high voltage gradient in the constriction V, the charge carriers are accelerated particularly strongly there, that is, they are heated up particularly strongly. In the remaining sections of channel K , because of the smaller voltage gradient there, the acceleration of the charge carriers is correspondingly lower - the charge carriers are therefore colder there.

The charge carriers heated in the constriction V do not all flow along the voltage gradient, that is, in the direction of the longitudinal axis of the channel. Especially if there is a potential at the storage gate C which attracts the heated, negative charge carriers sufficiently strongly - especially if there are also unevenness of the channel surface or deflections of the charge carriers caused by impacts - then some of these charge carriers attracted by the storage gate G penetrate through the isolator A to the memory gate C and charges this memory gate. The charge supplied to the memory gate normally remains stored on the memory gate, since the memory gate is surrounded on all sides by the insulator A , so that the conductivity of the FET channel K is controlled by the influence of the charge now stored in the memory gate C. The size of the ohmic resistance of the channel K is now an indication of whether a corresponding charge is stored on the memory gate G or whether no such charge is stored there.

These are the heated charge carriers that press through the insulator to the storage gate are generally electrons. It is already known per se, also heated holes through the To let the insulator penetrate to the memory gate, which is the case with the insulator materials used nowadays takes place only with a very low degree of efficiency, so that the charging of the memory gate with holes is very high slower than charging with electrons. Therefore, in general, the FET of the present invention equipped with an η-channel, which already contains more electrons than holes and therefore a special one fast charging of the storage gate allowed.

An experiment clearly shows the effect of the acceleration distance:

The drain-source voltage for charging the memory gate could even with the one shown in FIG. 2 shown Example, despite the relatively weak narrowing, can be selected about a third smaller than with one Memory FET with a memory gate that has no narrowing but the same channel length.

In FIGS. 5 and 6, two exemplary embodiments are shown in which the inhomogeneity was formed by constrictions V and V , respectively, in that, for example, corresponding holes or constrictions were provided in the middle of the memory gate in the areas B. FIG. In such designs, their acceleration distances approximately in the middle between the drain region D and source region S due to strong constrictions

are formed, the storage gate acceleration path voltage pulling the charge carriers to the storage gate can already be achieved with lower voltages between voltages between storage gate C and source 5 than are necessary for charging the embodiment shown in FIG. There, in the embodiment according to FIG. 2, a memory gate-source voltage is necessary for charging, which is at least approximately the drain-source voltage, since the acceleration path has a potential similar to that of the drain region D.

The inhomogeneity V can also be applied close to the source region in the case of an n-channel FET. The inhomogeneity should be particularly strong in this case, so that the charge carrier density there, which is usually particularly high there, does not compensate too much for the accelerating effect of the inhomogeneity. The channel width in the constriction V should therefore be z. B. be only 10% of the maximum width of the channel K. In this embodiment, the voltage between the memory gate and the acceleration path can advantageously be made particularly small during the charging of the memory gate, without at the same time completely interrupting the channel there due to a lack of influence.

The inhomogeneity can therefore be applied anywhere along the channel K, that is to say anywhere between the channel center and the channel end.

The design that is symmetrical in relation to the center of the duct offers a particular advantage. This is a memory FET, the inhomogeneity of which lies directly in this center of the channel K , compare FIG. 5 and 6, or around a memory FET that has two inhomogeneities symmetrical to this center, one left and one right of the center, see the inhomogeneities Vi and V2 in FIG Because of the symmetry, memory FETs can be charged both by voltages directed from the drain region D to the source region 5 and by advantageously equally high voltages directed from the source region 5 to the drain region D.

The measure according to the invention can in principle also be used in a storage FET of the depletion type, that is, cannot be applied only to an enhancement type storage FET. As with the enrichment type In the case of the depletion type, charge carriers, especially electrons, are in the acceleration path heated accordingly as soon as free charge carriers move through the acceleration path along the Move source-drain voltage.

The high field strength at the constriction V can be achieved with particularly low source-drain voltages if the length of the channel between the source area and drain area is made as short as possible, e.g. B. only a few μιη long or even smaller. This reduction in voltage can be achieved in any shape and in any position of the constriction in the channel K.

The inhomogeneity can in each case also be formed by a thickening Vd of the insulator A instead of by a narrowing K of the channel K , see FIG. 8. In the area of this thickening Vd , the influence of the memory gate C is weaker than at other channel locations, so that less high charge densities, that is to say higher longitudinal field strengths, prevail in the channel during the thickening than at the other channel locations.

The acceleration path is created here by the increased field strength. The channel charge carriers heated there can penetrate through the insulator to the storage gate G, especially at the edge of the thickening Vd, where the insulator A is thinner again. A memory FET with an inhomogeneity formed by such a thickening has approximately the same properties and advantages as a memory FET with an inhomogeneity formed by a channel constriction. It is therefore advantageous to apply the thickening anywhere along the channel.

If, in addition to the insulator thickening Vd , the duct narrowing V already described is also brought to the same duct point, see FIG. 2 to 7, then the longitudinal field strength in the acceleration section is particularly large, which is why particularly low voltages are sufficient to charge the memory gate G.

In special cases it is advantageous to mount a capacitively coupled control gate GH above the memory gate G, see FIG. 9. The coupling is created by the small distance between the two gates, see Fig. 9. Any potential can be fed to the control gate GH at the lead out connection GHA of the control gate GH. You can therefore press any potential ^r ) on the capacitively coupled memory gate G of your choice via the connection GHA, e.g. B. to generate acceleration voltages or braking voltages of any size between the memory gate G and the acceleration path in the channel. With the help of the GHA connection you can charge the storage gate G or

ίο the compensation of charges present there

heated charge carriers of the acceleration section

control, even if the memory gate G

already stores a certain charge.

The ones heated up in the acceleration section

Charge carriers, generally electrons, can also be used to erase, that is, to discharge the memory gate G, if the memory gate G has previously been used in any way, e.g. B. by means of the avalanche effect, charged with charges of opposite polarity

was. Because of the high number of charge carriers heated up in the acceleration section, this takes place here the discharge of the storage gate faster than if no acceleration path were installed in the channel.

For this purpose 2 sheets of drawings

Claims (9)

Patent claims: 1. Memory field effect transistor (memory FET) with a memory gate which is surrounded on all sides by an insulator, and with a semiconductor substrate in which a source region and a drain region are arranged and delimit a channel region in the longitudinal direction, and in which During operation, the charge state of the memory gate is changed by supplying charge carriers from the channel area by applying such a voltage between the source area and the drain area that charge carriers from the conductive channel area pass through the insulator to the memory gate (channel injection) , in particular for the program memory of a telephone switching system, characterized in that at least one locally limited acceleration path (V) is arranged in the channel area (K) , which is formed by a structural inhomogeneity and which has the effect that during operation by the between the source area (S ) and the drain region (D) applied voltage to the charge carriers in the longitudinal direction of the Canal ^ are accelerated. 2. Memory FET according to claim 1, characterized in that the structural inhomogeneity consists in that the memory gate (G) has at least one region in which its width (V) measured transversely to the longitudinal direction of the channel region (K ) is at most half its maximum Width is, so that the channel area (K), which is defined in its width by the shape of the memory gate (G), has at most half of its maximum width in the region (V) mentioned. 3. memory FET according to claim I or 2, characterized in that the Aulbnmnhomogcnität is formed at one point of the channel by a thickening (Vd) of the insulator (A) between Speichergale (C) and substrate ^ (F i g. 9) . 4. Memory FET according to one of the preceding claims, characterized in that the structural inhomogeneity (V. Vd) is attached to one end of the channel. 5. Memory FET according to one of the preceding claims, characterized in that the structural inhomogeneity (V, Vd) is attached in the center of the channel (F i g. 5 and 6). 6. memory FET according to one of claims 1 to 3, characterized in that the structural inhomogeneity (V. In the meantime, the channel end and the center of the channel is attached. 7. memory FET according to claim 4 or 6, characterized in that two such structural inhomogeneities are provided, one of which is attached on the drain side from the channel center (Vl) and the other on the source side from the channel center (V2) (Fig. 7). 8. memory FET according to any one of the preceding claims, characterized in that its channel is at most a few μιη long. 9. memory FET according to one of the preceding claims, characterized in that a Sieuergaie (GH) is arranged above the Speichergatc (C).