DE2744194C3 - - Google Patents

Description

The invention relates to a further development of the subject matter specified in the main patent 2445077.9 and further developments specified there, i.e. an electronic one produced using integrated technology

3 ·, storage element with two FETs, the main lines of which are connected in series, the first being called FET Memory FET, having an insulated floating gate and being electrically programmable, and the second FET, called a read FET, at its gate through a

4 (i control voltage is controllable and where the substrates both FETs are separated from each other by insulation. Such a storage element allows in particular the reject rate in the production of such memory elements

4- to diminish memory chips by adding relatively large tolerances to the operating voltages in spite of this high permissible clock frequencies are permitted. The memory FET is in the main patent especially a FAMOS-FET, i.e. one

-, o tax-gateless programmable by means of the avalanche effect Storage FET.

By z. B. DE-OS 2445078, 2445 079 and 2445 137 is an n-channel memory FET or p-channel memory FET with a completely isolated and

-, =, therefore floating, by channel injection instead of by Avalanche effect chargeable storage gate as well as an additional, capacitive storage gate acting, known by a control potential controllable control gate. He has the advantage of not having an in

wi need to read FETs connected in series, as especially in DE-OS 2445078 and 2445 137 is described. The programming voltage required for programming is particularly low because of the channel injection used. The storage cell

, contains only a single FET here, namely this one special memory FET. The control gate facilitates the operation of the memory FET both for reading, as well as programming and still opens the

Possibility to extinguish electrically.

DE-OS 2513207 is a modification this special memory FET with an η-channel is known there, namely in which the memory gate and a first TeQ of the control gate only covers a first channel part close to the drain, but in which the other part of the channel close to the source is only covered by the rest of the control gate. This modification is planned The main advantage is that the memory gate is also excessively discharged when erased, i.e. also positively charged without disrupting normal operation. This modification is also for use provided in a 1-FET memory cell, see in particular DE-OS 2525062. This special modification can also be relatively easy for itself as a 1-FET memory cell on an insulator, e.g. B. sapphire, be appropriate as a carrier, in particular the To improve isolation between individual memory cells and to reduce the source-drair breakdown voltage and to reduce the sub-threshold currents, which also reduces the production reject rate reduced, see the (not previously published) DE-OS 2643148.

All of these memory FETs programmable by channel injection are therefore each individually as 1-FET memory cells, which do not have any additional Read FETs need suitable because they are each highly blocking due to the charging of the memory gate State can be controlled. Especially in this particularly simple, space-saving structure of the 1-FET memory cell an important advantage of such a memory FET was seen. It therefore existed initially there is no reason to use this memory FET suitable for a 1-FET memory cell with a to connect further reading FETs that require a controller and space in series.

It turns out that, surprisingly, the clock frequency increases and also during operation of the memory cell the scrap rate in the manufacture of such channel injection programmable n-channel memory FETs can be reduced if the memory FET in question is programmable by channel injection is attached to an insulator as a carrier and if contrary to the usual practice in series with a source-drain path each have a read FET, which in turn is controlled by a Gate is influenced, is switched when the memory FET is so despite its general suitability mounted as a 1-FET memory cell in a 2-FET memory cell mounted on an insulating carrier is. Because of the use of an insulator as a support and the possible use of a special one thin epitaxial silicon layer as material for the source-drain path of the two FETs one Memory cell can also make the channel of the memory FET particularly short and thus with special low programming voltages, without source-drain breakdown voltages in dangerous way to lower and / or to increase sub-threshold currents in a dangerous way without affecting the reliability of the operation of the memory cell.

The invention is based on the electronic storage element cited above and specified in the main patent with two FETs.

With the invention, this storage element is developed so that it can operate with particularly low operating voltages can be programmed.

ι ο

In the case of the electronic memory element with two FETs, this development is achieved in that its memory FET is a memory FET programmable by means of channel injection with an additional, controllable by a control potential, capacitively acting on the floating gate, called the memory gate Control gate is.

The invention therefore also relates to a memory FET because of the additional attachment of the control gate n-channel or p-channel and with at least two gates, namely with the control gate and the memory gate. Significant differences to the known 2-FET memory cells that utilize the avalanche effect can be seen in the fact that the channel influenced by the memory gate is in its blocking instead of conductive state is controlled, so that at first it even appeared that the Read FET would always be superfluous, with the operating voltages required for programming because of the Use of channel injection are particularly low.

The measure according to the invention reduces the reject rate of highly integrated memories such memory FETs in 2-FET memory cells are also reduced by the fact that a non-programmed Memory FET, the memory gate of which is therefore uncharged, due to the statistical fluctuations in the Manufacture and operation of such memory FETs e.g. B. instead of the often intended enrichment type characteristic even an unintended conductive channel between its source-drain path as a depletion-type FET may have, i.e. it may also be extinguished excessively without the Endanger the operation of the storage facility. Namely, if a first storage FET and yet another storage FET - possibly even several others - each without a read FET connected to the same read line are, and if this other memory FET has a conductive channel and thereby a conductive connection to a power source, although it is only unprogrammed and is therefore in the "O" state, this conductive channel incorrectly indicates the "O" state of the first selected for reading Memory FET pretend to be when its memory gate is netatively charged and therefore in the "1" state. The selected, first memory FET then correctly supplies the read “1” status signal "No current", but the other - or the other storage FETs with unintentionally conducting Channel unintentionally deliver the simulated, superimposed »O« status signal »Strom flows "so that what appears to be a" 1 "state signal is being read from the first memory FET. The reject rate in the production of the memory cell is thus also reduced in the invention in that statistical fluctuations in the properties of the other memory FETs are made harmless, by placing a read FET in series with the memory FET influenced by the memory gate. The channel of the read FET of the other memory FET is namely when reading the first memory FET, as known from 2-FET memory cells, controlled in its non-conductive state, so that a in itself inadvertently conducting channel of this other memory FET no incorrectly read signal can pretend more.

Compared to the aforementioned known modification of the memory FET, which is also excessively erased

may be, the memory cell according to the invention has the advantage because of the insulator serving as a carrier the potentials in the substrates of the read FET or the channel part close to the source, on the one hand, and of the memory FET On the other hand, to separate the channel part close to the drain and thereby an increased clock frequency during operation with good isolation of the individual storage cells from one another, despite a reduction in the sub-threshold currents and source-drain breakdown voltages and thus despite a reduction in the reject rate, ι ο to allow. The production can also be carried out particularly easily, i.e. the reject rate can be kept relatively low, as will be explained.

The ones in the. DE-OS 2513207, 2525062, 2643948 v> shown remedial measure to allow the excessive discharge of the memory gate, namely to attach the memory gate only to the channel part near the drain, namely affects the reject rate, because they used relatively high demands on the tolerances of the production of various Masks and the tolerances of the adjustment of these masks during the production of the memory FET - requirements that can be less high with the invention.

The invention improves the reject rate in particular in that despite the unavoidable statistical Fluctuations in the properties of the various memory cells in a large memory matrix, Disturbances can be rendered harmless or reduced, which otherwise in particular through high requirements of tolerances, through excessive cancellation, through sub-threshold currents and / or through Source-drain breakdown voltages, so-called punch-through, can occur.

If both FETs have p-channels, they can be attached in p-channel circuits using the same technology due to the particularly thin epilactic silicon layer permitted here, high Source-drain breakdown voltages and because of the allowable particularly short channel of the memory FET particularly low programming voltages are possible. Namely, p-channel memory FETs need because of The particularly high energy threshold for holes at the channel / insulator boundary layer is otherwise inconvenient in itself high programming voltages.

If, on the other hand, an n-channel memory FET is used, the dimensions can otherwise be the same Even lower amounts for the programming voltages can be allowed without the operation affect the memory cell.

The additional control gate attached to the invention facilitates the operation of the memory cell, especially because the increased capacitance that would otherwise have to be applied between the drain and the memory gate, which creates problems with very short channels, can be omitted.

The invention and developments thereof are described in more detail with reference to the figure, which one Figure 10 shows a longitudinal section of an n-channel embodiment of the invention. By using the same As in the main patent, the present description can essentially refer to the Further-developing features that relate to the invention and its further developments are restricted. (, 5

The figure shows the electrically floating memory gate surrounded on all sides by an insulator Gl in the memory FET 71. which has an n-doped source S1, a p-doped substrate and an n-doped Has drain Dl. The controllable control gate G2 ', which is the memory gate Gl influenced capacitively via a thin insulating layer.

The memory cell shown in the figure also contains the read FET 72, which in this exemplary embodiment also contains an η-channel.

The embodiment shown thus contains two controllable gates G2 and GI ', which can be controlled separately for reading, programming and possibly also electrically controlled erasing. 72 is controlled preferentially and conducting when voltage is to be applied to the source-drain path of the memory FET 71. But you can also conductively connect the two controllable gates Gl, G2 'to each other and control both together by a control potential, this development then working similarly to the modified memory FET according to DE-OS 2513207, 2525062, 2643948, but with the difference that because of the galvanic separation of the substrates of the two FETs 71, TZ an increased clock frequency is achieved - apart from the particularly easy producibility in comparison to that modified memory FET. An essential difference to known 2-FET memory cells is, as already mentioned, that the invention is a memory cell in which the memory gate G1 of the memory FET 71 during programming with the aid of which only requires particularly low programming voltages Channel injection is charged so that the channel of the memory FET 71 is controlled in the blocking, instead of in the conductive state. Accordingly, the read signals, ie "no current" / "current flowing", have the inverted size compared to a memory FET programmed by the avalanche effect.

If the two controllable gates GZ, GZ 'are not directly connected to one another in a conductive manner, but are controlled separately, the clock frequency for operating such a memory cell and therefore also when operating memories made up of such memory cells can be increased further. The overall effective capacitance: on the connecting lines of the memory, which supply corresponding steeper potentials to the relevant gates GZ, GZ ' , is then reduced so that the transient state between two successive clocks is correspondingly shorter in time. The shortening of the settling time in question allows the clock frequency to be increased when operating such memories.

In addition, the separate control of the two controllable gates GZ, GZ ' allows both gates to be supplied with different potentials. In particular, in such a case, significantly higher voltages can be applied to the read FET 72 than to the memory FET 71 during the programming process. This has the advantage that the read FET 71 conducts particularly well during the programming process and thus often has a particularly low voltage drop between S2-D2 even with a narrow channel width, so that a particularly high voltage is then between S1-D1 and therefore the The heating of the charges in the channel of the storage FET 71 during the channel injection turns out to be particularly strong, which facilitates the charging of the storage gate G1.

The n-channel output shown schematically in the figure

management example you can z. B. using the teaching given in DE-OS 2445030 manufacture in the following way:

An epitaxial silicon layer, which is p-doped, is grown on the insulator Saph, which is used as a carrier. Then all of the silicon layer parts that are not required and that do not belong to the source-drain paths of both FETs 71, 7 "2 are etched away again. A first thin insulating layer is then grown over the entire surface, e.g. with a thickness of 600 A. A first polysilicon layer is then allowed to grow, which is still doped, for example p-doped, and which is then etched away again with high permissible tolerances, with the exception of the areas belonging to the memory gate G1 and the adjacent, overhanging edge layers What remains is the memory gate G1 together with temporarily adjoining edge layers, these edge layers now covering parts of the later source 51 and the later drain D1 of the memory FET 71, but not having to be of a specific size themselves compared to the relatively tight corresponding tolerances in the aforementioned modified memory FETs Projecting edge layers are only etched away later, as will be described below.

Next, a second m insulating layer is created on the remaining first polysilicon areas and on the parts of the first insulating layer that are still exposed, e.g. B. with a thickness of 500 A. A second polysilicon layer is grown on this second insulating layer 11 , from which the control gate G2 'and the gate G2 are formed by etching away using a mask. By using the same mask as J5, you can also etch away those areas of the first and second insulating layers and the protruding edge layers that previously covered the later areas of drain D1 and source 51, so that memory gate G1 and control gate G2 are now particularly precisely layered on top of one another which also reduces the reject rate for itself.

Then you can, for. As by diffusion, but mainly by means of ion implantation under encryption 4 ^r, application of the controllable gates G2, G2 'as a mask, the dopant, here η-doping of the regions Dl, 51, D2, produce 52nd At the same time, the polysilicon of the controllable gates G2, G2 'is doped in the same way and thus conducts well. The use of ion implantation instead of diffusion has the main advantage that the underdiffusion of the source and drain under the gate area can be largely avoided, so that very short channels of a well-defined length with narrow tolerances of the length are possible, which in itself reduces the reject rate, especially when using a large number of such memory cells in a highly integrated module.

The figure shows the manufacturing state that has now been reached. The respective p-conducting substrate on the carrier Saph here is flanked by the n-doped regions 51, D1, 52, D2. Between the gate G2 of the read FET T1 and its substrate is the insulator made up of parts of the first and second insulating layers. Between the control gate G2 'and the substrate of the memory FET 71 there is a remaining part of the second insulating layer, the first one Polisilicon layer Gl and the first insulating layer. A plurality of such n-channel memory FETs can be mounted simultaneously on the carrier Saph and form a memory.

A first protective oxide layer can still be found on the entire surface in the state shown in the figure let grow up, in which, if necessary, contacts for the areas 51, 52, Dl, D2 and attaches for the controllable gates - if one does not have neighboring, equally doped and on the same Areas with potential, e.g. B. D2, 51 as a single contiguous doped equal Area produced, which reduces the space required and also the requirements for masks. Afterward you can use metal vapor deposition to connect the connecting lines of the module, as well as create a second protective oxide layer on top.

In order to reduce the thickness of the insulator between the gate G2 and the substrate of the read FET Tl , the manufacturing process can be modified, e.g. the later application of the second insulating layer adds a further process step, namely an etching away of all now exposed parts of the first insulating layer by means of the remaining parts of the first polysilicon layer as a mask or by means of the mask that was used to shape these remaining parts the gate G2 and the substrate of the read FET Tl only consist of the second insulating layer. As a result, the control voltages at the gate G2 can influence the channel of the read FET Tl more intensely in a manner that reduces waste.

1 sheet of drawings

Claims (6)

Patent claims: 1. Electronic memory element manufactured using integrated technology with two FETs whose main lines are connected in series, the first FET, called a memory FET, having an insulated floating gate and being electrically programmable, and the second FET, called a read FET, on its gate can be controlled by a control voltage and the substrates of both FETs are separated from one another by insulation, according to patent 2445077.9, characterized in that its memory FET (71) is a memory FET programmable by channel injection with an additional memory FET Control potential controllable, capacitive on the floating gate (Gl), called memory gate (Gl), acting control gate (Gl ') . 2. Memory cell according to claim 1, characterized in that one connection area (D2) of the read FET ( TT) and the connection area (S1) of the memory FET (71) conductively connected therewith form a single common doped area. 3. Memory cell according to claim 1 or 2, characterized in that the memory FET (71) has a p-channel. 4. Memory cell according to claim 1 or 2, characterized in that the memory FET (71) has an η-channel. 5. A method for producing the memory cell according to any one of claims 1 to 4, characterized through the following process steps: a) A silicon layer is epitaxially applied to an insulator (Saph) as a carrier, which is doped and etched away again except for the source-drain sections (51-Dl, Sl-Dl) of both FETs; b) at least over the entire area of the remaining silicon layer mentioned is a produces a relatively thin first insulating layer; c) at least on this entire surface a first polysilicon layer is deposited, which is additionally endowed; d) the first polysilicon layer is essentially down to the required area of the Memory gate (Gl) etched away, but initially adjacent to the memory gate (Gl) another protruding edge layer in the over the later source (51) and over the later drain (Dl) of the memory FET (71) located region extends into; e) at least on the entire surface mentioned is a relatively thin second insulating layer generated; f) a second polysilicon layer is deposited at least over the entire surface; g) the second polysilicon layer is etched away by means of a mask down to the required areas of the two controllable gates (Gl, GT); h) with the mask used to form the two controllable gates ( Gl, GT) in method step g , the edge layers of the first polysilicon which reach over the later source (51) and over the later drain (Dl) of the memory FET (71) are layer and the unneeded parts of the first and second insulating layer are etched away: i) doping of the parts of the second polysilicon layer corresponding to the two controllable gates (Gl, GT) and doping of the silicon layer on their exposed surfaces for producing the sources (51, 52) and drains (Dl, Dl) is applied; k) at least over the entire surface, a first protective oxide layer, furthermore by means of contact windows, if necessary, contacts for the drains (Dl, Dl), sources (51, 52) and gates (G2, G2 '), as well as the necessary connecting lines by means of metal vapor deposition manufactured; 1) A second protective oxide layer is produced at least over the entire surface. 6. The method according to claim 5, characterized by the addition of a further process step between process steps d and e: dl) The parts of the uncovered by the remaining parts of the first polysilicon layer first insulating layer are etched away.