DE2744113A1 - N-channel storage IGFET with floating gate - has between drain and source N-doped auxiliary region in series with channel followed by further channel region - Google Patents

Abstract

The floating storage gate is surrounded by an insulator. The gate charge change is carried out by electrons highly accelerated and heated in the transistor channel (K). The electron heating overcomes the energy threshold to the insulator conductivity band, owing to an electric field effective in the source (S)-drain (D) direction. Thus the electrons reach the storage gate and program the channel injection, thus charging the storage gate to a potential, negative relative to uncharged state, as in 2445137. Between the source and drain is incorporated an n-doped auxiliary region (HS) in series with the channel, behind which is provided a further chanel region (Ka) with a selector gate (Ga2), insulated from and affecting this channel region.

Description

n-channel recorder w.

The invention relates to a development of the in the main application / in Main patent P 24 45 137.4-33 specified objects, all of which have a certain n-channel memory EETs relate to an n-channel memory FET with at least a gate, namely with a floating gate surrounded on all sides by an insulator Storage gate, in which the electrons injecting charge reload the storage gate Canal injection - d. H.

Reloading through strongly accelerated and in its own conducting channel as a result, electrons are heated, which because of their heating by a in the source-drain direction effective electric field the energy threshold to the conductivity band of the insulator overcome and thereby get to the storage gate -is exploited with the task of the channel injection for programming, i.e. charging the memory gate on an opposite the uncharged state negative potential, so that the memory gate after this charging by means of its negative charge due to influence in the source-drain current acts inhibitory manner on the source-drain path.

This n-Kvanal-S? Oak FET is thus charged by charging its Memory gate controlled in the (strongly) blocking state. Has this n-channel memory FET only a single gate, namely the memory gate, and an enhancement type channel then one can, for programming as well as for reading the unprogrammed n-channel memory FET, as described in the main application / in the main patent, make the channel conductive, by shifting the memory gate potential in a positive direction - e.g. supported by a capacitive additional overlap of the drain and the memory gate. This programming and reading is made easier if there is also a control gate is attached, which capacitively influences the memory gate potential. To use of the n-channel memory FET in memory matrices, no 2-FET memory cells are required, but actually only 1-FET memory cells. As in the main application / in the main patent is described, it is sufficient to use only the n-channel memory FET in each case to be used as a memory cell of a memory matrix, see Fig. 4 of the main application / des Main patent. Especially in this particularly simple, space-saving structure an often particularly important advantage of such an n-channel memory FET.

2-FET memory cells in which in particular a floating Memory FETs having a memory gate each have a selection FET or read FET connected are, when using FBIOS memory FETs and SAMOS memory FETs in one Numerous literature references are described, cf. in particular DT-OS 24 45 C77 = VPA 7k / 5186 as well as the one there and that in the DT-OS 24 45 C78 = VPA 74/5187 State of the art.

It turned out that, surprisingly, the reject rate at the Production of the n-channel memory FET described in the main application / in the main patent can be reduced if the n-channel memory FET is contrary to previous practice in series with its channel each has a further channel area, which in turn is from a controllable select gate is influenced, contains.

The invention is therefore based on the n-channel memory FET specified in the main application / in the main patent. The n-channel memory FET according to the invention is characterized in that between the source and the drain in series with its channel an n-doped auxiliary region and, behind it, a further channel region with a further channel region influencing this further channel region, isolated from this further channel region , controllable selection gate are inserted. The invention thus relates to an n-channel memory FET with at least two gates, namely with the memory gate and with the selection gate, so that this FET link its channel and its reichs represents a special kind of tetrode. In terms of its structure, the invention thus corresponds to a 2-FET memory cell. An essential difference to the known 2-FET memory cells is that the channel influenced by the memory gate is controlled in its blocking state when the memory gate is charged, so that it initially appeared that the further channel area would be superfluous because an in Memory gate that can be charged in this way allows the n-channel memory FET to be used alone without any further channel area within a 1-FET memory cell.

The measure according to the invention can reduce the reject rate of highly integrated Storage with n-channel memory FETs are reduced in particular in that a non-programmed n-channel memory FET with its memory gate uncharged is due to the statistical fluctuations in the manufacture and operation of such n-channel memory FETs e.g. instead of the often intended enhancement type characteristic even an unintended conductive channel fish its source-drain path as a depletion-type FET may exhibit without jeopardizing the operation of the memory. Namely, if a first n-channel memory FET and still another n-channel memory FET - possibly even several others - each without the measure according to the invention with the same read line are connected, and if this is another n-channel memory FET a conductive channel and thereby a conductive connection to a power source although it is only unprogrammed and is therefore in the "O" state, this can leading channel falsely- indicate the presence of the 0 "state of the first n-channel memory FET selected for reading, if its memory gate negatively charged and therefore in the "1" state, pretend.

The selected first n-channel memory # ST then supplies as read "1" status signal correctly no current ", but the other - resp. the other - n-channel memory FETs with inadvertently conducting channel inadvertently deliver the only simulated, superimposed "OG" state signal ~ current flows ", so that apparently the "1" status signal is read from the first n-channel memory FET. The reject rate in the manufacture of the n-channel memory FET is thus in the invention reduces that statistical fluctuations in the H properties of the other n-channel memory FET can be made harmless by adding an additional, independently controlled channel area in series with the channel affected by the memory gate of the n-channel memory FET is.

Namely, the further channel area of the other n-channel memory FtT becomes when reading the first n-channel memory FET, as for 2-FET memory cells known to be controlled in its non-performing state, so that a per se unintentional no conducting channel of this other n-channel memory FET because of the AND operation wrong read signal can fake it more.

Especially with a deleted one - e.g. with TJ light - so again unprogrammed n-channel memory FET is made possible by the invention that without Fault in memory operation - e.g. by the DT-OS 25 I 207 = VPA 75P6039 known per se - excessive deletion of the memory gate is permitted, so that The invention allows the channel to conduct even at zero source-drain voltage, ie E.g. the storage gate is not electrically as intended after discharging neutral, but positively charged with holes or in traps of the Isolator holes may be trapped, yes that even a depletion-type channel through a thin n-doped layer between the source and the rain or the auxiliary area may be attached - even if on one main line connection, e.g. the source, a current source, e.g. ground, is constantly connected. The one in the DT-OS 25 13 207 shown remedy to the excessive discharge of the memory gate to be able to allow, namely the memory gate only under a certain part of the Attaching a control gate affects the shot rate because it sets relatively high demands on the tolerances of the production of the masks used as well as the tolerances of the adjustment of these masks during the manufacture of the n-channel memory FET ahead - requirements that are less stringent with the invention even if there is an additional control gate above the storage state attached, as outlined in the below-described method of making a such ti ## formation of the invention can be seen.

Another circumstance lowers the reject rate when applying the measure according to the invention. Especially if a channel with a particularly short channel length there is often some sub-threshold current inadvertently occurring on, as soon as there is a high positive bias at the drain related to the source potential, especially if there is also a control gate attached to which, based on the Source potential no bias, namely e.g. Nasse, is. This mode of operation is especially important if the n-channel memory FET is in a memory array is attached, with a first selected n-channel memory FET being programmed will and. one or more other n-channel memory FETs at the drain with the Drain of the first n-channel memory FET are connected and in turn not programmed and should not be programmed in and of themselves. Such non-programmed ones other n-channel Steicher-FETs then show - especially because of the statistical Variations in the properties of the multitude of n-channelÆstorage F ~ Ts that are in the store are attached - sometimes quite considerable sub-threshold currents. In such other n-anal memory 7rTs can sometimes also by so-called ~ punch-through " a further sotirce drain current undesirably occur. Such subliminal oil flows as well as punch-through currents of the other n-channel memory FETs cause the total currents, that flow in the connecting line connecting the drains, sometimes considerably become large, e.g. often a multiple of the source-drain current of the program to be programmed first n-t2nal-o? eicher-FET can be. The fact that according to the invention between the source and the drain another channel area in series to the source-drain path of the n-channel memory FET, with these further, i-channel areas at unselected n-channel memory FET during programming of the first n-channel memory FETs can be controlled in the non-conducting state by themselves, such sub-threshold currents and punch-through currents can be effectively suppressed will.

In this way, because of the invention in the relevant, the connecting line connecting the drains to one another is only the one for programming required source-drain current of the first n-channel memory FET, so that the voltage drop relative to the FETs of the edge electronics of such a memory that are effective in series remains small. The smaller this voltage drop in the edge electronics, the more so the first n-channel memory FET is programmed more reliably.

The one placed between the source and the drain in the invention n-doped auxiliary area allows especially simple manufacturing processes for Fabrication of the gates apply as from the fabrication process examples described below emerges.

The invention thus improves the reject rate in particular by that despite inevitable statistical fluctuations in the properties of the various n-channel memory FETs rendered interference harmless in a large memory matrix which otherwise, in particular, due to high demands on tolerances excessive cancellation, by sub-threshold currents and / or by punch-through currents can still occur.

The invention and further developments thereof are illustrated with the aid of the figures 1 and 2 described next, which are a longitudinal section and a plan view of a Show embodiment of the invention. By using the same symbols as in the main application / in the main patent, the present description essentially on the further developing features, the invention and its further developments concern, restrict.

Figure 1 shows that surrounded on all sides by an insulator, in electrical Regarding floating memory gate Gl and the source-drain path S-D. Between the The channel influenced by the memory gate GI lies in the auxiliary area HS and the drain D K, the length of which in the present example is used to reduce the programming time required voltage is relatively short, namely only 3. Then this channel is but also so long that the requirements placed on the masks during manufacture this example are therefore relatively small.

The n-channel memory FET shown in FIG. 1 also includes the in series with the channel K effective further channel area Ka, which in this case as well is only 3 P long. This further channel region Ka lies in the exemplary embodiment shown between the source 5 and the auxiliary area HS. This auxiliary area itself points in contrast, in this embodiment, no connection of its own to the outside world to the source 5 and to the drain D, as indicated in the figure. Also with the Invention not always provided control gate G2 and always with the invention provided selection gate Ga2 influencing the further channel region Ka are from externally controllable, as is also indicated in FIG. 1.

The embodiment shown thus represents a tetrode in particular Type, which has namely two separate goods Ga2 and G1, with those of these Good affected areas K, Ka are in series with one another and therefore perform an AND operation in the source-drain path S-D. Because this Source-drain path o-D only conducts if each of the two, from gates Ga2, G1 governs areas K and Ka influenced by itself, corresponds to the shown n-channel memory FET a 2-FET memory line. A major difference to known 2-FET memory cells is, however, that the invention is an n-channel memory KET acts whose memory gate G1 when programming with the help of channel injection is negatively charged and its channel K by the charging in the blocking, instead of being controlled into the conductive state.

The further channel area Ka prevents due to the OT link in its non-conductive state, that in the event of excessive erasure of the memory gate G1 a current flows through the source-drain path S-D, which, as described above, to simulate ~ O "states during the reading process of other n-channel memory FETs could lead. The further channel area Ka also prevents due to the AND link in its blocking state, unintentional sub-threshold currents or punch-through currents in channel K and thus in the source-drain path S-D, which do the programming other n-channel memory FETs.

It is favorable that the one shown in FIG. 2, not shown in FIG. 1, is advantageous The width of the further channel region Ka is as large as possible compared to that in FIG. 2 shown, not shown in Fig. 1 width of the channel K so that during When programming this n-Xanal memory FET, the lowest possible voltage drop occurs at the other channel area Ka and thus as possible the entire voltage over the conductive source-drain path S-D then tube ~ the channel K occurs. The lower namely the voltage drop at the further channel area Ka compared to the voltage drop is on channel K, the more intense the heating of the electrons in the conductive channel K during programming so that the intended negative Charging of the storage gate Gi then occurs particularly reliably. One can e.g. Think of a ratio of the channel widths of 10: 1 and even more, so that the space requirement is there for this development, vie Fig. 2 shows, essentially by the width of the further channel area Ka, but only insignificantly due to the space required by the channel K of the n-channel memory FET is conditional. This dimensioning is special then Recommended if the n-channel memory FET is installed in a memory module which contains only relatively few such n-channel memory FETs, so that the space requirement less important than the high reliability and the reduced reject rate is. This exemplary embodiment is therefore particularly suitable for memory chips with only e.g. 1024 or 256 memory cells, which are used to store short programs are often sufficient.

If the invention only the floating memory gate G1, but not also has the control gate G2 shown in Fig. 1, the structure is special simple. This embodiment is relatively fast with the help of ultraviolet Light can be extinguished because there is no control gate over it that casts a shadow G2 is present. To make such an embodiment particularly reliable as a memory cell To be able to operate, it is sometimes advisable to have a sufficiently amplified capacitive coupling between the memory gate G1 and the drain D, e.g. by especially large overlap of these two areas, as in the main application Main patent is indicated. This ensures that, when programming it during the start of charging, the storage gate potential by means of the drain potential is made so positive that it reliably puts the channel K in the conductive state controls and that the memory gate Gl also the electrons heated in the channel K attracts and thus promotes its charge. By such a sufficient capacitive Coupling between the drain D and the memory gate G1 is particularly reliable this channel K when reading and when starting programming in the unprogrammed State of the memory FET - at least weakly - conductive, but at the Read in the programmed state of this memory FET reliably non-conductive, even if the channel K is of the enrichment type due to its doping or structure is - but especially if he is of the impoverishment type.

However, if the n-channel memory FET, as shown in FIG Has an additional, controllable control gate G2, it is not necessary to have a capacitive Coupling between the drain D and the memory gate G1 and / or a depletion type channel K to attach in the unprogrammed state during the reading process the ~ O "state signal ~ Current flows "or a conductive state of the channel at the beginning of programming K to get. A suitable potential can then be applied to this control gate G2 through which the channel K becomes conductive if the n-channel memory FET is not programmed in each case, and in which the channel K is non-conductive, if the n-channel Spencher-RET is programmed.

As will be described below, the requirements for the tolerances are of masks in the production of the precisely stacked gates G1 and G2 pleasantly low. The manufacture of the n-channel memory FET with control gate is also simply because the channel K can be of the enrichment type, that is to say of the same Type, like the further channel area Ka shown in FIG. 1.

Because the control gate G2 and the selection gate Ga2 are not directly The clock frequency can be conductively connected to one another but can be controlled separately to operate such an n-channel memory FET and therefore also to operate off memories constructed in such n-channel memory FETs can be increased. The total effective capacitance on the connecting lines of the storage tank that connect the relevant Supply selection gates Ga2 or the relevant control gates G2 corresponding potentials, is namely reduced, so that the transient state between two successive Clocking is correspondingly short in time. The shortening of the respective settling time allows the clock frequency to be increased when operating such memories.

It also allows the two controllable ones to be controlled separately Gates G2, Ga2 to supply both gates with different potentials. In particular one can in such a case between the auxiliary area HS or the source 5 on the one hand and the selection gate Ga2 on the other hand, significantly higher voltages than between the Drain D on the one hand and the control gate G2 on the other hand during the programming process invest. The advantage of this is that during the programming process, the further kenal area Ka is then particularly good conductive and thus often even with a narrow channel area width has a particularly low voltage drop, so that the heating of the electrons in the conductive channel K during the channel injection, what turns out to be particularly strong the charging of the storage gate G1 is facilitated.

Because the auxiliary area HS is used to limit the channel at the same time K as well as to delimit the further channel area Ka is used by it directly adjacent to these two areas, as shown in the figure, can you save special conductive connections that would have to be attached if you the channel K on the one hand and the further channel region Ka on the other hand, in each case different, own auxiliary areas would limit what would be possible in itself. Furthermore this brings the channel K and the further channel area Ka jointly delimiting only auxiliary area HS has the advantage, particularly little space on the surface of the substrate HT to need. In addition, such a single auxiliary area enables HS to use relatively simple masks in making the n-channel memory FrT.

Especially if the capacitance between the auxiliary area HS and the Substrate HT - for whatever reason, e.g. because of the large width of the channel area - is large, when programming another n-channel memory FET, its drain is directly connected to the drain of the first n-channel memory FET, a malfunction occurs: while programming the other n-channel memory FET namely, there is also positive potential at the drain D of the first n-channel memory FET, during the Auxiliary area HS of this first n-channel memory FET still approximated to the potential of the substrate HT, i.e. e.g.

at ground potential. Even if the further channel area Ka at this time is controlled in its non-conductive state, flows between the Auxiliary area HS and the drain D in the channel K a powerful, the high capacity between the auxiliary area HS and substrate HT charging current, if the channel K is conductive is, e.g. if so during this operating state - for whatever reason - additionally the potential of the control gate G2 subsequently changed in a positive direction will. Because of the conductivity of the channel K can namely through the high capacitance a channel injection between the auxiliary area HS and the substrate HT charging current and thus a partial charging of the storage gate G1 can be triggered. The disorder is that each time a different n-channel memory FET is programmed even accidentally partially recharging the Memory gate G1 of the first n-channel memory FET with electrons can enter, until this memory gate G1 is finally charged quite strongly and negatively simulates an intentional programming of this first n-channel memory FET. This disruption can be reduced or avoided in particular by the fact that between the auxiliary area HS and the drain D, parallel to the channel K, or between the auxiliary area HS and a positive voltage source, a high-resistance resistor is inserted, over which the auxiliary area HS to the potential of the drain D in harmless Way is charged as long as the further channel area Ka at least largely is controlled in its non-conductive state.

The one shown schematically in the figures, having a control gate G2 The embodiment example can be produced in the following way, for example: On the p-conducting Substrate HT is first allowed to grow on a thick oxide layer. Then it is etched a window in the thick oxide layer you along the entire surface and length GL of the source-drain path S-D of the n-channel memory FET, so that the substrate HT is openly accessible again there. Then leave a first layer of insulation, namely grow a thin oxide layer 11 on this entire area of the window, e.g. with a thickness of 6002. Then a first polysilicon layer is grown, which are still endowed and which are then restored with high permissible tolerances etched away with the exception of the protruding parts to the memory gate G1 and the adjoining it Edge layers G1s that are not yet etched away.

What remains is the memory gate G1 together with temporarily adjoining edge layers G1 ', these edge layers G1' now partially and do not have to have a particular size themselves. These protruding edge layers G1 'are only etched away later, as will be described below.

Next one leaves on the polysilicon areas Gl, G1 'and on the parts of the first insulating layer II that are still exposed, a second insulating layer 12 arise, e.g. with the thickness 5002. On this second insulating layer 12 one leaves a second polysilicon layer grow, from which by etching away by means of a Mask the control gate G2 and the select gate Ga2 is formed. By taking advantage of the The same mask can also be used for those areas of the insulating layers 11, 12 and etch away the protruding edge layers G1 ', which were previously the later areas Covered by drain D, source 5 and auxiliary area HS, so that the memory gate G1 and the control gate G2 are particularly exactly layered on top of each other, what also for the reject rate is reduced.

Then you can, for. B. by means of ion implantation using of the control gate G2 and the selection gate Ga2 and the print oxide layer Du as a mask, generate the n-doping of the areas D, S, HS. At the same time, the polysilicon is used of the control gate G2 and the selection gate Ga2 are n-doped and are therefore highly conductive. Instead of The use of ion implantation can also be used by diffusion in a well-known manner Way the Generate n-doping of the areas D, S. HS, at the same time an n-doping of the parts of the polysilicon layer, which the control gate G2 and the Select gate Ga2 form is achieved.

The manufacturing state now reached is shown in FIG. 1.

The n-doped regions D, S, HS are in the p-conducting substrate HT generated. The is located between the selection gate Ga2 and the further channel area Ka insulator constructed from parts of the first and second insulating layers 11, 12. Between the control gate G2 and the channel K lies a remaining part one after the other each of the second insulating layer 12, the first polysilicon layer Gl and the first insulating layer I1. The source-drain path S-D of this n-channel memory FET is surrounded by the thick oxide layer Du. A variety of such n-channel memory FETs can be attached to the substrate HT at the same time and form a memory. By using the mask that forms the control gate 22 to etch the source free As already mentioned, the bung of the drain D is also elegantly achieved, that the control gate G2 is mounted very precisely over the memory gate G1, wherein these two gates, as shown in FIG. 1, are each the same in this example are long, namely about 3 µ long.

On the entire disk with the state shown in FIG. 1, one can Let a first protective oxide layer grow, in which one can use window contacts for areas 5 and D and for the controllable gates Ga ~ and Gv. Afterward you can use metal vapor deposition to connect the connection lines of the module, as well Generate a second protective oxide layer on top.

Such a production of the control gate G2, the memory gate G1 and the channel K together with the areas HS and D is already through for itself the DT-OS 24 45 030 = VPA 74/1129 known.

If you have an inventive n-channel memory FET without a control gate G2 produces, the number of process steps can be reduced. One can namely immediately after the growth of the first polysilicon layer by means of a Mask this first polysilicon layer with the exception of the memory gate G1 and the etch away parts of this layer belonging to the selection gate Ga2 - in this one The trap is therefore the insulator between the substrate HT on the one hand and the two gates G1, Ga2, on the other hand, each have the same thickness, e.g. 600 i thick.

Then you can by means of ion implantation, taking advantage of the gates G1 and Ga2 and the thick oxide layer Du as masks, an n-doping of the Create areas S, HS, D, Ga2 and G1. Instead of this ion implantation one can also using the same mask with which the Gates Gi, Ga2 were formed, completely etch away the insulating layers over the later areas S, HS '# and generate these areas S, HS, D by means of diffusion, with a doping at the same time the gates Gl, Ga2 arises. Then you can do a first over the whole disc Protective oxide layer, then contacts of the areas S, D, Ga2, as well as by means of windows create connecting lines by means of metal vapor deposition. Finally you can cover the whole pane with a second protective oxide layer.

To the thickness of the insulator between the gate Ga2 and the further The duct area can be reduced in size by modifying the manufacturing process by that between the formation of the regions G1, G1 'from the first polysilicon layer and the subsequent application of the second insulating layer 12, a further method step inserts, namely an etching away of all now exposed parts of the first insulating layer 11 by means of G1, G1 'or by means of the mask used to form G1, G11. then consists the insulator between the gate Ga2 and the further channel region Ka only from the second insulating layer 12, whereby the control potentials at the gate Ga2 affect the wider canal area Ka more intensively in a manner reducing the rejects can.

11 claims 2 figures

Claims (11)

Patent claims 7) n-channel memory FET with at least one gate, namely with a floating memory gate surrounded on all sides by an insulator, in the channel injection that injects electrons to recharge the storage gate - i.e. reloading through strongly accelerated in its own conductive channel and thereby heated electrons, which because of their heating by a in the source-drain direction effective electric field the energy threshold to the conductivity band of the insulator overcome and thereby get to the storage gate - is exploited with the task of the channel injection for programming, i.e. charging the memory gate on an opposite the uncharged state negative potential, so that the memory gate after this charging by means of its negative charge by influencing the source-drain current acts in an inhibiting manner on the source-drain path, according to application / patent P 24 45 137.4-53, especially for program memories of telephone systems, d a d u r c h g e k e n n z e i c h n e t that between the source (5) and the drain (D) in row to its channel (K) first an n-doped auxiliary area (MS) and behind it a further canal area (Ka) with an influencing this further canal area, controllable selection gate (Ga2) isolated from this further channel area are. 2. n-channel memory FET according to claim 1, d a d u r c h g e -k e n It should be noted that the width of the further channel region (Ka) is much greater than the width of the channel (K). 3. n-channel memory FET according to claim 1 or 2, d a d u r c h g e it is not indicated that it only has the memory gate (ai) and the select gate (Ga2), but has no further gate (G2). 4. n-channel memory FET according to claim 1 or 2, d a d u r c h g e it is not indicated that it has an additional, one connection has controllable control gate (G2) that acts capacitively on the memory gate (G1). 5. n-channel memory FET according to claim 4, d a d u r c h g e -k e n It should be noted that its control gate (G2) and its select gate (Ga2) are not immediate conductively connected to one another and therefore controllable separately. 6. n-channel memory FET according to one of the preceding claims, d a d u r c h g e k e n n n z e i c h n e t that between the channel (K) and the other Channel area (Ka) only one, both to channel (X) and to channel area (Ka) immediately adjacent auxiliary area (HS) is inserted. 7. n-channel memory FET according to one of the preceding claims, d a d u r c h g e k e n n n z e i c h n e t that the auxiliary area (HS) is attached to a special, high resistance is connected. 8. A method for producing the n-channel memory FET according to claim 3 g e k e n n n z e v 4 # n e t d u c h the process fs process steps: a. On a p-type silicon wafer as a substrate (HT) is a relatively thick oxide layer (Du) applied, in which a window that extends to the substrate (HT), in which the source-drain path is intended to be etched; b. in the window there will be a relative A thin first insulating layer (11) is produced; c. there will be a first on the whole disc Polysilicon layer deposited; d. the first polysilicon layer is made by means of a mask except for the required areas of the selection gate (Ga2) and the memory gate (Gl) etched away; e. it becomes an n-type doping through ion implantation the selection gate (Ga2), the memory gate (ei), the source (5), the auxiliary area (HS) and the drain (D) generated; f. a first protective oxide layer is applied over the entire pane, furthermore by means of contact windows contacts for the drain (D), the source (5) and the Selection gate (Ga2), as well as the necessary connecting lines by means of metal vapor deposition manufactured; G. A second protective oxide layer is made of silver around the entire pane. 9. The method according to claim 8, g e k e n n n z e i c h n e t by the following Changes to process step e: e1. Using the same mask that is used for shaping the gates (G1, Ga2) was used in process step d, the over the later source (5), the later auxiliary area (HS) and the later drain (D) lying Parts of the first insulating layer (11) are etched away; e2. a doping of the memory gate (G1), the selection gate (Ga2) of the drain (D), the auxiliary region (SH) and the source (5) is created by means of diffusion. 10. A method for producing the n-channel memory FET according to claim 4, 5 or #, g e k e n n n z e i c h n e t d u r c h the following process steps: a. On a p-conducting silicon wafer as a substrate (HT), a relatively thick Oxide layer (Du) applied, in which a window extending to the substrate (HT), in which the source-drain path is to lie, is etched; b. in the window a relative sense first insulating layer (11) is produced; c. all over the disc a first polysilicon layer is deposited, which is additionally doped; d. the first polysilicon layer is substantially reduced to the required area of the memory gate (G1) is etched away, but adjoining the memory gate (G,) first of all another layer of dandruff (G1 ') in the but later auxiliary area tHS) and the later drain (D) reaches into areas; e. on the first Polysilicon layer, a relatively thin second insulating layer (12) is produced; f. a second polysilicon layer is deposited over the entire wafer; G. the second polysilicon layer is down to the required level by means of a mask Areas of the control gate (G2) and the selection gate (Ga2) etched away; H. with the to Forming of the control gate (G2) and the selection gate (Ga2) used in method step g The mask becomes the one that rises over the later auxiliary area (HS) and the later drain (D) Edge layer (G1 ') of the first polysilicon layer and the parts that are not required etching away the first and second insulating layers (11, 12); i. an n-doping of the the control gate (G2) and the selection gate (Ca2) corresponding parts of the second polysilicon layer as well as n-doping of the substrate (HT) on its exposed surfaces for Production of the source (S), the holding region (HS), and the drain (D) is applied; k. A first protective oxide layer is applied over the entire pane, furthermore by means of a contact window we-the contacts for the drain (D), the selection gate (Ga2) and the control gate (G2), as well as metal vapor deposition, the necessary connecting lines are made; 1. A second protective oxide layer is made over the entire pane. 11. The method according to claim 10, g e k e n n z e i c h n e t d u r c h the insertion of a further process step between the process steps d and e: dl. The remaining parts of the first polysilicon layer (G1, al ') uncovered parts of the first insulating layer (I1) are etched away.