JPS58223362A - Semiconductor device - Google Patents

Abstract

PURPOSE:To contrive not to generate latch-up by extinguishing a parasitic bi- polar transistor by a method wherein the device is so formed that at least one set of source and drain of a C-MOSFET form Schottky contact. CONSTITUTION:The n-well type C-MOSFET is composed of a p-channel MOSFET 33 formed on the n<-> well 32 of a p<-> substrate 31 and an n-channel MOSFET 34 formed in the substrate 31. Where, the source 40 and the drain 41 of the FET 33 are constituted so as to form Schottky contact between the well 32. The current flowing through the Schottky contact depends on the majority carrier of the semiconductor side, and the injection efficiency of the minority carrier is remarkably low. Thereby, the parasitic transistor is extinguished, and thus latch-up does not occur. As a result, the removal of a guard ring, etc. is enabled, and the transverse expansion of the well can be reduced, therefore the high density can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to confectionery structures for semiconductor devices, particularly OMO8 integrated circuits.

The MO8 element, which consists of p-channel type and n-channel type MOS) transistors, has excellent features such as low power consumption and a wide operating power supply voltage range, and is widely used in large-scale integrated circuits. There is a drawback that a so-called latch-up phenomenon occurs in which abnormal current continues to flow when a signal is applied to the input or output terminal.

The present invention was developed in view of this situation, and its objectives include the advantages of high density of MO8i elements and short manufacturing period. Latch-up can be completely prevented without using a filtration membrane. A semiconductor device f1t consisting of 0MO8 elements,
Our goal is to provide the following.

In order to achieve such an objective, the present invention provides 0M08
X-channel is formed by p-channel and n-channel MO8)
The source and drain of at least one of the transistors are configured to form a shot Φ contact.

The present invention will be described in detail below using examples, but first, the mechanism by which the latch-up phenomenon occurs in the conventional 0M08 X-element and the principle by which the latch-up phenomenon can be solved by the present invention will be explained.

Diagram M1 schematically shows the structure of a conventionally used 0MO8 element. In the figure, 11 indicates a p-channel MO8II transistor, and 12 indicates an n-channel MO8) transistor, each of which has a drain 14° as a p region formed on an n-substrate 13, a source 15, and a gate formed on the surface between the two. 1G and formed in the p-well 17 provided in the n-substrate 13? Drain as region 18. It is composed of a source 19 and a gate 20.

In this way, in the 0MO8 element, the guard link 21 consisting of the substrate, the well, the source, the drain, and the p+ region formed around the n-channel MOS transistor 12, that is, the periphery of the p-well 1T; High concentration diffusion layers 22 and 23 for potential fixing consisting of n4- and p10 regions, respectively, are provided adjacent to the drain 14 of the p-channel MO8 transistor 11 and the source 19 of the n-channel MO8 transistor 12. Since many impurity layers of different conductivity types coexist, npn and pnp bipolar transistors are formed between the different impurity layers. The figure shows such parasitic bibo 2.
Although typical examples of transistors have been shown, such transistors Trl and Trg are connected to each other to form a parasitic thyristor with a pnpn structure.

FIG. 2 shows its equivalent circuit. In the figure, the transistor Trl is triggered by the noise current If.

The double-up phenomenon occurs when Trs remains in the dion state fIa through the positive feedback loop, and the current continues to flow.

To prevent this, transistor Tr+ or Tr
It is clear that a method of reducing the current amplification factor hyx of s is effective, and hFl is determined by the emitter injection efficiency and the base transport efficiency, as is well known.

For this reason, conventional methods have been used to reduce the base transport efficiency by deepening the well to widen the lapsed base width or increasing the impurity concentration in the base region.

However, these methods are not compatible with high density, or require the use of epitaxial layers.
There was an inconvenience that destroyed the original advantages of MO8 Kiko, such as high density and short production period.

Therefore, the present invention provides another 1! that determines the current amplification factor hyg as described above. The main focus is on reducing the emitter injection efficiency.

That is, in the source and drain forming a normal pn junction as shown in Fig. 1, the impurity concentration is 1x10" at
oms/c1++" or more, while the impurity concentration of the well or substrate is 5〆10 to 2 x 10"a t
The emitter injection efficiency is about 0.0 m s/cnt8 under such conditions, and the emitter injection efficiency is 0.99 or more, and most of the current flowing through the pn junction is caused by minority carriers in the well or the substrate. As is well known, the one-by-one operation is caused by minority carriers injected into the base region, so under the above conditions, the parasitic bipolar transistor Tr+
Tr+ is in a state where it can be reliably operated.

On the other hand, in the present invention, the source, drain, and drain, which are normally configured to form a pn junction, are configured to form a Schottky contact. As is well known, the current flowing through the Schottky contact is caused by majority carriers on the semiconductor side, and the minority carrier injection efficiency 4 is extremely low. For example, if the impurity concentration of the well or substrate has the value mentioned above, the injection efficiency will be 0.001 or less, and the current amplification factor of the parasitic bipolar transistor will be 1/1000.
In the following, it is virtually the same as if the parasitic bipolar transistor had disappeared. Therefore, the parasitic bipolar transistors Trl, Tr! shown in FIG. The parasitic thyristor disappears by removing one or both of the
Latch-up will no longer occur.

Various metals or metal silicides can be used as the source and drain materials for forming the Schottky contact. - For example, especially in the case of an n-substrate, aluminum is suitable from the viewpoint of workability, and platinum is also suitable for an n-substrate. Further, materials that can be used for either nap substrate include, for example, molybdenum and tungsten, which form metal silicide.

FIG. 3 is a sectional view schematically showing the structure of an embodiment of the present invention. This embodiment is an example applied to an n-well type MO8 element, in which a p-channel MO8 transistor 33 formed in an n-well 32 provided in a p-substrate 31 and a p-channel MO8 transistor 33 and a p-substrate 3
It is composed of an n-channel MO8) transistor 34 formed in 1. The gates 35 and 36 of both transistors are both made of polysilicon, and the gates 35 and 36 are formed of polysilicon between the p-channel transistors 33, that is, the n-well 32.
A guard link 37 consisting of an n area is provided at the peripheral edge of the area.

Here, the source 3 of the n-channel MO8) transistor 34 is
The source 40 and drain 41 of the p-channel O8 transistor 33 are made of aluminum so as to form a Schottky contact with the n-well 32, while the source 40 and drain 3g of the p-channel O8 transistor 33 are made of aluminum. .

When the latch-up characteristics of the CMOS element having the above configuration were measured, no latch-up was observed at all.

It has been confirmed that the configuration of the present invention using Schottky contact is extremely effective.

Furthermore, in this case, it was confirmed that since the Schottky contact can be formed extremely shallowly, short channel effects also occur and are less likely to occur.

In addition, in the above-mentioned embodiment, the conventional CMO8 element, that is, the first
Since the same photomask as in the case of forming the element tube shown in the figure was used, in addition to the guard ring 31, a high concentration diffusion 142 for potential fixing consisting of an n region adjacent to the drain 41 of the p channel transistor 33 and the n channel transistor Although a metal layer 43 is formed adjacent to the source 38, these can be removed since latch-up does not occur in the case of the present invention as described above.

An example is shown in Figure 4. In this embodiment, the source 44 and drain 45 of the n-channel MO transistor 34 are
It is also composed of molybdenum to form a Schottky contact. Conventionally, the depth of the lfc and n-well 32 was made as deep as 4 to 6 .mu.m to prevent latch-up from occurring, as described above, but in this embodiment, it is formed as extremely shallow as 2 .mu.m. As a result, transverse waves in the well are reduced, making it possible to achieve higher density than conventional CMOB elements. Further, when forming each source and drain, metal is also deposited on the gates 35 and 36 exposed from polysilicon, thereby providing the advantage that the resistance of the gate electrode can be reduced.

As explained above, according to the CMO8 element of the present invention,
By using Schottky contacts for the source and drain, parasitic bipolar transistors can be eliminated and the latch-up problem can be fundamentally solved. As a result, it is possible to remove the guard ring, etc., and the well can be made shallower, reducing transverse waves in the well by as much as 9, so that a significant increase in density can be achieved and the manufacturing process can be simplified. In addition, since the source and drain are made of metal, etc., parasitic resistance can be reduced, and through process improvements, the resistance of the gate electrode can also be reduced, making it possible to increase speed.
Furthermore, since the bond is shallow, it has various excellent effects such as the short channel effect being less likely to occur.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view schematically showing an example of a conventional CMO8 element, Fig. 2 is an equivalent circuit of a parasitic thyristor, Fig. 3 is a cross-sectional view showing an embodiment of the present invention, and Fig. 4 is a cross-sectional view showing an example of the present invention. FIG. 3 is a sectional view showing another embodiment of the invention. 31..p-substrate, 32..n-well, 33
Skewer...pf Yarnel MO8) Langister, No. 34...
n-channel MO8) transistor, 40.41.44.4
5... Source and drain forming Schottky contact. Patent applicant Japan! Masaki Yamakawa 10- Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] p-channel MO8) Rungis, Ta and n-channel M
O8) A semiconductor device comprising an 0MO8 element constituted by a transistor, characterized in that the source and drain of at least one of a p-channel MOS transistor or an n-channel MO8) transistor form a Schottky contact. .