JPH0964288A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having a large latch-up resistance and a high reliability. SOLUTION: A guard ring made up of an n-well region 5 is provided around an input-output protection circuit, further a p<+> semiconductor region 18 connected with a terminal Tp for power supply is provided adjacently to the guard ring and in parallel with the guard ring inside a p-well region 3 wherein the input-output protection circuit is formed. Accordingly, holes and electrons are captured by a p<+> semiconductor region 18 and the guard ring respectively so as to prevent diffusion of the holes and the electrons into the inner circuits, thus making it hard to generate a latch-up phenomenon in a CMOS device in the inner circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a complementary MOSFET (Complementary Metadevice).
l Oxide Semiconductor Field Effect Transistor ； C
The present invention relates to a technique effectively applied to a semiconductor integrated circuit device having a MOSFET.

[0002]

2. Description of the Related Art CMOS devices are one of the effective circuit technologies for realizing low power consumption of semiconductor integrated circuit devices. The CMOS device is an n-channel type MISFET
Qn and p-channel type MISFET Qp are arranged in series. For example, as shown in FIG. 7, an n-well region 4 is formed on the main surface of a p-type semiconductor substrate 1, and a p-type semiconductor substrate 1 is formed. Shows a structure in which an n-channel type MISFET Qn is formed and a p-channel type MISFET Qp is formed in the n-well region 4.

By the way, in the CMOS device,
An unstable operation phenomenon called latch-up, which is unique to the structure of a CMOS device, may occur in which a large current continues to flow from the power supply terminal to the ground terminal.

That is, in the CMOS device, as shown in FIG. 7, a lateral npn parasitic bipolar transistor Q1 is formed between the source region 13a of the n-channel type MISFET Qn, the p-type semiconductor substrate 1 and the n-well region 4. Further, the source region 17a of the p-channel type MISFET Qp, the n-well region 4 and the p-type semiconductor substrate 1 are formed.
The vertical pnp parasitic bipolar transistor Q2 is constituted by.

Further, these two parasitic bipolar transistors Q1 and Q2 can be regarded as forming a thyristor as shown by a broken line. Since this circuit is a positive feedback circuit, two parasitic bipolar transistors Q
When one of Q1 and Q2 is forward biased,
The above latch-up phenomenon occurs. Note that R in FIG.
w and Rs are the resistance of the n-well region 4 and the resistance of the semiconductor substrate 1, respectively.

For example, when the emitter-base of the npn parasitic bipolar transistor Q1 is forward biased by transient noise, the npn parasitic bipolar transistor Q1 becomes conductive. npn parasitic bipolar transistor Q
The collector current flowing through 1 becomes majority carriers in the n-well region 4, causing a voltage drop in the resistor Rw, and pnp
The emitter-base of the parasitic bipolar transistor Q2 is forward biased. As a result, the pnp parasitic bipolar transistor Q2 is rendered conductive, and the collector current flowing through the pnp parasitic bipolar transistor Q2 is formed of the reversely biased n-well region 4 and the p-type semiconductor substrate 1.
They are collected in the n-junction and flow into the semiconductor substrate 1 to become majority carriers. This majority carrier causes a voltage drop in the resistor Rs, biasing the emitter-base of the npn parasitic bipolar transistor Q1 more and more forward, and unless the power supply voltage is lowered, the power supply terminal T _DD to the ground terminal T shown in FIG. Current continues to flow to _SS .

Therefore, in the circuit design, a measure is usually taken to prevent the latch-up by absorbing the carriers injected into the p-type semiconductor substrate 1 or the n-well region 4.

First, the minority carrier is an n-channel MI.
It is absorbed by a guard ring provided around the SFET Qn or the p-channel type MISFET Qp. That is, a guard ring constituted by an n ⁺ semiconductor region to which a reverse bias is applied is provided around the n-channel type MISFET Qn formed on the p-type semiconductor substrate 1 and implanted into the p-type semiconductor substrate 1. The electrons of minority carriers are trapped by this guard ring to prevent the electrons from diffusing into the n-well region 4.

Similarly, a guard ring composed of ap ⁺ semiconductor region is provided around the p-channel type MISFET Qp formed in the n-well region 4, and holes of minority carriers are trapped by this guard ring. Diffusion of holes into the p-type semiconductor substrate 1 can be suppressed.

Next, the majority carriers are absorbed by the semiconductor region to which the power supply terminal is connected. That is, FIG.
In the CMOS device shown in FIG. 3, holes are captured in the p ⁺ semiconductor region 18 to which the power supply terminal of the p-type semiconductor substrate 1 is connected, and the n ⁺ semiconductor region 14 to which the power supply terminal of the n well region 4 is connected. Can capture electrons at.

Note that, for example, "Submicron Device (a)", published by Maruzen Co., Ltd. on July 31, 1987, by Mitsumasa Koyanagi, P209 describes a measure for preventing latchup of a CMOS device using a guard ring. .

[0012]

An input / output protection circuit is usually provided in the input / output section of the semiconductor integrated circuit device in order to protect the input from overvoltage surge.
The input protection element composed of a pn diode in the input / output protection circuit works to limit the input voltage when a large voltage below the ground potential or above the power supply voltage is applied to the input terminal. However, at this time, avalanche breakdown occurs in the pn junction forming the input protection element, a large amount of holes and electrons are generated, and diffuse in the semiconductor substrate.

Therefore, for example, when the input / output protection circuit is formed on the p-type semiconductor substrate 1, as shown in FIG. 8, a guard ring having an n-well region 5 around the input / output protection circuit is formed. This guard ring traps most of the minority carrier electrons generated in the input / output protection circuit and prevents them from diffusing into the internal circuit in which the CMOS device is formed.

However, the holes of majority carriers generated in the input / output protection circuit cannot be captured by the guard ring, and most of them diffuse to the internal circuit in which the CMOS device is formed. Some of the holes are recombined with the electrons of the guard ring formed in the n-well region 5, and are captured in the p ⁺ semiconductor region 18 to which the power supply terminal T _{P of} the p-type semiconductor substrate 1 is connected. However, the effect is not enough,
Most of the holes serve as the base current of the npn parasitic bipolar transistor Q1 shown in FIG. This base current forward biases between the emitter and the base to make the npn parasitic bipolar transistor Q1 conductive, and C of the internal circuit
It causes a latch-up phenomenon in a MOS device.

An object of the present invention is to provide a technique capable of obtaining a highly reliable semiconductor integrated circuit device having a large latch-up resistance.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0017]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, (1) In the semiconductor integrated circuit device of the present invention, the guard ring constituted by the well region is arranged around the input / output protection circuit, and the guard ring opposite to the conductivity type of the well region constituting the guard ring is arranged. A conductive type semiconductor region is provided adjacent to the guard ring in a semiconductor substrate or a well region inside the guard ring.

(2) In the semiconductor integrated circuit device of the present invention, a guard ring formed of a well region is arranged around the input / output protection circuit, and the conductivity type of the well region forming the guard ring is arranged. A semiconductor region of the opposite conductivity type is provided adjacent to the guard ring in the semiconductor substrate or the well region outside the guard ring.

(3) Further, in the semiconductor integrated circuit device of the present invention, a guard ring constituted of a well region is arranged around the input / output protection circuit, and the conductivity type of the well region constituting the guard ring is arranged. Adjacent to the guard ring, a semiconductor region of the opposite conductivity type is provided in the semiconductor substrate or well region inside the guard ring and in the semiconductor substrate or well region outside the guard ring.

[0020]

According to the above means, in the guard ring formed by the well region provided around the input / output protection circuit, the minority carriers generated in the input / output protection circuit are effectively captured, and further, the guard ring is formed. The majority carriers generated in the input / output protection circuit are effectively trapped in the semiconductor region, which is arranged adjacent to the ring and has a conductivity type opposite to that of the well region forming the guard ring.

As a result, it is possible to prevent the majority carriers and the minority carriers generated in the input / output protection circuit from diffusing into the semiconductor substrate, so that the latch-up phenomenon hardly occurs in the CMOS device formed in the internal circuit. It becomes possible to do.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 is a double-well CMOS having an input / output protection circuit according to an embodiment of the present invention.
It is a principal part sectional drawing of the semiconductor substrate which shows a device.

As shown in FIG. 1, an internal circuit having an input / output protection circuit, a guard ring provided around the input / output protection circuit, and a CMOS device is formed on a p-type semiconductor substrate 1.

The input / output protection circuit is formed in the p-well region 3, and the input terminal T _IN of the input protection element is the wiring 21.
It is connected to the n ⁺ semiconductor region 16 provided in the p well region 3 by c. Further, in the p well region 3 in which the input / output protection circuit is formed, a p ⁺ semiconductor to which the power supply terminal T _P is connected by the wiring 21p in parallel with the guard ring provided around the input / output protection circuit. The area 18 is arranged.

The p ⁺ semiconductor region 18 is provided around the input / output protection circuit, and the holes of the majority carriers generated in the input / output protection circuit are trapped by the p ⁺ semiconductor region 18 to form an internal circuit. It prevents the holes from diffusing.

The guard ring provided around the input / output protection circuit is constituted by the n-well region 5, and the power supply terminal T _G of the guard ring is n-shaped by the wiring 21d.
It is connected to the n ⁺ semiconductor region 15 provided in the well region 5. By capturing the minority carrier electrons generated in the input / output protection circuit with this guard ring, the diffusion of the electrons to the internal circuit is prevented. Although the guard ring is provided so as to surround the periphery of the input / output protection circuit, it does not necessarily have to be arranged continuously over the entire circumference of the input / output protection circuit, and a part thereof may be discontinuous.

The internal circuit has an n-channel type MISFET Qn formed in the p-well region 2 and a p-channel type MISFET Qp formed in the n-well region 4. In the p well region 2, a gate electrode 9n and a low concentration n are formed.
An n-channel type MISFET Qn is formed which includes a source region 10a and a drain region 10b made of a type impurity and a source region 13a and a drain region 13b made of a high concentration n-type impurity.

Further, in the n-well region 4, the gate electrode 9
In addition to the p-channel type MISFET Qp including the source region 11a and the drain region 11b made of p, the low concentration p-type impurity, and the source region 17a and the drain region 17b made of the high concentration p-type impurity,
An n ⁺ semiconductor region 14 is formed in which the power supply terminal T _N of the n well region 4 is connected by the wiring 21n.

Next, a method of manufacturing the CMOS device having the input / output protection circuit of the first embodiment will be briefly described with reference to FIGS.

First, as shown in FIG. 2, p well regions 2 and 3 and n well regions 4 and 5 are formed on the main surface of a semiconductor substrate 1 made of p type silicon single crystal by a self-alignment method. After that, a field insulating film 6 for element isolation is formed on the surfaces of the p well regions 2 and 3 and the n well regions 4 and 5.

Next, p well regions 2 and n of the internal circuit are formed.
Although not shown in the figure, the threshold voltage control layers of the n-channel type MISFET Qn and the p-channel type MISFET Qp are formed by ion-implanting p-type impurities (for example, boron (B)) into the respective channel regions of the well region 4. Form each.

Next, a gate insulating film 7 is formed on the surfaces of the p well regions 2 and 3 and the n well regions 4 and 5, respectively. Then, on the semiconductor substrate 1, a polycrystalline silicon film (not shown) into which phosphorus (P) is introduced and a silicon oxide film 8 are formed.
Are sequentially deposited by the CVD (Chemical Vapor Deposition) method.

Next, as shown in FIG. 3, the silicon oxide film 8 and the polycrystalline silicon film are sequentially etched using a photoresist (not shown) as a mask to form an n-channel type MISFET Qn forming an internal circuit. The gate electrode 9n and the gate electrode 9p of the p-channel type MISFET Qp are formed.

Next, using a photoresist (not shown) and the gate electrode 9n as a mask, an n-type impurity (for example, P) is ion-implanted in the p-well region 2 of the internal circuit to reduce the concentration of the n-channel MISFET Qn. A source region 10a and a drain region 10b made of the n-type semiconductor region are formed. Further, using the photoresist (not shown) and the gate electrode 9p as a mask, the n well region 4 of the internal circuit is formed.
A p-type impurity (for example, B) is ion-implanted into the p-type MISFET Qp to form a source region 11a and a drain region 11b, which are p-type semiconductor regions of low concentration.

Next, although not shown, a silicon oxide film is deposited on the semiconductor substrate 1 by the CVD method, and the silicon oxide film is etched by, for example, RIE (Reactive Ion Etching) method to form the gate electrodes 9n and 9p. Sidewall spacers 12n and 12p are formed on the side walls, respectively.

Next, using a photoresist (not shown) and the gate electrode 9n and the sidewall spacer 12n as a mask, an n-type impurity (for example, arsenic (As)) is ion-implanted into the p well region 2 of the internal circuit. Then, the source region 13a and the drain region 13b formed of the high-concentration n-type semiconductor region of the n-channel type MISFET Qn are formed.

At the same time, a region to which the power supply terminal T _N of the n-well region 4 of the internal circuit is connected, a region to which the power supply terminal T _G of the n-well region 5 forming the guard ring is connected, and the input / output protection circuit. The n-type impurities are also ion-implanted into the regions to which the input terminals T _IN are connected to form high-concentration n ⁺ semiconductor regions 14, 15, and 16, respectively.

Further, by using a photoresist (not shown) and the gate electrode 9p and the sidewall spacer 12p as a mask, p-type impurities (for example, B) are ion-implanted into the n-well region 4 of the internal circuit, and a p-channel is formed. Type MISF
A source region 17a and a drain region 17b made of a high concentration p-type semiconductor region of ETQp are formed.

At the same time, the p-well region 3 of the input / output protection circuit
The p-type impurity (B) is also ion-implanted into a region to which the power supply terminal T _{P of the P} ⁺ semiconductor region 18 of high concentration is connected.
Is formed.

Next, as shown in FIG. 4, after depositing a silicon oxide film 19 on the semiconductor substrate 1, the silicon oxide film 19 is etched using a photoresist (not shown) as a mask to form a contact hole 20. Make a hole. After that, a metal film (not shown) is deposited on the semiconductor substrate 1, the metal film is etched to form the wiring 21, and finally, the surface of the semiconductor substrate 1 is covered with the passivation film 22. The CMOS device of the first embodiment shown in FIG. 1 is completed.

A CMOS having the structure of the first embodiment shown in FIG.
The voltage shown in Table 1 below is set to each terminal of the device and the CMOS device having the conventional structure shown in FIG.
The current flowing through the input terminal T _IN of the input / output protection circuit when the npn parasitic bipolar transistor Q1 was turned on was obtained by simulation. The voltage applied to the semiconductor substrate 1 is set to 0V.

[0044]

[Table 1]

In the simulation, the p-well regions 2 and 3, the n-well regions 4,5 and the n-channel type M are used.
Source region 13a of ISFET Qn, n ⁺ semiconductor region 1
The impurity concentration distributions of the source regions 17a and the p ⁺ semiconductor regions 18 of the p-channel type MISFETs Qp are defined as Gaussian distributions, and the impurity concentration distributions thereof are summarized in Table 2 below.

[0046]

[Table 2]

According to the simulation, in the CMOS device having the conventional structure, the input terminal T _IN of the input / output protection circuit is
When a current of 1.97 × 10 ⁻⁶ A flows into the circuit, the npn parasitic bipolar transistor T1 becomes conductive and the CMO of the internal circuit
A malfunction occurs in the S device. However, in the CMOS device having the structure of the first embodiment, n is maintained until a current of 8.26 × 10 ⁻⁴ A flows to the input terminal T _IN of the input / output protection circuit.
The pn parasitic bipolar transistor Q1 does not conduct, and the CMOS device of the internal circuit operates stably even if a current larger by one digit than that of the CMOS device of the conventional structure flows.

As described above, according to the first embodiment, even if holes and electrons are generated in the input / output protection circuit, the electrons are efficiently captured by the guard ring provided around the input / output protection circuit. Further, the holes are efficiently trapped in the p ⁺ semiconductor region 18 arranged adjacent to the guard ring and in parallel with the guard ring, so that the diffusion of holes and electrons into the internal circuit can be prevented. The device latch-up phenomenon can be made less likely to occur.

(Embodiment 2) FIG. 5 is a double well type CMO having an input / output protection circuit according to another embodiment of the present invention.
It is a principal part sectional view of a semiconductor substrate which shows an S device.

As shown in FIG. 5, as in the first embodiment, the input / output protection circuit, the guard ring provided around the input / output protection circuit, and the CMO are provided on the p-type semiconductor substrate 1.
An internal circuit having an S device is formed.

However, the p ⁺ semiconductor region 18 to which the power supply terminal T _P is connected is provided in the p well region 3 in which the input / output protection circuit is formed in the first embodiment, but this embodiment 2 Is provided in the p-well region 2 arranged in the internal circuit, and further, in the p ⁺ semiconductor region 1
8 is provided adjacent to the guard ring and in parallel with the guard ring.

A CMOS having the structure of the second embodiment shown in FIG.
The voltage shown in Table 3 below was set to each terminal of the device, and the current flowing to the input terminal T _IN of the input / output protection circuit when the npn parasitic bipolar transistor Q1 became conductive was obtained by simulation. The voltage applied to the semiconductor substrate 1 is set to 0V.

The p-well regions 2 and 3, the n-well regions 4 and 5, and the n-channel type MIS used in the simulation.
The source region 13a of the FET Qn, the n ⁺ semiconductor region 14,
The impurity concentration distributions of the source regions 17a and the p ⁺ semiconductor regions 18 of the p-channel type MISFETs Qp and 15, 16 are all defined by Gaussian distribution and are the same as those summarized in Table 2 above.

[0054]

[Table 3]

According to the simulation, in the CMOS device having the structure of the second embodiment, npn is maintained until a current of 4.14 × 10 ⁻⁶ A flows to the input terminal T _IN of the input / output protection circuit.
The parasitic bipolar transistor Q1 does not conduct, and the CMOS device in the internal circuit operates stably even if a current about twice as large as that in the CMOS device having the conventional structure shown in FIG. 8 flows.

As described above, according to the second embodiment, the p ⁺ semiconductor region 18 is arranged in the p well region 2 of the internal circuit so as to be adjacent to the guard ring and parallel to the guard ring. The holes diffused from the input / output protection circuit to the internal circuit can be captured in the p ⁺ semiconductor region 18, and the latch-up phenomenon of the CMOS device can be made less likely to occur.

(Embodiment 3) FIG. 6 is a double-well CMO having an input / output protection circuit according to another embodiment of the present invention.
It is a principal part sectional view of a semiconductor substrate which shows an S device.

As shown in FIG. 6, similar to the first embodiment, the I / O protection circuit, the guard ring provided around the I / O protection circuit, and the CMO are provided on the p-type semiconductor substrate 1.
An internal circuit having an S device is formed.

However, the p ⁺ semiconductor region 18 to which the power supply terminal T _P is connected is provided only in the p well region 3 in which the input / output protection circuit is formed in the first embodiment, but this embodiment does not. 3 is provided in the p-well region 3 where the input / output protection circuit is formed and in the p-well region 2 arranged in the internal circuit, and these p ⁺ semiconductor regions 18a and 18b are adjacent to the guard ring. It is provided parallel to the guard ring.

A CMOS having the structure of the third embodiment shown in FIG.
The voltages shown in Table 4 below were set to the respective terminals of the device, and the current flowing to the input terminal T _IN of the input / output protection circuit when the npn parasitic bipolar transistor Q1 became conductive was obtained by simulation. The voltage applied to the semiconductor substrate 1 is set to 0V.

The p-well regions 2 and 3, the n-well regions 4,5 and the n-channel type MIS used in the simulation.
The source region 13a of the FET Qn, the n ⁺ semiconductor region 14,
The impurity concentration distributions of the source regions 17a and the p ⁺ semiconductor regions 18 of the p-channel type MISFETs Qp and 15, 16 are all defined by Gaussian distribution and are the same as those summarized in Table 2 above.

[0062]

[Table 4]

According to the simulation, in the CMOS device having the structure of the third embodiment, npn is maintained until a current of 1.62 × 10 ⁻³ A flows to the input terminal T _IN of the input / output protection circuit.
The parasitic bipolar transistor Q1 does not conduct, and the CMOS device of the internal circuit operates stably even if a current that is three orders of magnitude larger than that of the CMOS device of the conventional structure shown in FIG. 8 flows.

Thus, the holes generated in the input / output protection circuit are captured by the p ⁺ semiconductor region 18a provided in the p well region 3 in which the input / output protection circuit is formed, and further,
Holes diffused from the input / output protection circuit to the internal circuit beyond the guard ring can be captured by the p ⁺ semiconductor region 18b provided in the p well region 2 arranged in the internal circuit, and The latch-up phenomenon can be made less likely to occur.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, the semiconductor integrated circuit device having the double well type CMOS device has been described in the above embodiment, but an n well type CMOS in which an n type well region is provided on a semiconductor substrate of p type conductivity type. The present invention can be applied to a device or a semiconductor integrated circuit device having a p-well CMOS device in which a p-type well region is provided on a semiconductor substrate having an n-type conductivity.

[0067]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

According to the present invention, the majority carrier and the minority carrier generated in the input / output protection circuit can be prevented from diffusing into the internal circuit, and the latch-up phenomenon of the CMOS device formed in the internal circuit can be prevented. It is possible to obtain a highly reliable semiconductor integrated circuit device having a large latch-up resistance because it can be prevented.

[Brief description of drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate showing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of essential parts of a semiconductor substrate showing a semiconductor integrated circuit device that is an embodiment of the present invention.

FIG. 3 is a cross-sectional view of essential parts of a semiconductor substrate showing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 4 is a cross-sectional view of essential parts of a semiconductor substrate showing a semiconductor integrated circuit device that is an embodiment of the present invention.

FIG. 5 is a cross-sectional view of essential parts of a semiconductor substrate showing a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 6 is a cross-sectional view of essential parts of a semiconductor substrate showing a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 7 is a cross-sectional view of essential parts of a semiconductor substrate showing an example of a conventional semiconductor integrated circuit device.

FIG. 8 is a cross-sectional view of essential parts of a semiconductor substrate showing an example of a conventional semiconductor integrated circuit device having a guard ring.

[Explanation of symbols]

1 semiconductor substrate 2 p well region (internal circuit) 3 p well region (input / output protection circuit) 4 n well region (internal circuit) 5 n well region (guard ring) 6 field insulating film 7 gate insulating film 8 silicon oxide film 9n Gate electrode (n-channel MISFET) 9p Gate electrode (p-channel MISFET) 10a Source region (low-concentration n-type semiconductor region) 10b Drain region (low-concentration n-type semiconductor region) 11a Source region (low-concentration p-type) Semiconductor region) 11b Drain region (low concentration p-type semiconductor region) 12n Sidewall spacer (n-channel type MIS)
FET) 12p Sidewall spacer (p channel MIS)
FET) 13a source region (high-concentration n-type semiconductor region) 13b drain region (high-concentration n-type semiconductor region) 14 n ⁺ semiconductor region 15 n ⁺ semiconductor region 16 n ⁺ semiconductor region 17a source region (high-concentration p-type semiconductor region) Semiconductor region) 17b drain region (high-concentration p-type semiconductor region) 18 p ⁺ semiconductor region 18a p ⁺ semiconductor region 18b p ⁺ semiconductor region 19 silicon oxide film 20 contact hole 21 wiring 21a wiring 21b wiring 21c wiring 21d wiring 21n wiring 21p Wiring 22 Passivation film Qn n-channel type MISFET Qp p-channel type MISFET T _DD power supply terminal T _SS ground terminal T _IN input / output protection circuit input terminal T _G guard ring power supply terminal T _N n well area power supply terminal T _P Power supply terminal for p-well region Q1 npn parasitic bipolar Transistor Q2 pnp parasitic bipolar transistor Rs resistance Rw resistance

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hisako Sato 2326 Imai, Ome-shi, Tokyo, Hitachi Device Development Center (72) Inventor Hiroo Masuda 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device Development Center (72) Inventor Hisaaki Kunitomo 2326 Imai, Hitachi, Ltd. Device Development Center, Ome-shi, Tokyo (72) Inventor Seiji Narii 2326 Imai, Ome-shi, Tokyo Ltd. Device Development Center, Hitachi, Ltd. (72) Inventor Satoshi Udagawa 2326 Imai, Ome-shi, Tokyo Inside Hitachi, Ltd. Device Development Center

Claims (9)

[Claims] 1. A semiconductor integrated circuit device in which a guard ring formed of a well region is arranged around an input / output protection circuit, the conductivity type being opposite to the conductivity type of the well region forming the guard ring. A semiconductor integrated circuit device, wherein a semiconductor region is provided adjacent to the guard ring in a semiconductor substrate or a well region inside the guard ring. 2. A semiconductor integrated circuit device in which a guard ring formed of a well region is arranged around an input / output protection circuit, the conductivity type being opposite to the conductivity type of the well region forming the guard ring. A semiconductor integrated circuit device, wherein a semiconductor region is provided adjacent to the guard ring on a semiconductor substrate or a well region outside the guard ring. 3. A semiconductor integrated circuit device in which a guard ring formed of a well region is arranged around an input / output protection circuit, the conductivity type being opposite to that of the well region forming the guard ring. A semiconductor integrated circuit device, wherein a semiconductor region is provided adjacent to the guard ring in a semiconductor substrate or a well region inside the guard ring and in a semiconductor substrate or a well region outside the guard ring. . 4. A semiconductor integrated circuit device in which a guard ring constituted by a first n-well region is arranged around an input / output protection circuit formed in a first p-well region, the p-type A semiconductor integrated circuit device, wherein a semiconductor region is provided adjacent to the guard ring in the first p-well region in which the input / output protection circuit is formed. 5. A guard ring formed by a first n-well region is arranged around an input / output protection circuit formed in the first p-well region, and the input / output is sandwiched by the guard ring. An n-channel MI formed in the second p-well region on the semiconductor substrate on the side opposite to the protection circuit.
Double-well CMOS including an SFET and a p-channel MISFET formed in the second n-well region
In a semiconductor integrated circuit device in which an internal circuit having a device is arranged, a p-type semiconductor region is provided adjacent to the guard ring in the second p-well region arranged in the internal circuit. And a semiconductor integrated circuit device. 6. A guard ring constituted by a first n-well region is arranged around an input / output protection circuit formed in the first p-well region, and the input / output is sandwiched by the guard ring. An n-channel MI formed in the second p-well region on the semiconductor substrate on the side opposite to the protection circuit.
Double-well CMOS including an SFET and a p-channel MISFET formed in the second n-well region
A semiconductor integrated circuit device in which an internal circuit having a device is arranged, wherein the p-type semiconductor region is adjacent to the guard ring, and the input / output protection circuit is formed.
The semiconductor integrated circuit device is provided in the p-well region and in the second p-well region arranged in the internal circuit. 7. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor region is arranged in parallel with the guard ring. 8. The semiconductor integrated circuit device according to claim 1, wherein the maximum value of the impurity concentration of the semiconductor region is 3 × 10 ²⁰ cm ^−3. Integrated circuit device. 9. The semiconductor integrated circuit device according to claim 4, wherein the p-type semiconductor region is the first
2. The semiconductor integrated circuit device according to claim 1, which is a power supply terminal for the p-well region or the second p-well region.