JPS6170760A - Vertical type mosfet - Google Patents
Vertical type mosfetInfo
- Publication number
- JPS6170760A JPS6170760A JP59192888A JP19288884A JPS6170760A JP S6170760 A JPS6170760 A JP S6170760A JP 59192888 A JP59192888 A JP 59192888A JP 19288884 A JP19288884 A JP 19288884A JP S6170760 A JPS6170760 A JP S6170760A
- Authority
- JP
- Japan
- Prior art keywords
- source
- vertical
- breakdown
- region
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015556 catabolic process Effects 0.000 abstract description 11
- 230000003071 parasitic effect Effects 0.000 abstract description 10
- 230000000694 effects Effects 0.000 abstract description 4
- 229920000136 polysorbate Polymers 0.000 abstract 1
- 230000006378 damage Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7839—Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は電力用の縦型ＭＯ３ＦＥＴに関するものである
。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a vertical MO3FET for power use.
従来例の構成とその問題点
近年、電力用縦型ＭＯ３ＦＥＴは、電源回路等の分野で
多く利用されるようになってきた。Structure of conventional example and its problems In recent years, vertical power MO3FETs have come to be widely used in fields such as power supply circuits.
以下、図面を参照しながら、上述したような従来の電力
用縦型ＭＯ５ＦＥＴについて説明を行う。Hereinafter, the conventional power vertical MO5FET as described above will be explained with reference to the drawings.
第１図は、従来の縦型ＭＯ８ＦＥＴの構造断面図を示す
。第１図において、１はソース電極、２は眉間絶縁のた
めの５ｉ０２膜、３はゲート電極、４はソース領域、５
はパックゲート領域、６はパックゲート領域６との接合
部の耐圧を向上させるために設けられたドレインバッフ
ァ領域、７はドレイン領域である。FIG. 1 shows a structural cross-sectional view of a conventional vertical MO8FET. In FIG. 1, 1 is a source electrode, 2 is a 5i02 film for insulation between the eyebrows, 3 is a gate electrode, 4 is a source region, and 5
6 is a pack gate region, 6 is a drain buffer region provided to improve the breakdown voltage at the junction with the pack gate region 6, and 7 is a drain region.
以上のように構成された縦型ＭＯ８ＦＥＴについて、以
下その動作について説明する。まず、構成を具体的に述
べるためＫｐチャネル型ＭＯＳＦＥＴの動作について説
明する。尚、この場合は４は？領域、５はｎ領域、６は
ｐ−領域、７はｐ＋領領域なる。ソース４に対してドレ
イン７をマイナス電位とするとし、ゲート３をソース電
位を等しくすると、ゲート３とパックゲート５とのオー
バーラツプ部にチャネルは形成されず、ソース４とドレ
イン７に電流は流れない。ゲート３にソース４よりも負
の電圧を印加してゆくと、チャネルがオーバーラツプ領
域に形成され、電流が流れる。The operation of the vertical MO8FET configured as above will be described below. First, in order to specifically describe the configuration, the operation of the Kp channel type MOSFET will be explained. In this case, what about 4? 5 is an n region, 6 is a p- region, and 7 is a p+ region. Assuming that the drain 7 has a negative potential with respect to the source 4, and the gate 3 has the same source potential, no channel will be formed in the overlap between the gate 3 and the pack gate 5, and no current will flow between the source 4 and the drain 7. . When a voltage more negative than that of the source 4 is applied to the gate 3, a channel is formed in the overlap region and current flows.
次に、従来例のもつ欠点を第２図を用いて説明する。第
２図は、従来の縦型ＭＯ８ＦＥＴの等価回路を示すもの
である。１１は、ドレイン電極端子、１２はゲート電極
端子、１３はソース電極端子、１４はパックゲート領域
６とドレインバッファ領域６との間に形成されるダイオ
ード、１５は寄生ＰＮＰ）ランジスタ、１６はパックゲ
ート領域５の内部抵抗を表わしている。ドレイン電極を
負側に電圧印加してゆくと、終には寄生ダイオード１４
がブレークダウンし、その際に生じるブレークダウン電
流の一部は、寄生バイポーラトランジスタ１５をＯＮに
する働きをする。その結果、ブレークダウン電流は急激
に増大し、素子の破壊に至らせる場合がある。このため
ブレークダウン時に電流を流しても破壊されにくい縦型
ＭＯ３ＦＥＴの開発が望まれていた。Next, the drawbacks of the conventional example will be explained using FIG. 2. FIG. 2 shows an equivalent circuit of a conventional vertical MO8FET. 11 is a drain electrode terminal, 12 is a gate electrode terminal, 13 is a source electrode terminal, 14 is a diode formed between the pack gate region 6 and the drain buffer region 6, 15 is a parasitic PNP) transistor, and 16 is a pack gate It represents the internal resistance of region 5. When voltage is applied to the drain electrode on the negative side, eventually the parasitic diode 14
breaks down, and a portion of the breakdown current generated at that time serves to turn on the parasitic bipolar transistor 15. As a result, the breakdown current increases rapidly, which may lead to destruction of the device. For this reason, it has been desired to develop a vertical MO3FET that is less likely to be destroyed even when current is applied during breakdown.
発明の目的
本発明は、上記欠点に鑑み、ブレークダウン電流で破壊
を生じないような新しい構造の縦型ＭＯ３ＦＥＴを提供
するものである。OBJECTS OF THE INVENTION In view of the above-mentioned drawbacks, the present invention provides a vertical MO3FET with a new structure that does not cause destruction due to breakdown current.
発明の構成
この目的を達成するために、本発明の縦型ＭＯ３ＦＥＴ
は、ソースとパックゲート間がショットキー接合で形成
されている。この構成によってブレークダウン電流を流
しても寄生バイポーラトランジスタが存在しないために
、素子の破壊は生じにくくなる。Structure of the Invention To achieve this objective, the vertical MO3FET of the present invention
A Schottky junction is formed between the source and the pack gate. With this configuration, even if a breakdown current is applied, there is no parasitic bipolar transistor, so the device is less likely to be destroyed.
実施例の説明
以下、本発明の一実施例について図面を参照しながら説
明する。第３図は本発明の一実施例における縦型ＭＯ３
ＦＥＴの構造断面図を示すものである。第３図において
、２１はソース電極、２２はゲート・ソース間の眉間絶
縁のためのＳｉＯ２膜、２３はゲート電極、２４はパッ
クゲート領域２５とショットキー接合を形成するソース
・ショットキー電極、２６はパックゲート領域、２６は
ドレインバッファ層、２７はドレイン領域を示すもので
ある。DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 shows a vertical MO3 in an embodiment of the present invention.
1 shows a cross-sectional view of the structure of an FET. In FIG. 3, 21 is a source electrode, 22 is a SiO2 film for glabellar insulation between the gate and source, 23 is a gate electrode, 24 is a source-Schottky electrode that forms a Schottky junction with the pack gate region 25, and 26 26 is a pack gate region, 26 is a drain buffer layer, and 27 is a drain region.
以上のように構成された縦型ＭＯ３ＦＥＴについて以下
その動作を説明する。縦型ＭＯ３ＦＥＴとしての動作は
従来例と同じである。等価回路を第４図に示す。同図に
おいて、３１はドレイン電極端子、３２はゲート電極端
子、３３はソース電極端子、３４はパックゲートとドレ
インバッファ層間の接合ダイオード、３５はソース・シ
ョットキー電極とパックゲート間のシ苔ットキーダイオ
ード、３Ｂはパックゲート領域の内部抵抗である。The operation of the vertical MO3FET configured as above will be described below. The operation as a vertical MO3FET is the same as the conventional example. The equivalent circuit is shown in FIG. In the figure, 31 is a drain electrode terminal, 32 is a gate electrode terminal, 33 is a source electrode terminal, 34 is a junction diode between the pack gate and the drain buffer layer, and 35 is a Schottky between the source/Schottky electrode and the pack gate. Diode 3B is the internal resistance of the pack gate region.
寄生のバイポーラトランジスタは存在しない。There are no parasitic bipolar transistors.
以上のように、本実施例によれば、ソース領域がショッ
トキー接合で置き換えられるととＫよって、寄生バイポ
ーラトランジスタの存在を抹消し、ブレークダウン電流
による破壊の問題を解消することができる。As described above, according to this embodiment, when the source region is replaced with a Schottky junction, the existence of the parasitic bipolar transistor can be eliminated and the problem of destruction caused by breakdown current can be solved.
なお・本実施例は、ｐチャネル縦型ＭＯ９ＦＸ。Note that this example is a p-channel vertical MO9FX.
Ｔについて説明したが、ｎチャネル縦型ＭＯ３ＦＥＴに
ついても同様のことが言えるのは言うまでもない。Although the explanation has been made regarding T, it goes without saying that the same can be said about n-channel vertical MO3FET.
発明の効果
以上のように、本発明はソースとパックゲート間をショ
ットキー接合することで、寄生バイポーラトランジスタ
の効果を抹消でき、破壊しにくい縦型ＭＯ３ＦＥＴを得
ることができ、その実用的効果は大なるものがある。Effects of the Invention As described above, the present invention makes it possible to eliminate the effect of a parasitic bipolar transistor by forming a Schottky junction between the source and the pack gate, and to obtain a vertical MO3FET that is difficult to destroy.The practical effects of the present invention are as follows. There is something big.
第１図は、従来の縦型ＭＯ３ＦＥＴの構造断面図、第２
図は従来の縦型ＭＯ３ＦＥＴの等価回路図、第３図は本
発明の一実施例における縦型ＭＯＳＦＥＴの構造断面図
、第４図は本発明の一実施例における縦型ＭＯ３ＦＥＴ
の等価回路図である。
２１・・・・・・ソース電極、２３・・・・ゲート電極
、２４・・・・・ショットキー電極、２６・・・・・・
パックゲート領域、２６・・・・−・ドレインバッファ
層、２７・・・・・ドレイン領域。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
筒３図Figure 1 is a cross-sectional view of the structure of a conventional vertical MO3FET;
The figure is an equivalent circuit diagram of a conventional vertical MO3FET, Figure 3 is a cross-sectional view of a vertical MOSFET according to an embodiment of the present invention, and Figure 4 is a vertical MOSFET according to an embodiment of the present invention.
FIG. 21... Source electrode, 23... Gate electrode, 24... Schottky electrode, 26...
Pack gate region, 26...- Drain buffer layer, 27... Drain region. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Diagram 3
Claims (1)
て形成されていることを特徴とする縦型ＭＯＳＦＥＴ。A vertical MOSFET characterized in that a source region is formed by a Schottky junction in a pack gate region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59192888A JPH067597B2 (en) | 1984-09-14 | 1984-09-14 | Vertical MOSFET |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59192888A JPH067597B2 (en) | 1984-09-14 | 1984-09-14 | Vertical MOSFET |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6170760A true JPS6170760A (en) | 1986-04-11 |
| JPH067597B2 JPH067597B2 (en) | 1994-01-26 |
Family
ID=16298642
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59192888A Expired - Lifetime JPH067597B2 (en) | 1984-09-14 | 1984-09-14 | Vertical MOSFET |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH067597B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02281661A (en) * | 1989-04-21 | 1990-11-19 | Nec Corp | Vertical type field effect transistor |
| JP2009105421A (en) * | 2001-11-21 | 2009-05-14 | Fuji Electric Device Technology Co Ltd | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58223362A (en) * | 1982-06-21 | 1983-12-24 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device |
-
1984
- 1984-09-14 JP JP59192888A patent/JPH067597B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58223362A (en) * | 1982-06-21 | 1983-12-24 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02281661A (en) * | 1989-04-21 | 1990-11-19 | Nec Corp | Vertical type field effect transistor |
| JP2009105421A (en) * | 2001-11-21 | 2009-05-14 | Fuji Electric Device Technology Co Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH067597B2 (en) | 1994-01-26 |
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