JPH02281661A - Vertical type field effect transistor - Google Patents

Abstract

PURPOSE:To improve a transistor of this design in its withstanding property to an inductance load by a method wherein a source region is formed of metal silicide buried in an opposite conductivity type has base region formed on the surface of a certain conductivity type semiconductor substrate. CONSTITUTION:In a vertical type field effect transistor, an N<+> silicon substrate 1 is made to serve as an N drain region, an N<-> drain region 2 is epitaxially grown thereon, a P base region 3 is formed, an oxide film is deposited on the surface, a window is provided, metal silicide is deposited in the recess formed through etching, the oxide film is removed, and a silicide layer 5 is formed in the recess to serve as a source region. When a voltage is applied to a gate electrode 7, an inversion layer 11 is formed in a channel region, and when a voltage is applied between a source electrode 9 and a drain electrode 10, electrons discharged from the source electrode 9 reach to the drain electrode 10 passing through the silicide layer 5, the P base region 3 just under the gate electrode 7, and the inversion layer 11, and as the N<+> source region 4 has been replaced with the silicide layer 5, an NPN parasitic transistor is not formed. Therefore, a field effect transistor of this design can be made large in withstanding property to an inductance load.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to vertical field effect transistors.

[Conventional technology]

FIG. 3 is a schematic cross-sectional view of an example of a conventional vertical field effect transistor.

An N- drain region 2 is provided on an N+ silicon substrate 1,
A P base region 3 is provided in this. An N+ source region 4 is provided within the P base region 3. A gate electrode IF+7 is provided via the gate oxide film 6. After covering the oxide film 8, an opening is opened, a source electrode 9 is provided, and a train electrode 10 is formed on the back surface of the substrate.
form.

In such a vertical electrolytic transistor, a parasitic NPN transistor is formed in which the N drain region 2 is the collector, the P base region 3 is the base, and the N'' source region 4 is the emitter.

[Problem to be solved by the invention]

The above-described conventional vertical field effect transistor has a structure in which a parasitic transistor is built in, and therefore, when this parasitic transistor becomes conductive, there is a problem that the transistor is destroyed due to current concentration. In order to make it difficult for the parasitic transistor to conduct, there is a method of reducing the base resistance and reducing the DC amplification factor hPE, but doing so has problems such as difficulty in determining conditions because it greatly affects other characteristics. There is.

[Means to solve the problem]

The vertical field effect transistor of the present invention includes a semiconductor substrate of one conductivity type serving as a drain region, a base region of opposite conductivity type formed on the surface of the semiconductor substrate, and a metal silicide embedded in the base region. a source region to be formed, a gate electrode provided above from an edge of the surface of the source region to an edge of the surface of the base region via an insulating film, and a drain provided on the back surface of the semiconductor substrate. and an electrode.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic cross-sectional view of one embodiment of the present invention.

The N+ silicon substrate 1 is used as an N drain region, and an N
- epitaxially grow the drain region 2 to form the P base region 3;

An oxide film is provided on the surface, a window is opened in the portion where the source region will be formed, and the P base region 3 is etched to form a recess. A metal silicide such as molybdenum silicide or titanium silicide is deposited to a thickness that fills the recessed portion using the CVD method. By removing the oxide film, silicide layer 5 is formed only in the recesses. Let this be the source area.

Next, a gate oxide film 6 is provided, and a gate electrode 7 made of polycrystalline silicon is formed thereon. The end of the gate electrode 7 and the end of the silicide M5 are formed to match in position W. CVD
A hole is formed in the upper part of the silicide layer 5, a source electrode 9 is formed of a metal such as AJI, and a drain electrode 10 is formed on the back surface of the silicon substrate 1.

FIG. 2 is a schematic cross-sectional view for explaining the operation of the embodiment shown in FIG. 1.

By applying a voltage to the gate electrode 7, an inversion layer 11 is formed in the channel region. When a voltage is applied between the source electrode 9 and the drain electrode, electrons emitted from the source electrode 9 pass from the silicide layer 5 to the P base region 3 directly under the gate electrode 7 and the inversion layer 11, and then pass through the drain electrode lO leading to.

In the present invention, the part that becomes the emitter of the parasitic transistor (
Since the N+ source region 4) in FIG. 3 has been replaced by the silicide layer 5, no NPN parasitic transistor is formed. Therefore, no undesired current will flow, and the transistor will not be destroyed due to current concentration.

In addition, there is no need to limit the impurity concentration of the P base region 3 to suppress conduction of parasitic transistors. can be selected.

Although the above embodiment has been explained using an N-channel type, it goes without saying that the present invention can be applied to a P-channel type in the same manner.

〔Effect of the invention〕

As described above, the present invention eliminates the presence of parasitic transistors by forming the source region of the vertical field effect transistor with metal silicide, and therefore has the effect of increasing the inductance load capacity.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view of one embodiment of the present invention, and FIG.
FIG. 3 is a schematic cross-sectional view of an example of a conventional vertical field effect transistor. 1...N+ silicon substrate, 2...N drain region,
3...P base region, 4...N+ source region, 5.
... Silicide layer, 6... Gate oxide film, 7... Gate electrode, 8... Oxide film, 9... Source electrode, 10...
- train electrode, 11... inversion layer, 12... depletion layer.

Claims (1)

[Claims] a semiconductor substrate of one conductivity type serving as a drain region; a base region of opposite conductivity type formed on the surface of the semiconductor substrate; a source region formed of metal silicide embedded in the base region; and the source region. A vertical semiconductor substrate comprising: a gate electrode provided above from an end of the surface of the semiconductor substrate to an end of the surface of the base region via an insulating film; and a drain electrode provided on the back surface of the semiconductor substrate. type field effect transistor.