JPH04280474A - Soi structure mosfet - Google Patents

Abstract

PURPOSE:To make an ohmic connection between an Si region where an MOSFET channel is formed and a source electrode of the MOSFET in the MOSFET in SOI structure and obtain MOSFET without any kink effect. CONSTITUTION:In terms of MOSFET in SOI structure, an Si region (p region) in which an MOSFET channel is formed, is adapted to make an ohmic connection with a source electrode 25 of the MOSFET. A hole generated by the impact ionization of hot electrons, flows out routinely from the source electrode 25 placed in ohmic contact with the Si region (p region) so that no hole may be accumulated. This construction makes it possible to eliminate a particular kink effect of this device.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to SOI (Silico
MOS with n On Insulator structure
It is related to FET.

0002

[Prior Art] Conventionally, technologies in this field include:
For example, (1) K. Kato, T. Wada, K. Ta
niguchi, IE3 Trans. on E. D
．． ED-32 (1985) P. 458, (2) J-P.
Collinge, IE3 EDL 9 (1988) P
．． There was one described in 97 etc.

FIG. 3 is a block diagram of a conventional MOSFET having an SOI structure. As shown in this figure, a back gate oxide film 2 is provided on a back gate electrode 1. A Si layer 3 is provided on the back gate oxide film 2, and a source region 4 and a drain region 5 are formed in this Si layer 3. Its source area 4
A gate oxide film 6 is formed between the drain region 5 and the drain region 5, and a gate electrode 7 is provided on the gate oxide film 6. In other words, it has a structure in which a MOSFET is formed in the Si layer 3. By adopting such a structure, the MOSFET can be connected to the back gate electrode (usually a Si substrate) 1 by the back gate oxide film 2.
Since the insulation is improved, when an LSI using this MOSFET is constructed, each MOSFET can be ideally isolated.

[0004] Also, regarding the wiring provided on the MOSFET shown in FIG. 3, the capacitance between the wiring and the Si substrate can be reduced by the back gate oxide film 2, so that a high-speed etching element can be realized.

[0005]

[Problems to be Solved by the Invention] However, as long as the MOSFET has the above-mentioned SOI structure, as shown in the above-mentioned document, there is a kink (kink) peculiar to this structure.
) There was a problem that the effect occurred. This kink effect will be explained.

[0006] An n-channel MOSFE with the structure shown in FIG.
Think about T. In the figure, 11 is a back gate electrode;
2 is a back gate oxide film, 13 is a p region, 14 is a source (n+) region, 15 is a source electrode, and 16 is a drain (
17 is a drain electrode, 18 is a gate oxide film, and 19 is a gate electrode. Here, the p region 13 where the channel is formed is insulated by the n+/p junction with the source (n+) region 14 and drain (n+) region 16, and the depletion layer directly under the gate oxide film 18 and back gate oxide film 12. A floating region is formed.

During normal operation, the back gate electrode 11,
The source electrode 15 is set to 0V, and a positive voltage of about 5V is applied to the drain electrode 17. When a positive voltage is applied to the gate electrode 19, a channel is formed in the Si near the gate oxide film 18, and the MOSFET is turned on. At this time, a region insulated by the depletion layer of the n+/p junction of the reverse biased source and drain, the back gate oxide film, and the depletion layer near the channel is generated in the portion of the Si layer where the channel is not formed.

[0008] This area is described in literature (2) as a floating substrate.
rate). Since this floating substrate has a low potential, the source (n+) region 14
Hot electrons flow through the channel to the drain (n+) region 16.
on), holes generated by impact ionization flow in and accumulate in this region. This causes the potential in this region to rise, resulting in
Because the threshold voltage of the MOSFET decreases,
Drain current increases. Since the amount of holes generated increases with increasing drain current, the relationship between drain voltage and drain current does not show the usual saturation, but shows a kink at a certain drain voltage, and again increases with drain voltage. . This is the kink effect, and when this phenomenon occurs, the operating characteristics of the MOSFET cannot be easily predicted, and the characteristics also change easily.
There was a problem.

As a means to avoid this phenomenon, the above-mentioned document (2) proposes a method of reducing the thickness of the Si layer shown in FIG. 4. That is, in an SOI n-channel MOSFET with a gate length of 2 μm and a gate oxide film thickness of 15 nm, a kink effect was observed when the thickness of the Si layer 3 was 400 nm, but no kink effect occurred when the thickness was 100 nm. The reason for this is that when the thickness of the Si layer is 100 nm,
Impact ionization is reduced by the depletion layer spreading throughout the Si layer, and floating/
It is said that this is due to the disappearance of the area that should be called the substrate. As described above, the kink effect can be reduced by reducing the thickness of the Si layer, but a complicated process is required to reduce the thickness of the Si layer.

[0010] The present invention is directed to the SOI structure MOS described above.
The purpose is to avoid the process difficulty of reducing the thickness of the Si layer to 100 nm or less in order to reduce the kink effect in FETs, and to provide a MOSFET with an SOI structure without kink effects through a simple process. shall be.

[0011]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a MOSFET with an SOI structure in which a Si region in which a channel of the MOSFET is formed is insulated from a substrate by an insulating film. In, the above S
The i-region has a structure in which it is ohmically connected to the source electrode of the MOSFET.

0012

According to the present invention, as described above, in a MOSFET having an SOI structure, the Si region in which the channel of the MOSFET is formed is ohmically connected to the source electrode of the MOSFET. Therefore, holes generated by impact ionization of hot electrons constantly flow out from the source electrode in ohmic contact with the Si region, and no accumulation of holes occurs.

[0013] Therefore, the kink effect peculiar to the device can be eliminated.

[0014]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic diagram of a MOSFET having an SOI structure showing a first embodiment of the present invention. In the conventional device, as shown in FIG. 4, a p region 13 in which a channel is formed has an n+/p junction with a source (n+) region 14 and a drain (n+) region 16, a gate oxide film 18, and a back gate. An insulated floating region is formed by the depletion layer directly under the oxide film 12, but in this embodiment, as shown in FIG. The shape is such that it is connected to the source electrode 25 through an ohmic contact. Therefore, no floating region is formed. In FIG. 1, 21 is a back gate electrode, 22 is a back gate oxide film, 26 is a drain (n+) region, 27 is a drain electrode, 28 is a gate oxide film, and 29 is a gate electrode.

Here, in fact, FIG. 4 (conventional structure) and FIG.
The central part of the Si layer in the two structures (structures of the present invention) (
The potential distribution of the A-A' line and the B-B' line) is
Figure 2 shows the results calculated using the dimensional device simulator.
Shown below. In this figure, the graph a shows the case of FIG. 1 (the structure of the present invention), and the graph b shows the case of FIG. 4 (the conventional structure). Here, the source voltage is 0V, the drain voltage is 5V, and the gate and back gate voltages are 2.5V.
, the Si layer thickness was 2 μm, the gate length was 1.6 μm, and the gate and back gate oxide films were 10 nm.

As is clear from FIG. 2, in case b of FIG. 4 (conventional structure), a well with a low potential is formed in the p region 13. This corresponds to the floating area mentioned above. Channel drain (n+
) Holes generated by hot electrons near the region 16 are accumulated in this well, resulting in a kink effect.

On the other hand, in case a of FIG. 1 (structure of the present invention), such a potential well is not formed;
Holes generated by impact ionization of hot electrons constantly flow out from source electrode 25 which is in ohmic contact with p region 23, and no accumulation of holes occurs. Further, according to calculations, no kink effect was observed in the drain voltage vs. drain current characteristics in FIG. 1 (structure of the present invention).

FIG. 5 shows a second embodiment of the present invention.
1 is a schematic configuration diagram of a MOSFET structure. As shown in this figure, a back gate oxide film 32 is formed on a Si substrate (back gate electrode) 31. A p region 33 is formed thereon, a p+ region 34 and a source region 35 are formed on one side, and a source electrode 36 is provided so as to short-circuit the p+ region 34 and source region 35. A p+ region 37 and a drain region 38 are formed on the other side, and a drain electrode 39 is provided so as to short-circuit the p+ region 37 and drain region 38. A gate oxide film 40 is formed between the source region 35 and the drain region 38, and a gate electrode 41 is formed thereon.
will be established.

The manufacturing process of the SOI structure MOSFET will be explained with reference to FIG. First, Figure 6 (a
), oxygen ions are implanted into a Si substrate and annealed at a high temperature to embed an oxide film in the substrate, which is used as a back gate oxide film 52. That is, a Si substrate 51, a back gate oxide film 52, and a Si layer 53 are formed.

Next, as shown in FIG. 6(b), after oxidizing the Si layer (p region) 53 and forming a gate oxide film 54,
A gate electrode 55 is formed of n+ polycrystalline silicon (polySi). Furthermore, after forming an n+ layer 56 by As+ ion implantation, the gate electrode 55 is covered with an oxide film 57. Then, as shown in FIG. 6(c), M
The Si layer (p region) 53 is etched leaving the OSFET region. Further, a source region 58 and a drain region 59 are formed from p+ polycrystalline silicon, a source electrode 60 and a drain electrode 61 are further formed, and after depositing BPSG 62 as an insulating film, a contact hole 63 is opened.

With this structure, the source electrode 60 and the drain electrode 61 made of p+ polycrystalline silicon are in contact with the Si layer (p region) 53, and the dopant B (boron) is more concentrated than the p+ polycrystalline silicon. diffuses into p region 53 to form a p+ region, source electrode 60 and p region 53 are ohmically connected, and the same effect as the embodiment of FIG. 1 can be obtained.

At this time, drain electrode 61 and p region 53 are also ohmically connected, but no problem occurs. FIG. 7 is a schematic diagram of a MOSFET having an SOI structure showing a third embodiment of the present invention. Also in this embodiment, in order to establish an ohmic connection between source electrode 76 and p region 73,
A p+ region 74 is formed in the source region by ion implantation, and a source electrode 76 (for example, n+ polySi) is formed.
P+ region 74 and n+ region 75 are formed so as to be short-circuited. In addition, in FIG. 7, 71 is a back gate electrode, 72 is a back gate oxide film, 77 is a drain region,
78 is a drain electrode, 79 is a gate oxide film, and 80 is a gate electrode.

With this configuration, the same effects as the embodiment shown in FIG. 1 can be obtained. FIG. 8 is a schematic configuration diagram of a MOSFET having an SOI structure showing a fourth embodiment of the present invention. In this embodiment, p+
Region 94 is formed deeper than n+ region 95, and p+ region 94 forms an ohmic connection with p region 93. Furthermore, since the breakdown voltage of the n+/p+ junction is as low as several mV, the n+ region 95 is
This means that it is substantially ohmically connected to the p region 93 through the + layer 94, and the same effect as in Example 1 of FIG. 1 can be obtained. In FIG. 8, 91 is a back gate electrode, 92 is a back gate oxide film, 97 is a drain region, 99 is a gate oxide film, and 100 is a gate electrode.

Further, in this embodiment, there is no need to newly form a layer of n+ polycrystalline silicon or the like as a source electrode or a drain electrode, resulting in a simple structure. Here, the back gate electrode may be a Si substrate or may be a newly provided conductive material. Also, these M
As long as the OSFET has the configuration described in the above embodiments, it may be formed not on a Si substrate but on a substrate made of another material, such as a glass substrate.

Furthermore, although the case of an n-channel MOSFET has been described, the same effect can be obtained even if the structure is made into a p-channel MOSFET by changing the n+ region to the p+ region, the p+ region to the n+ region, the p layer to the n layer, etc. Effects can be obtained. Note that the present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention.
These are not excluded from the scope of the present invention.

[0026]

As described in detail above, according to the present invention, in a MOSFET having an SOI structure, a p-type (n-channel MOSFET) in which a channel (inversion layer) is formed,
Since the structure is such that the ET) or n-type (p-channel MOSFET) region is ohmically connected to the source electrode, the kink effect that could only be reduced by thinning the Si layer does not occur, making it possible to create an SOI with stable operating characteristics. A MOSFET with this structure can be realized through a simple manufacturing process.

[Brief explanation of the drawing]

FIG. 1: MO of SOI structure showing a first embodiment of the present invention.
It is a schematic block diagram of SFET.

FIG. 2 is a diagram showing the results of calculation using a two-dimensional device simulator of the potential distribution in the central portion of the Si layer in the two structures of FIG. 4 (conventional structure) and FIG. 1 (structure of the present invention).

FIG. 3 is a block diagram showing the structure of a conventional SOIMOSFET.

FIG. 4 is a diagram illustrating the kink effect of a conventional SOIMOSFET.

FIG. 5: MO of SOI structure showing a second embodiment of the present invention.
It is a schematic block diagram of SFET.

FIG. 6: MO of SOI structure showing a second embodiment of the present invention.
It is a sectional view of the manufacturing process of SFET.

FIG. 7: MO of SOI structure showing a third embodiment of the present invention.
It is a schematic block diagram of SFET.

FIG. 8: MO of SOI structure showing a fourth embodiment of the present invention.
It is a schematic block diagram of SFET.

[Explanation of symbols]

21, 71, 91 Back gate electrode 22, 32
, 52, 72, 92 back gate oxide film 23,
33, 53, 73, 93 p region (Si region) 2
4, 35, 58 Source (n+) area 25, 3
6, 60, 76 source electrode 26, 38, 59,
77, 97 Drain (n+) region 27, 39, 61, 78 Drain electrode 28, 4
0, 54, 79, 99 Gate oxide film 29, 41
,55,80,100 Gate electrode 31,51
Si substrate (back gate electrode) 34, 37, 74
, 94 p+ region 56 n+ layer 57 oxide film 62 BPSG 63 contact hole 75, 95 n+ region

Claims (1)

[Claims] 1. In a MOSFET having an SOI structure in which a Si region where a channel of the MOSFET is formed is insulated from a substrate by an insulating film, the Si region is ohmically connected to a source electrode of the MOSFET. MOSFET with SOI structure.