JP2012151496A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device accelerated in switching speed of a transistor.SOLUTION: A semiconductor device comprises: a semiconductor layer 10 formed on a part of an insulating layer; a first transistor 20 formed on a side surface 10a of the semiconductor layer 10 and including a first gate insulating film 21, a first gate electrode 22, and two first impurity layers 23, 24 that become a source and a drain; and a second transistor 30 formed on a side surface 10b of the semiconductor layer 10 and including a second gate insulating film 31, a second gate electrode 32, and two second impurity layers 33, 34 that become a source and a drain.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof. In particular, the present invention relates to a semiconductor device in which the switching speed of a transistor is increased and a manufacturing method thereof.

  FIG. 8 is a cross-sectional view for explaining the configuration of a conventional semiconductor device. In this figure, an n-type well 100 a is formed in a p-type silicon layer 100. An n-type impurity layer 100b is formed in the n-type well 100a, and a voltage Vdd is applied to the n-type well 100a through the n-type impurity layer 100b.

  A p-type MOS transistor 110 and a p-type MOS varactor 120 are disposed adjacent to each other in the n-type well 100a. The voltage Vdd is also applied to the source 113 of the p-type MOS transistor 110 and the source 123 and drain 124 of the p-type MOS varactor 120.

  A signal Sin is applied to the gate electrode 112 of the p-type MOS transistor 110, and a differential signal XSin of the signal Sin is input to the gate electrode 122 of the p-type MOS varactor 120. For this reason, when the p-type MOS transistor 110 is switched from on to off or from off to on, the charge (for example, electrons) accumulated in the channel region of the p-type MOS transistor 110 and the channel region of the p-type MOS varactor 120 are accumulated. The charges (for example, holes) that have been exchanged are exchanged. For this reason, the p-type MOS transistor 110 switches at a higher speed than when the p-type MOS varactor 120 is not provided (see, for example, Patent Document 1).

JP 2002-124635 A (FIG. 2)

If a transistor having a higher switching speed than the transistor having the above structure is realized, the operation speed of the semiconductor device is further increased.
The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device in which the switching speed of a transistor is increased and a method for manufacturing the same.

In order to solve the above problems, a semiconductor device according to the present invention includes a semiconductor layer formed on a part of an insulating layer,
A first transistor formed in a first region on a side surface of the semiconductor layer and having a first gate insulating film, a first gate electrode, a first source impurity layer, and a first drain impurity layer;
A second gate insulating film, a second gate electrode, a second source impurity layer, and a second gate insulating film formed on a side surface of the semiconductor layer opposite to the first region through the semiconductor layer; A second transistor having a second drain impurity layer;
A well formed in the semiconductor layer and common to the first transistor and the second transistor;
It comprises.

  In this semiconductor device, a case is considered where a first signal is input to the first gate electrode and a second signal obtained by inverting the first signal is input to the second gate electrode. In this case, charges (for example, holes) accumulated in the channel region of the first transistor and charges (for example, electrons) accumulated in the channel region of the second transistor have opposite polarities. For this reason, when the first transistor is on, the second transistor functions as a varactor, and when the second transistor is on, the first transistor functions as a varactor.

  When the first transistor is switched from on to off, the charge accumulated in the channel region of the first transistor and the charge accumulated in the channel region of the second transistor are: Exchanged through the well. The same applies when the first transistor switches from off to on.

  Further, the first region in which the first transistor is formed and the second region in which the second transistor is formed are opposed to each other with the semiconductor layer interposed therebetween. For this reason, the distance that the charge moves during the charge exchange is shorter than that in the conventional example.

  Accordingly, the switching speed of each of the first transistor and the second transistor is higher than that of the conventional example described above.

  Further, since the charges accumulated in the channel regions of the first transistor and the second transistor are exchanged when these transistors are switched, they are reused without going out of the semiconductor layer. The Therefore, power consumption of the first transistor and the second transistor is reduced.

  The first gate electrode and the second gate electrode are, for example, polysilicon electrodes, but may be metal electrodes.

The thickness of the semiconductor layer sandwiched between the first gate insulating film and the second gate insulating film is preferably 0.35 fμE or less. Where f = clock frequency of the semiconductor device (1 / s), μ = hole mobility of the semiconductor device (cm ² / sV), E = channel under the first gate insulating film and the second gate This is the maximum value of the electric field strength (V / cm) in each channel under the insulating film.

  The first gate insulating film and the second gate insulating film are preferably arranged at positions facing each other through the semiconductor layer, but may be shifted.

  The first source impurity layer and the second source impurity layer may be connected to each other to form one impurity layer. In this case, the thickness of the semiconductor layer in which the first source impurity layer and the second source impurity layer are located is the same as the thickness of the semiconductor layer in which the first drain impurity layer and the second drain impurity layer are located. It may be thinner.

  The first source impurity layer and the second source impurity layer are disposed at positions facing each other through the semiconductor layer, and the first drain impurity layer and the second drain impurity layer Are disposed at positions facing each other through the semiconductor layer, the semiconductor layer is a first oxide layer sandwiched between the first source impurity layer and the second source impurity layer And a second oxide layer sandwiched between the first drain impurity layer and the second drain impurity layer. In this case, among the capacitances of the first transistor and the second transistor, the capacitance caused by the source impurity layer and the drain impurity layer is reduced, so that the power consumption is further reduced.

  The semiconductor layer is, for example, a substantially rectangular parallelepiped. In this case, the first region is a first side surface of the substantially rectangular parallelepiped, and the second region is a surface opposite to the first side surface. The first side surface and the opposite surface are preferably side surfaces in the longitudinal direction.

A method of manufacturing a semiconductor device according to the present invention includes a step of forming a substantially rectangular parallelepiped semiconductor layer that functions as a well by introducing impurities on a part of a first insulating film;
Forming a first gate insulating film on a first side surface of the semiconductor layer and forming a second gate insulating film on a second side surface of the semiconductor layer;
Forming a first gate electrode located on the first gate insulating film and a second gate electrode located on the second gate insulating film;
Forming the first source impurity layer and the first drain impurity layer on the first side surface, and forming the second source impurity layer and the second drain impurity layer on the second side surface; A process.

An upper insulating layer located on the semiconductor layer is formed between the step of forming the semiconductor layer and the step of forming the first and second source impurity layers and the first and second drain impurity layers. Comprising the steps of:
The step of forming the first and second source impurity layers and the first and second drain impurity layers is performed using the first gate electrode, the second gate electrode, and the upper insulating layer as a mask. It may be a step of introducing impurities into the semiconductor layer.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming a substantially rectangular parallelepiped semiconductor layer which functions as a well by introducing impurities on a part of the first insulating film;
A gate insulating film of the first transistor is formed on the first side surface of the semiconductor layer, and a gate insulating film of the second transistor is formed on the second side surface opposite to the first side surface. Process,
A gate electrode of the first transistor is formed on the gate insulating film of the first transistor, and a first electrode on the gate insulating film of the second transistor is positioned opposite to the gate electrode of the first transistor. Forming a gate electrode of the transistor of 2;
By processing a part of the semiconductor layer, the semiconductor layer is adjacent to a region sandwiched between the gate electrode of the first transistor and the gate electrode of the second transistor, and has a thickness larger than that of the other part. Forming a thin thin portion;
By introducing impurities into the semiconductor layer using the gate electrode of the first transistor and the gate electrode of the second transistor as a mask, the impurities are dispersed throughout the thin portion, and the source of the first transistor and A source impurity layer functioning as a common source of the second transistor is formed, a drain impurity layer of the first transistor is formed on the first side surface, and the first transistor is formed on the second side surface. Forming a drain impurity layer of the second transistor separated from the drain impurity layer of the second transistor.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming a substantially rectangular parallelepiped semiconductor layer which functions as a well by introducing impurities on a part of the first insulating film;
A gate insulating film of the first transistor is formed on the first side surface of the semiconductor layer, and a gate insulating film of the second transistor is formed on the second side surface opposite to the first side surface. Process,
Forming a conductive film on the gate insulating film of the first transistor, on the gate insulating film of the second transistor, on the semiconductor layer, and on the upper insulating layer;
By patterning the conductive film, a gate electrode of the first transistor is formed on the gate insulating film of the first transistor, and the first transistor is formed on the gate insulating film of the second transistor. Forming a gate electrode of the second transistor at a position facing the gate electrode of
On the region where the drain impurity layer of the first transistor is formed on the first side surface and on the region where the drain impurity layer of the second transistor is formed on the second side surface, respectively. Forming a coating film;
By introducing impurities into the semiconductor layer under the condition that impurities pass through the coating film, using the gate electrode of the first transistor, the gate electrode of the second transistor, and the upper insulating layer as a mask, A source impurity layer functioning as a source of each of the first and second transistors is formed by diffusing impurities from the first side surface to the second side surface, and the first transistor has a first impurity layer on the first side surface. Forming a drain impurity layer and forming a drain impurity layer of the second transistor separated from the drain impurity layer of the first transistor on the second side surface.

(A) is a perspective view of the semiconductor device according to the first embodiment of the present invention, (B) is a sectional view of (A) cut along a horizontal plane including a straight line AA, and (C) is a semiconductor of (A). The circuit diagram of an apparatus. The graph explaining the relationship between the gate-source voltage Vgs in the p-type MOS transistor and the amount of charge accumulated in the channel region. (A) is a figure which shows an example of the signal S input into the gate electrode 22 of the p-type MOS transistor 20, and the inversion signal XS input into the gate electrode 32 of the p-type MOS transistor 30. (B) and (C) are diagrams for explaining charges in the channel regions of the p-type MOS transistors 20 and 30 when t = t1 and t2 in FIG. 3, respectively. (A) is a perspective view for explaining a manufacturing method of the semiconductor device shown in FIG. 1, (B) is a perspective view for explaining the next step of (A), and (C) is the next of (B). The perspective view for demonstrating the process of (D) is a perspective view for demonstrating the next process of (C), (E) is the perspective view for demonstrating the next process of (D). Sectional drawing explaining the structure of the semiconductor device which concerns on 2nd Embodiment. Sectional drawing explaining the structure of the semiconductor device which concerns on 3rd Embodiment. Sectional drawing explaining the structure of the semiconductor device which concerns on 4th Embodiment. Sectional drawing for demonstrating the structure of the conventional semiconductor device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1A is a perspective view of the semiconductor device according to the first embodiment of the present invention, and FIG. 1B is a cross-sectional view of FIG. 1A cut along a horizontal plane including a straight line AA. FIG. FIG. 1C is a circuit diagram of the semiconductor device illustrated in FIG. In this semiconductor device, p-type MOS transistors 20 and 30 are formed on side surfaces 10a and 10b in the longitudinal direction of a substantially rectangular parallelepiped n-type silicon layer 10, respectively. A signal S is input to the gate electrode 22 of the p-type MOS transistor 20, and an inverted signal XS obtained by inverting the signal S is input to the gate electrode 32 of the p-type MOS transistor 30. That is, a differential signal is input to the p-type MOS transistors 20 and 30.

  The n-type silicon layer 10 is formed on the silicon oxide film 2 on the silicon substrate 1, and the whole functions as an n-type well in a planar-type p-type MOS transistor. That is, the p-type MOS transistors 20 and 30 are formed in the same n-type well. A silicon oxide layer 11 is formed on the upper surface of the n-type silicon layer 10. On the side surface 10a of the n-type silicon layer 10, a gate insulating film 21 of the p-type MOS transistor 20 and p-type impurity layers 23 and 24 serving as a source and a drain are formed. A gate electrode 22 is formed on the gate insulating film 21, and Al alloy wirings 25 and 26 are connected to the p-type impurity layers 23 and 24, respectively.

  Further, on the side surface 10b of the n-type silicon layer 10, a gate insulating film 31 of the p-type MOS transistor 30 and p-type impurity layers 33 and 34 serving as a source and a drain are formed. A gate electrode 32 is formed on the gate insulating film 31, and Al alloy wirings 35 and 36 are formed in the p-type impurity layers 33 and 34, respectively.

  The gate electrodes 22 and 32 are, for example, polysilicon electrodes. In this case, the gate electrodes 22 and 32 are preferably formed of dual-doped polysilicon into which both n-type impurities and p-type impurities are introduced. In this way, the threshold voltage required for the operation of the p-type MOS transistors 20 and 30 can be lowered, so that the p-type MOS transistors 20 and 30 can be miniaturized.

  Further, the gate electrodes 22 and 32 may be metal electrodes. When the gate insulating films 21 and 31 are extremely thinned, if the gate electrodes 22 and 32 are made of polysilicon, the depletion layer capacitance generated in the gate electrodes 22 and 32 becomes a problem. On the other hand, when the gate electrodes 22 and 32 are metal electrodes, such a problem does not occur. The material of the gate electrodes 22 and 32 in this case is preferably a material having a work function in the vicinity of the mid gap in silicon such as silicide metal. Further, since heat is generated during operation, heat resistance is preferable.

  The p-type MOS transistors 20 and 30 are arranged at positions facing each other. Specifically, the gate insulating films 21 and 31, the p-type impurity layers 23 and 33, and the p-type impurity layers 24 and 34 are opposed to each other.

  FIG. 2 is a graph for explaining the relationship between the gate-source voltage Vgs of the p-type MOS transistors 20 and 30 and the amount of charge accumulated in the channel region of the p-type MOS transistors 20 and 30. Hereinafter, the p-type MOS transistor 20 will be described as an example. The voltage Vgs varies depending on the signal S input to the gate electrode 22.

  When the voltage Vgs is negative, an inversion layer having a capacitance Cox is formed in the channel region located under the gate insulating film 21. The charges accumulated in the inversion layer are holes. A depletion layer is formed under the inversion layer, and this depletion layer also has a capacitance Ci. In addition, a potential distribution is generated in the n-type silicon layer 10 due to the formation of the inversion layer. The n-type silicon layer 10 has a capacitance Cb due to this potential distribution. Thus, the capacitance C of the p-type MOS transistor 20 is the sum of the capacitances Cox, Ci, and Cb. However, the capacity Cox is dominant.

  When the negative value of the voltage Vgs is sufficiently large, a strong inversion layer is formed in the p-type MOS transistor 20, and the capacitance C becomes a constant value Cmax. In this state, the p-type MOS transistor 20 is turned on.

  Thereafter, the voltage Vgs is increased from the negative potential toward the zero potential. Then, the holes are dispersed and the inversion layer changes from the intermediate inversion state to the weak inversion state. Thereby, the capacity | capacitance C reduces and becomes the minimum value Cmin. In this state, the p-type MOS transistor 20 is turned off.

  When the voltage Vgs further increases and becomes a positive potential, electrons are accumulated and the capacitance C increases. When the positive potential of the voltage Vgs becomes sufficiently large, the capacitance C of the p-type MOS transistor 20 becomes a constant value Cmax. In this state, the p-type MOS transistor 20 is in an off state and functions as a varactor.

  Thus, when the voltage Vgs changes from a negative potential to a positive potential and the p-type MOS transistor 20 switches from on to off, the charge amount of Q = 2Vs (Cmax−Cmin) needs to move in the channel region. However, Vs = the amplitude of the voltage Vgs. The same applies to the case where the voltage Vgs changes from the positive potential to the negative potential and the p-type MOS transistor 20 changes from the off state to the on state. This relational expression is also applied to a general MOS transistor.

  In a MOS transistor having a general structure, when the frequency of an input signal increases, the movement of holes may not be able to follow the potential change of the signal. In this case, the MOS transistor is not switched on / off.

  On the other hand, as will be described with reference to FIGS. 3A and 3B, in the present embodiment, differential signals are input to the p-type MOS transistors 20 and 30, so The charged charge and the charge stored in the p-type MOS transistor 30 are exchanged at the time of switching. Therefore, even if the frequency of the signal is high, it is switched on / off.

  FIG. 3A is a diagram illustrating an example of the signal S input to the gate electrode 22 of the p-type MOS transistor 20 and the inverted signal XS input to the gate electrode 32 of the p-type MOS transistor 30. 3B and 3C are diagrams for explaining the charges in the channel regions of the p-type MOS transistors 20 and 30 when t = t1 and t2 in FIG. 3A, respectively.

  As shown in FIG. 3A, at t = 0, in a state where the signal S is at a negative high level potential, the p-type MOS transistor 20 is in an on state, and holes serving as carriers are accumulated in the channel region. ing. In this case, since the inverted signal XS is at a positive high level potential, the p-type MOS transistor 30 is in an off state and functions as a varactor, and electrons are accumulated in the channel region.

  At t = t1, the signal S is in the process of falling from a negative high level potential to 0 potential, and the inverted signal XS is in the process of falling from a positive high level potential to 0 potential.

  As shown in FIG. 3B, at t = t1, holes located in the channel region gradually diffuse in the p-type MOS transistor 20, and electrons located in the channel region are diffused in the p-type MOS transistor 30. It gradually spreads.

  Thereafter, as shown in FIG. 3A, when t = t2, the signal S is in a rising process from 0 potential to a positive high level potential, and the inverted signal XS is changed from 0 potential to a negative high level potential. It is in the process of rising.

  As shown in FIG. 3C, at t = t2, the holes move to the channel region of the p-type MOS transistor 30, and the electrons move to the channel region of the p-type MOS transistor 20. Then, the p-type MOS transistor 20 switches from on to off and functions as a varactor. The p-type MOS transistor 30 is switched from off to on.

  Thus, when the p-type MOS transistors 20 and 30 are switched, the electric charges held by each other are exchanged, but the distance that the electric charges move at that time is shorter than that of the conventional example (n-type silicon Less than the thickness d of the layer 10). Therefore, the p-type MOS transistors 20 and 30 are switched at high speed.

For example, when the hole μ = 4 × 10 ² (cm ² / sV: temperature is 300 k, carrier concentration is 10 ¹⁴ to 10 ¹⁵ / cm ³ ) and the source voltage is 1.8 V, the hole drift diffusion rate = 7. 2 × 10 ² (cm ² / s). When the distance d = 200 nm under this condition, the time t required for the hole to move the distance d is 0.55 ps calculated from d = (D × t) ^0.5 . Accordingly, the p-type MOS transistor 20 can be switched from the on state to the off state at a high speed of 350 GHz (requires t = 1 ps), for example.

  In addition, since the charge exchange is performed inside the n-type silicon layer 10, the charge does not move outside the semiconductor device. Therefore, the power consumption of the p-type MOS transistors 20 and 30 at the time of switching is reduced as compared with the conventional case.

Each effect described above becomes larger as the distance d 1 between the gate insulating films 21 and 31 is smaller. The distance d is, _{t r} μE less, that is preferably at 0.35fμE less. However, _tr = rise time of signals S and XS, f = clock frequency (1 / s) of the semiconductor device, μ = hole mobility (cm ² / sV) of the semiconductor device, and E = Maximum value of electric field strength (V / cm) in each of the channel under the first gate insulating film and the channel under the second gate insulating film.

  4 is a perspective view for explaining a method of manufacturing the semiconductor device shown in FIG. First, as shown in FIG. 4A, a silicon oxide film 2 is formed on a silicon substrate 1 by a CVD method, and a silicon film 12 and a silicon oxide film 13 are further formed on the silicon oxide film 2 by a CVD method. And stack in this order. The silicon film 12 is a film that becomes the n-type silicon layer 10, and the silicon oxide film 13 is a film that becomes the silicon oxide layer 11.

  Next, as shown in FIG. 4B, a photoresist film (not shown) is applied on the silicon oxide film 13, and this photoresist film is exposed and developed. As a result, a resist pattern is formed on the silicon oxide film 13. Next, the silicon oxide film 13 and the silicon film 12 are etched using this resist pattern as a mask. Thereby, the silicon oxide film 13 and the silicon film 12 are patterned. Next, an n-type impurity is introduced into the patterned silicon film 12. Thereby, the n-type silicon layer 10 and the silicon oxide layer 11 are formed. Thereafter, the resist pattern is removed.

  Next, as shown in FIG. 4C, the n-type silicon layer 10 is thermally oxidized. Thereby, gate insulating films 21 and 31 are formed in the n-type silicon layer 10.

  Next, as shown in FIG. 4D, a polysilicon film is formed on the entire surface including the gate insulating films 21 and 31. Next, a photoresist film is applied on the polysilicon film, and the photoresist film is exposed and developed. Thereby, a resist pattern is formed on the polysilicon film. Next, the polysilicon film is etched using this resist pattern as a mask. As a result, the polysilicon film is patterned, and gate electrodes 22 and 32 are formed. Thereafter, the resist pattern is removed.

  Thereafter, the gate insulating films 21 and 31 protruding from the gate electrodes 22 and 32 are removed by etching using the gate electrodes 22 and 32 as a mask. Next, P-type impurities are introduced into the n-type silicon layer 10 using the gate electrodes 22 and 32 as a mask. As a result, the p-type impurity layers 23, 24, 33, and 34 shown in FIG. 1B are formed in the n-type silicon layer 10. Here, the distance between the p-type impurity layers 23 and 33 and the distance between the p-type impurity layers 24 and 34 are 2 of the average value of the variation in depth of the p-type impurity layers 23, 24, 33 and 34. It is preferable to make it twice or more.

Next, as shown in FIG. 4E, an Al alloy film is formed on the entire surface including the n-type silicon layer 10 by sputtering. Next, a photoresist film is applied on the Al alloy film, and this photoresist film is exposed and developed. Thereby, a resist pattern is formed on the Al alloy film. Next, the Al alloy film is etched using this resist pattern as a mask. As a result, Al alloy wirings 25, 26, 35, and 36 are formed. Thereafter, the resist pattern is removed.
In this way, the semiconductor device of FIG. 1 is formed.

  As described above, according to the first embodiment of the present invention, the rectangular n-type silicon layer 10 is formed, and the p-type MOS transistors 20 and 30 are formed on the side surfaces 10a and 10b of the n-type silicon layer 10, respectively. Yes. The n-type silicon layer 10 functions as a common well for the p-type MOS transistors 20 and 30. The signal S is input to the gate electrode 22 of the p-type MOS transistor 20, and the inverted signal XS of the signal S is input to the gate electrode 32 of the p-type MOS transistor 30.

  For this reason, charges (holes or electrons) accumulated in the channel regions of the p-type MOS transistors 20 and 30 have opposite polarities. Therefore, when the p-type MOS transistors 20 and 30 are switched, the charges accumulated in the channel regions are exchanged. The side surfaces 10a and 10b are side surfaces in the longitudinal direction of the n-type silicon layer 10 and face each other. Therefore, the distance that the charge moves when the charge is exchanged is shorter than that of the conventional example.

  For this reason, the switching speed of the p-type MOS transistors 20 and 30 is increased. Therefore, a semiconductor device that operates at a high speed (for example, 350 GHz) without using attached circuits such as a ringing prevention circuit (resistance insertion, etc.), a pull-up / pull-down circuit, a push pro circuit, a slew rate control circuit, and a PLL circuit. (For example, an ALU: Arithmetic and Logical Unit register or cache memory) can be provided.

  Further, the charge accumulated in the channel region inside the n-type silicon layer 10 is reused. Therefore, the power consumption of the p-type MOS transistors 20 and 30 is reduced.

  FIG. 5 is a cross-sectional view illustrating a configuration of a semiconductor device according to the second embodiment of the present invention. This figure is a cross-sectional view corresponding to FIG. 1B in the first embodiment. In the present embodiment, the portion of the substantially rectangular parallelepiped n-type silicon layer 10 where the impurity layer serving as the source of the p-type MOS transistors 20 and 30 is formed is thinner than the other regions to form the thin portion 10c. ing.

  In the thin portion 10c, the impurity layers serving as the sources of the p-type MOS transistors 20 and 30 are connected to each other to form one p-type impurity layer 23. For this reason, unlike the first embodiment, it is not necessary to form the Al alloy wiring 35. Hereinafter, the same components as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  In the method of manufacturing the semiconductor device according to the present embodiment, the thin portion 10c is formed in the n-type silicon layer 10 between the step of forming the gate electrodes 22 and 32 and the step of forming the p-type impurity layers 23, 24, and 34. The first embodiment is the same as the first embodiment except that a forming step is included.

  The details of the process of forming the thin portion 10c in the n-type silicon layer 10 are as follows. First, a photoresist film is applied on the entire surface including the n-type silicon layer 10, and the photoresist film is exposed and developed. Thereby, a resist pattern is formed on the entire surface including the n-type silicon layer 10. Next, the n-type silicon layer 10 is etched using this resist pattern as a mask. As a result, a thin portion 10 c is formed in the n-type silicon layer 10. Thereafter, the resist pattern is removed.

  According to the second embodiment, the same effect as that of the first embodiment can be obtained. In addition, the formation method of the thin part 10c is not restricted to an above-described example. For example, when the n-type silicon layer 10 is formed by patterning the silicon film 12 and the silicon oxide film 13 shown in FIG. 4, the thin portion 10c may be formed.

  FIG. 6 is a cross-sectional view illustrating a configuration of a semiconductor device according to the third embodiment of the present invention. This figure is a cross-sectional view corresponding to FIG. 1B in the first embodiment. The semiconductor device according to this embodiment is related to the second embodiment except that the portion of the n-type silicon layer 10 where the p-type impurity layer 23 is formed has the same thickness as the other portions. The configuration is the same as that of the semiconductor device. Hereinafter, the same components as those of the second embodiment are denoted by the same reference numerals, and description thereof is omitted.

  The manufacturing method of the semiconductor device according to the present embodiment is the same as that of the second embodiment except that there is no step of forming the thin portion 10c and details of the steps of forming the p-type impurity layers 23, 24, and 34. This is the same as the manufacturing method of the semiconductor device.

  In the present embodiment, details of the process of forming the p-type impurity layers 23, 24, and 34 are as follows. First, a silicon oxide film (not shown) is thinly formed on the entire surface including the n-type silicon layer 10 by, for example, a CVD method, and this silicon oxide film is patterned. As a result, regions of the n-type silicon layer 10 where the p-type impurity layers 24 and 34 are formed are covered with the thin silicon oxide film. Next, impurities are introduced into the n-type silicon layer 10 by thermal diffusion. At this time, the thermal diffusion conditions are set so that the impurities pass through the thin silicon film. As a result, the region covered with the silicon oxide film has a shallower impurity layer than the region where the p-type impurity layer 23 is formed. Thereby, p-type impurity layers 23, 24, and 34 are formed. Thereafter, the aforementioned silicon oxide film is removed.

  According to the third embodiment, the same effect as that of the first embodiment can be obtained.

  FIG. 7 is a cross-sectional view illustrating a configuration of a semiconductor device according to the fourth embodiment of the present invention. This figure is a cross-sectional view corresponding to FIG. 1B in the first embodiment. In the present embodiment, in the n-type silicon layer 10, a portion sandwiched between the p-type impurity layers 23 and 33 and a portion sandwiched between the p-type impurity layers 24 and 34 constitute the silicon oxide layer 14. Except for this point, the configuration is the same as that of the semiconductor device according to the first embodiment. Hereinafter, the same components as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  As described with reference to FIG. 2 in the first embodiment, the capacitance C of the p-type MOS transistors 20 and 30 includes the capacitance Cox due to the inversion layer, the capacitance Ci due to the depletion layer, and the potential in the n-type silicon layer 10. It becomes the sum with the capacity Cb by distribution. In the present embodiment, since the silicon oxide layer 14 is formed in the n-type silicon layer 10, the capacitance Cb is smaller than that in the first embodiment.

  Therefore, in this embodiment, in addition to the same effect as that of the first embodiment, it is possible to obtain an effect that the power consumption caused by the capacitance C of the p-type MOS transistors 20 and 30 can be reduced.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, each of the p-type MOS transistors 20 and 30 may be an n-type MOS transistor. Even in this case, the above-described effects can be obtained.

  Moreover, although the gate insulating films 21 and 31 of the p-type MOS transistors 20 and 30 are disposed at positions facing each other, the above-described effects can be obtained even when these positions are shifted. However, the greatest effect can be obtained when they are arranged at positions facing each other.

  In each of the embodiments described above, the n-type silicon layer 10 is a substantially rectangular parallelepiped, but may have other shapes (column, cylinder, complex). In these cases, the p-type MOS transistor 20 and the p-type MOS transistor 30 are arranged at positions facing each other through the main body of the n-type silicon layer 10.

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Silicon oxide film, 10 ... P-type silicon layer, 10a, 10b ... Side surface, 10c ... Thin part, 11, 14 ... Silicon oxide layer, 12 ... Silicon film, 13 ... Silicon oxide film, 20, 30 ... p-type MOS transistor, 21,31 ... gate insulating film, 22,32 ... gate electrode, 23,24,33,34 ... p-type impurity layer, 25,26,35,36 ... Al alloy wiring, 100 ... p Type silicon layer, 100a ... n-type well, 100b ... n-type impurity layer, 110 ... p-type MOS transistor, 112,122 ... gate electrode, 113,123 ... source, 120 ... p-type MOS varactor, 124 ... drain

Claims (2)

Forming on a portion of the first insulating film, a semiconductor layer of a straight rectangular parallelepiped that acts as an impurity is not introduced wells,
A gate insulating film of the first transistor is formed on the first side surface of the semiconductor layer, and a gate insulating film of the second transistor is formed on the second side surface opposite to the first side surface. Process,
A gate electrode of the first transistor is formed on the gate insulating film of the first transistor, and a first electrode on the gate insulating film of the second transistor is positioned opposite to the gate electrode of the first transistor. Forming a gate electrode of the transistor of 2;
By processing a part of the semiconductor layer, the semiconductor layer is adjacent to a region sandwiched between the gate electrode of the first transistor and the gate electrode of the second transistor, and has a thickness larger than that of the other part. Forming a thin thin portion;
By introducing impurities into the semiconductor layer using the gate electrode of the first transistor and the gate electrode of the second transistor as a mask, the impurities are dispersed throughout the thin portion, and the source of the first transistor and A source impurity layer functioning as a common source of the second transistor is formed, a drain impurity layer of the first transistor is formed on the first side surface, and the first transistor is formed on the second side surface. Forming a drain impurity layer of the second transistor separated from the drain impurity layer of the second transistor;
A method for manufacturing a semiconductor device comprising: Forming on a portion of the first insulating film, a semiconductor layer of a straight rectangular parallelepiped that acts as an impurity is not introduced wells,
A gate insulating film of the first transistor is formed on the first side surface of the semiconductor layer, and a gate insulating film of the second transistor is formed on the second side surface opposite to the first side surface. Process,
Forming a conductive film on the gate insulating film of the first transistor, on the gate insulating film of the second transistor, on the semiconductor layer, and on the upper insulating layer;
By patterning the conductive film, a gate electrode of the first transistor is formed on the gate insulating film of the first transistor, and the first transistor is formed on the gate insulating film of the second transistor. Forming a gate electrode of the second transistor at a position facing the gate electrode of
On the region where the drain impurity layer of the first transistor is formed on the first side surface and on the region where the drain impurity layer of the second transistor is formed on the second side surface, respectively. Forming a coating film;
By introducing impurities into the semiconductor layer under the condition that impurities pass through the coating film, using the gate electrode of the first transistor, the gate electrode of the second transistor, and the upper insulating layer as a mask, A source impurity layer functioning as a source of each of the first and second transistors is formed by diffusing impurities from the first side surface to the second side surface, and the first transistor has a first impurity layer on the first side surface. Forming a drain impurity layer and forming a drain impurity layer of the second transistor separated from the drain impurity layer of the first transistor on the second side surface;
A method for manufacturing a semiconductor device comprising:

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