JP2005101515A - Semiconductor switch - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To produce a high integration LSI by realizing a CMOS switch with a microstructure. <P>SOLUTION: A double gate MOSFET comprises: a semiconductor region 34; a gate insulation film 19 touching the semiconductor region 34; a first gate electrode 22 and second gate electrode 20 sandwitching the semiconductor region 34 through the gate insulation film 19; and conductor regions 31 and 32 touching the semiconductor region 34 on the opposite sides of the first gate electrode 22 and the second gate electrode 20. The channel region is formed of a semiconductor, the source/drain region is formed of a metal, a low level voltage is applied to the first gate electrode 22 and a high level voltage is applied to the second gate electrode 20 during on time, whereas a high level voltage is applied to the first gate electrode 22 and a low level voltage is applied to the second gate electrode 20 during off time. A semiconductor switch where the first gate electrode 22 has a work function smaller than that of the semiconductor region 34, and the second gate electrode 20 has a work function larger than that of the semiconductor region 34 is thereby provided. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor switch formed of a semiconductor device.

  A switch used in an LSI is often composed of a complementary metal oxide semiconductor (CMOS) in order to propagate / shut off both high level (high) and low level (low) signals (Patent Document 1). . A tunnel effect transistor using a Schottky barrier or a Schottky clamp nMOS transistor using a CMOS process has already been disclosed (Non-patent Document 1).

However, many switches are required for a large scale integrated circuit (LSI). For example, the switching of the write holding of the static random access memory (SRAM), the signal line selection of the dynamic random access memory (DRAM), and the like. If these switches are configured with a conventional CMOS structure, it will hinder high integration of LSI.
JP 2002-289697 A Hattori et al., “Tunneling Transistor with a New Structure Using Internal Field Emission of Schottky Barrier Junctions”, Japanese Journal of Applied Physics, Vol. 31, Part 2, October 1992, 10B, 1467-1469. Page (Reiji Hattori, Akihiro Nakae and Junji Shirafuji, “A New Type of Tunnel-Effect Transistor Employing Internal Field Emission of Schottky Barrier Junction”, Jpn. J. Appl. Phys., Vol. 31, pp. L1467-L1469, Part 2, No. 10B, vol. 15, October, 1992.)

  An object of the present invention is to realize a highly integrated LSI by realizing a CMOS switch, which is used in many LSIs, with a fine structure.

  The first feature of the semiconductor switch according to the embodiment of the present invention is (a) a semiconductor region having a predetermined work function defined by the first and second main surfaces, and (b) sandwiching the semiconductor region. And (c) a work function that is disposed on the first gate insulating film and that is smaller than a predetermined work function. (2) a second gate electrode disposed on the second gate insulating film and having a work function larger than a predetermined work function, and (e) a first main surface. The gist of the present invention is a semiconductor switch including a main current supply region and a main current receiving region arranged so as to be connected to the semiconductor region in the extending direction and sandwich the semiconductor region.

  The second feature of the semiconductor switch according to the embodiment of the present invention is that (a) a semiconductor region having a predetermined work function defined by the first and second main surfaces, and (b) sandwiching the semiconductor region. And (c) a work smaller than the work function of the semiconductor region, which is disposed on the first gate insulating film and (c) the first and second gate insulating films respectively disposed on the first and second main surfaces. A first gate electrode having a function; (d) a second gate electrode disposed on the second gate insulating film and having a work function larger than that of the semiconductor region; and (e) a second main electrode. A main current supply conductor region and a main current receiving conductor region which are arranged so as to be connected to the semiconductor region in the direction of extending the surface and sandwich the semiconductor region; (f) a main current supply conductor region on the second gate electrode side; Impurities placed on the surface of the main current receiving conductor region And a diffusing layer, and summarized in that a semiconductor switch is greater than the electron affinity of the electron affinity semiconductor region (g) an impurity diffusion layer.

  According to the semiconductor switch of the present invention, the device size of the pass gate can be reduced by using a CMOS switch in which the work function of the nMOS gate is set smaller and the work function of the pMOS gate is set larger than the work function of the channel semiconductor. It can be realized with a fine structure.

  A semiconductor region; a gate insulating film in contact with the semiconductor region; a first gate electrode and a second gate electrode formed so as to sandwich the semiconductor region with the gate insulating film interposed therebetween; a first gate electrode and a second gate electrode; In a double-gate MOSFET having a conductor region connected to a semiconductor region on both sides of a gate electrode, a channel region is formed of a semiconductor, a source / drain region is formed of metal, and a metallographic junction is formed with the semiconductor of the channel region When turned on, a low level voltage is applied to the first gate electrode and a high level voltage is applied to the second gate electrode. When off, a high level voltage is applied to the first gate electrode and a low level voltage is applied to the second gate electrode. . For example, the first gate electrode provides a semiconductor switch having a work function smaller than that of the semiconductor region, and the second gate electrode has a work function larger than that of the semiconductor region. A CMOS switch used in many LSIs is realized with a fine structure to enable production of highly integrated LSIs. Here, “metallurgical junction” means forming a metallurgical junction, and includes a Schottky contact, an ohmic contact, a pn junction, and the like.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or similar parts are denoted by the same or similar reference numerals. Further, the following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is not specified as follows. The technical idea of the present invention can be variously modified within the scope of the claims.

(Comparative example)
A simplified circuit symbol of a CMOS switch used in an LSI is described as shown in FIG. In the CMOS switch shown in FIG. 1, the input voltage V _IN is applied to the input terminal 6, and the output voltage V _OUT is obtained at the output terminal 8. When the voltage applied to the first gate terminal 2 connected to the gate of the pMOS transistor 10 is V _GP and the voltage applied to the second gate terminal 4 connected to the gate of the nMOS transistor 12 is V _GN , the CMOS switch In the ON state, a voltage is set so that V _GP = low and V _GN = high. In the OFF state, a voltage is set so that V _GP = high and V _GN = low. In the CMOS switch, the pMOS transistor becomes conductive when V _GP = low and V _IN = high, and the nMOS transistor becomes conductive when V _GN = high and V _IN = low.

In the circuit symbol shown in FIG. 1, the source and the drain seem to be shared, but in the detailed circuit symbol, it is expressed as shown in FIG. That is, in the CMOS structure, a pMOS transistor and an nMOS transistor are connected in parallel between the source and the drain. A typical structure for realizing such a CMOS switch is as shown in FIG. In FIG. 38, n ⁺ source / drain regions 24 and 26, a gate insulating film 19, and an n ⁺ polysilicon gate electrode (second gate electrode) 20 are formed in a p well 16 formed for the n-type semiconductor substrate 14. An nMOS transistor is provided. On the other hand, in the n-type semiconductor substrate 14, a pMOS transistor including p ⁺ source / drain regions 28 and 30, a gate insulating film 19, and a p ⁺ polysilicon gate electrode (first gate electrode) 22 is disposed. The isolation region 18 of the pMOS transistor and the nMOS transistor is formed by using shallow trench isolation (STI). As shown in FIG. 38, the input terminal 6 as a CMOS switch is connected to one main electrode 26 of the nMOS transistor and 28 which is one main electrode of the pMOS transistor, and the output terminal 8 is connected to the nMOS transistor. The other main electrode 24 and the other main electrode 30 of the pMOS transistor are connected to 30 to realize the circuit configuration of the CMOS switch shown in FIG. 1 or 2 as a whole.

  In the CMOS switch as the comparative example, the circuit expression shown in FIG. 1 or 2 is substantially the same in the circuit configuration in the following embodiments of the present invention, and the same expression is used.

(First embodiment)
In a semiconductor switch composed of a double gate MOSFET, a channel region is a semiconductor region 34, source / drain regions are conductor regions 31 and 32 made of metal, and gates on both sides are a first gate electrode 22 and a second gate electrode 20, respectively. . When the semiconductor switch is conductive (ON), a low level is applied to the first gate electrode 22 and a high level voltage is applied to the second gate electrode 20, and when the semiconductor switch is cut off (OFF), the first gate electrode 22 is high. A low level voltage is applied to the second gate electrode 20.

  FIG. 3 is a schematic sectional view of the semiconductor switch according to the first embodiment of the present invention. FIG. 3 corresponds to a schematic element cross-sectional composition of the semiconductor switch as viewed from above. The first gate electrode 22 and the second gate electrode 20 are formed so as to sandwich the semiconductor region 34. The first gate electrode 22 has a work function smaller than that of the semiconductor region 34, and the second gate electrode 20 has a work function larger than that of the semiconductor region 34. Then, conductor regions 31 and 32 are formed so as to be in contact with the semiconductor region 34 with the first gate electrode 22 and the second gate electrode 20 interposed therebetween.

The semiconductor region 34 is, for example, non-doped silicon (Si), the first gate electrode 22 is p ⁺ polysilicon, the second gate electrode 20 is n ⁺ polysilicon, the conductor regions 31 and 32 are titanium silicide (TiSi ₂ ), cobalt It is formed of silicide (CoSi ₂ ), nickel silicide (NiSi), or the like. A Schottky junction is formed between the conductor regions 31 and 32 and the semiconductor region 34.

FIG. 4 shows an example of semiconductor switch characteristics according to the present invention. As shown in FIG. 4, as an example of the device dimensions, in FIG. 3, the gate length L = 0.1 μm, the thickness t _OX = 1 nm of the gate insulating film 19, and the thicknesses of the conductor regions 31 and 32 D = 10 nm. The broken line is the input voltage V _IN waveform. The voltage V _GP applied to the first gate terminal connected to the first gate electrode 22 is + 0.5V, and the voltage V _GN applied to the second gate terminal connected to the second gate electrode 20 is −0. Assuming .5 V, the potential of V _IN does not propagate to the output voltage V _OUT as indicated by the dotted line in the figure. On the other hand, when the voltage V _GP applied to the first gate terminal is −0.5 V and the voltage V _GN applied to the second gate terminal is +0.5 V, as shown by the solid line in FIG. The potential of V _IN propagates to _OUT . As described above, according to the semiconductor switch according to the first embodiment of the present invention, the switch operation can be performed with a finer structure as compared with the conventional CMOS.

FIG. 5 shows a bird's-eye view of the structure of the semiconductor switch according to the first embodiment of the present invention. In the first embodiment, a plate-shaped semiconductor region 34 is formed on the buried insulating film 36, and the first gate electrode 22 and the second gate electrode 20 are formed on both sides of the semiconductor region 34 via the gate insulating film 19. Conductor regions 31 and 32 are formed so as to be in contact with the semiconductor region 34 with the first gate electrode 22 and the second gate electrode 20 interposed therebetween.

  6 to 23 show a semiconductor switch manufacturing method according to the first embodiment of the present invention.

(A) First, a plate-like semiconductor region (for example, non-doped silicon) 34 is provided on a buried insulating film (for example, SiO ₂ ) 36, and a gate insulating film (for example, SiO ₂ ) 19 is formed on the surface by an oxidation process or a deposition process. Form (FIGS. 6 to 8). Here, FIG. 6 is a schematic top view showing a gate insulating film forming step as one manufacturing step of the semiconductor switch manufacturing method according to the first embodiment of the present invention, and FIG. 7 corresponds to FIG. FIG. 8 is a schematic side view, and FIG. 8 is a schematic cross-sectional structure diagram taken along the line II in FIGS.

(B) Next, a polycrystalline semiconductor (for example, polysilicon) is deposited to form the semiconductor region 40, and a protective film (for example, a silicon nitride film (SiN)) 38 is formed on the surface thereof by a nitridation process or a deposition process. By the process and reactive ion etching (RIE) process, the polycrystalline semiconductor region 40 and the protective film 38 on the surface thereof are left so as to intersect with the plate-like semiconductor region 34, and the side surface of the polycrystalline semiconductor region 40 is protected by the nitriding process. A film 38 is formed (FIGS. 9 to 11). Here, FIG. 9 is a schematic top view showing a gate electrode patterning step as one manufacturing step of the semiconductor switch manufacturing method according to the first embodiment of the present invention, and FIG. 10 is a schematic view corresponding to FIG. FIG. 11 is a schematic sectional view taken along line II of FIGS. 9 and 10.

(C) Next, the gate insulating film 19 on the semiconductor surface other than under the polycrystalline semiconductor region 40 is removed by a chemical dry etching (CDE) process (FIGS. 12 to 14). Here, FIG. 12 is a schematic top view showing the gate insulating film removal step of the source / drain portion as one manufacturing step of the method of manufacturing the semiconductor switch according to the first embodiment of the present invention, and FIG. FIG. 14 is a schematic side view corresponding to FIG. 12, and FIG. 14 is a schematic cross-sectional structure diagram taken along the line II of FIGS.

(D) Next, a metal is deposited on the semiconductor surface from which the gate insulating film 19 has been removed, and conductor regions 31 and 32 (for example, TiSi ₂ , CoSi ₂ , NiSi) are formed by a thermal process (FIGS. 15 to 17). Here, FIG. 15 is a schematic top view showing a silicide formation process as one manufacturing process of the semiconductor switch manufacturing method according to the first embodiment of the present invention, and FIG. 16 is a schematic view corresponding to FIG. FIG. 17 is a side view, and FIG. 17 is a schematic sectional view taken along the line II of FIG. 15 and FIG.

(E) Next, a p ⁺ polysilicon gate electrode 22 and an n ⁺ polysilicon gate electrode 20 are formed in the polycrystalline semiconductor region 40 by lithography and ion implantation (FIGS. 18 to 20). Here, FIG. 18 is a schematic top view showing a gate impurity introduction process as one manufacturing process of the semiconductor switch manufacturing method according to the first embodiment of the present invention, and FIG. 19 is a schematic view corresponding to FIG. FIG. 20 is a schematic sectional view taken along the line II of FIG. 18 and FIG.

(F) Next, the protective film 38 and the polycrystalline semiconductor region 40 on the plate-like semiconductor region 34 are removed by a chemical mechanical polishing (CMP) process (FIGS. 21 to 23). Here, FIG. 21 is a schematic top view showing a gate electrode separation process as one manufacturing process of the semiconductor switch manufacturing method according to the first embodiment of the present invention, and FIG. 22 is a schematic view corresponding to FIG. FIG. 23 is a schematic sectional view taken along the line II of FIG. 21 and FIG.

  The semiconductor switch structure of the first embodiment of the present invention shown in FIG. 3 or FIG. 5 can be manufactured by the manufacturing steps shown in FIGS.

(Second Embodiment)
FIG. 24 is a schematic sectional view of a semiconductor switch according to the second embodiment of the present invention. FIG. 24 is the same as FIG. 3 in that it corresponds to a schematic element cross-sectional composition of a semiconductor switch as viewed from above. The conductor region to which V _IN and V _OUT are connected may be formed only on the surface of the semiconductor layer.

  In the example shown in FIG. 24, an example is shown in which conductor regions 42, 44, 46, 48 are formed only in the surface region of the semiconductor region 50. Compared with the case of FIG. 3 in which the conductor regions 31 and 32 are formed over the entire thickness D direction of the semiconductor region 50, the parasitic resistance of the conductor region is increased. However, the conductor regions 42, There is an advantage in that 44, 46 and 48 can be formed.

(Third embodiment)
FIG. 25 is a schematic sectional view of a semiconductor switch according to the third embodiment of the present invention. FIG. 25 is the same as FIG. 3 in that it corresponds to a schematic element cross-sectional composition of a semiconductor switch as viewed from above. The first conductor regions 421 and 461 formed on the semiconductor surfaces on both sides of the first gate electrode 22 are substances having a work function larger than that of the semiconductor region 50. The second conductor regions 442 and 482 formed on the semiconductor surfaces on both sides of the second gate electrode 20 are materials having a work function smaller than that of the semiconductor region 50. The first conductor regions 421 and 461 are made of, for example, platinum silicide (PtSi), and the second conductor regions 442 and 482 are made of, for example, erbium silicide (ErSi ₂ ). Although the number of manufacturing steps is increased as compared with the second embodiment, there is an advantage that the contact resistance of the Schottky junction is reduced.

(Fourth embodiment)
FIG. 26 and FIG. 27 show a schematic cross-sectional structure diagram and a bird's-eye view of a semiconductor switch according to the fourth embodiment of the present invention. P ⁺ diffusion layers 52 and 56 are formed on the surface of the semiconductor region 50 on both sides of the p + polysilicon gate electrode which is the first gate electrode 22, and on both sides of the n ⁺ polysilicon gate electrode which is the second gate electrode 20. N ⁺ diffusion layers 54 and 58 are formed on the surface of the semiconductor region 50. Compared to the case where a Schottky junction is used, the short channel effect resistance deteriorates, but there is an advantage that the contact resistance of the Schottky junction can be reduced.

(Fifth embodiment)
FIG. 28 is a schematic sectional view of a semiconductor switch according to the fifth embodiment of the present invention. On the surface of the semiconductor region 50 on both sides of the p ⁺ polysilicon gate electrode which is the first gate electrode 22, the p ⁺ diffusion layer 52, 46 is located at a position shorter than L _D from the conductor regions 42 and 46 and the first gate electrode 22. 56 is formed on the surface of the semiconductor region 50 on both sides of the n ⁺ polysilicon gate electrode which is the second gate electrode 20, and n at a position shorter than L _D from the conductor regions 44 and 48 and the second gate electrode 20. ⁺ Diffusion layers 54 and 58 are formed. L _D is the distance of the depletion layer formed in the semiconductor region 50 by the diffusion potential between the p ⁺ diffusion layers 52 and 56 and the n ⁺ diffusion layers 54 and 58 and the semiconductor region 50. Although the manufacturing process is increased as compared with other embodiments, if the depletion layer wraps the conductor regions 42, 46, 44, 48, there is an advantage of suppressing the contact resistance and leakage current of the Schottky junction. Further, since the p ⁺ diffusion layers 52 and 56 and the n ⁺ diffusion layers 54 and 58 are formed away from the gate electrodes 22 and 20, there is an advantage that the short channel effect resistance is enhanced.

(Sixth embodiment)
FIG. 29 shows a schematic sectional view of a semiconductor switch according to the sixth embodiment of the present invention. On the surface of the semiconductor region 50 on both sides of the p ⁺ polysilicon gate electrode which is the first gate electrode 22, p is located at a position shorter than L _D from the first conductor regions 421 and 461 and the first gate electrode 22. ⁺ Diffusion layers 52 and 56 are formed, and the second conductor regions 442 and 482 and the second gate electrode 20 are formed on the surface of the semiconductor region 50 on both sides of the n ⁺ polysilicon gate electrode which is the second gate electrode 20. N ⁺ diffusion layers 442 and 482 are formed at a position shorter than L _D from ND. L _D is the distance of the depletion layer formed in the semiconductor region 50 by the diffusion potential between the p ⁺ diffusion layers 52 and 56 and the n ⁺ diffusion layers 54 and 58 and the semiconductor region 50. The first conductor regions 421 and 461 are materials having a work function larger than that of the semiconductor region 50, and the second conductor regions 442 and 482 are materials having a work function smaller than that of the semiconductor region 50. The first conductor regions 421 and 461 are, for example, platinum silicide (PtSi), and the second conductor regions 442 and 482 are, for example, erbium silicide (ErSi ₂ ). Although the manufacturing process is increased as compared with the above-described embodiment, there is an advantage that the contact resistance of the Schottky junction is further reduced.

In the sixth embodiment of the present invention, the material of the first gate electrode 22 and the second gate electrode 20 may not be polysilicon. A single crystal semiconductor may be used, and the same effect can be obtained when the first gate electrode 22 is formed using platinum silicide (PtSi) and the second gate electrode 20 is formed using erbium silicide (ErSi ₂ ). It is done.

(Seventh embodiment)
FIG. 30 shows a schematic sectional view of a semiconductor switch according to the seventh embodiment of the present invention. As shown in FIG. 30, the semiconductor switch according to the seventh embodiment of the present invention sandwiches the semiconductor region 34 between the semiconductor region 34 defined by the first and second main surfaces and having a predetermined work function. As described above, the first and second gate insulating films 19 disposed on the first and second main surfaces, respectively, and the work smaller than the work function of the semiconductor region 34 disposed on the first gate insulating film 19. A first gate electrode 22 having a function, a second gate electrode 20 disposed on the second gate insulating film 19 and having a work function larger than that of the semiconductor region 34, and a first main surface. A main current supply conductor region 32 and a main current receiving conductor region 31 arranged so as to be connected to the semiconductor region 34 in the extending direction and sandwich the semiconductor region 34, and a main current supply conductor region 32 on the first gate electrode 22 side. And main current acceptance And a impurity diffusion layers 140, 142 on the surface of the body region 31 are arranged respectively, the electron affinity of the impurity diffusion layers 140 and 142 is smaller than the electron affinity of the semiconductor region 34.

For example, when the first gate electrode 22 is formed of p ⁺ polysilicon and the impurity diffusion layer 142 is formed as a p ⁺ region, the electron affinity of the impurity diffusion layers 140 and 142 is greater than the electron affinity of the semiconductor region 34. Is also small.
Such an impurity diffusion layer can of course be formed symmetrically on the second gate electrode 20 side as well as on the first gate electrode side.

The conductor regions 31 and 32 are formed of erbium silicide (ErSi ₂ ), titanium silicide (TiSi ₂ ), cobalt silicide (CoSi ₂ ), nickel silicide (NiSi), or the like. A Schottky junction is formed between the conductor regions 31 and 32 and the semiconductor region 34.

By providing the impurity diffusion layers 140 and 142 made of p ⁺ layer on the surface of erbium silicide (ErSi _2), it is possible to increase the tunneling probability of the holes between the erbium silicide (ErSi ₂₎ and the semiconductor region 34 Therefore, a high driving force can be obtained in the pMOSFET operation realized on the first gate electrode 22 side.

(Production method)
The bird's-eye view of the structure of the semiconductor switch according to the seventh embodiment of the present invention is the same as FIG. In the seventh embodiment, a plate-like semiconductor region 34 is formed on the buried insulating film 36, and the first gate electrode 22 and the second gate electrode 20 are formed on both sides of the semiconductor region 34 via the gate insulating film 19. Conductor regions 31 and 32 are formed so as to be in contact with the semiconductor region 34 with the first gate electrode 22 and the second gate electrode 20 interposed therebetween.

  The manufacturing method of the semiconductor switch according to the seventh embodiment is the same as the manufacturing process shown in FIGS. 6 to 23, and further the manufacturing process shown in FIGS. 31 to 33 is added.

(A) First, a plate-like semiconductor region (for example, non-doped silicon) 34 is provided on a buried insulating film (for example, SiO ₂ ) 36, and a gate insulating film (for example, SiO ₂ ) 19 is formed on the surface by an oxidation process or a deposition process. Form (FIGS. 6 to 8). Here, FIG. 6 is a schematic top view showing a gate insulating film forming step as one manufacturing step of the semiconductor switch manufacturing method according to the seventh embodiment of the present invention, and FIG. 7 corresponds to FIG. FIG. 8 is a schematic side view, and corresponds to a schematic cross-sectional structure diagram taken along the line II in FIGS.

(B) Next, a polycrystalline semiconductor (for example, polysilicon) is deposited to form the semiconductor region 40, and a protective film (for example, a silicon nitride film (SiN)) 38 is formed on the surface thereof by a nitridation process or a deposition process. By the process and reactive ion etching (RIE) process, the polycrystalline semiconductor region 40 and the protective film 38 on the surface thereof are left so as to intersect with the plate-like semiconductor region 34, and the side surface of the polycrystalline semiconductor region 40 is protected by the nitriding process. A film 38 is formed (FIGS. 9 to 11). Here, FIG. 9 is a schematic top view showing a gate electrode patterning step as one manufacturing step of the semiconductor switch manufacturing method according to the seventh embodiment of the present invention, and FIG. 10 is a schematic view corresponding to FIG. FIG. 11 corresponds to a schematic cross-sectional structure diagram taken along the line II of FIG. 9 and FIG.

(C) Next, the gate insulating film 19 on the semiconductor surface other than under the polycrystalline semiconductor region 40 is removed by a chemical dry etching (CDE) process (FIGS. 12 to 14). Here, FIG. 12 is a schematic top view showing the gate insulating film removal step of the source / drain part as one manufacturing step of the method of manufacturing the semiconductor switch according to the seventh embodiment of the present invention, and FIG. FIG. 14 is a schematic side view corresponding to FIG. 12, and FIG. 14 corresponds to a schematic cross-sectional structure diagram taken along the line II in FIGS. 12 and 13.

(D) Next, a metal is deposited on the semiconductor surface from which the gate insulating film 19 has been removed, and conductor regions 31 and 32 (for example, ErSi ₂ , TiSi ₂ , CoSi ₂ , NiSi) are formed by a thermal process (FIGS. 15 to 15). 17). Here, FIG. 15 is a schematic top view showing a silicide formation step as one manufacturing step of the semiconductor switch manufacturing method according to the seventh embodiment of the present invention, and FIG. 16 is a schematic view corresponding to FIG. The side view and FIG. 17 correspond to the schematic cross-sectional structure diagram taken along the line II of FIGS.

(E) Next, a p ⁺ polysilicon gate electrode 22 and an n ⁺ polysilicon gate electrode 20 are formed in the polycrystalline semiconductor region 40 by lithography and ion implantation (FIGS. 18 to 20). Here, FIG. 18 is a schematic top view showing a gate impurity introduction step as one manufacturing step of the semiconductor switch manufacturing method according to the seventh embodiment of the present invention, and FIG. 19 is a schematic view corresponding to FIG. 20 corresponds to a schematic cross-sectional structure diagram taken along the line I-I in FIGS. 18 and 19.

(F) Next, the protective film 38 and the polycrystalline semiconductor region 40 on the plate-like semiconductor region 34 are removed by a chemical mechanical polishing (CMP) process (FIGS. 21 to 23). Here, FIG. 21 is a schematic top view showing a gate electrode isolation step as one manufacturing process of the semiconductor switch manufacturing method according to the seventh embodiment of the present invention, and FIG. 22 is a schematic view corresponding to FIG. FIG. 23 is a schematic sectional view taken along the line II of FIG. 21 and FIG.

(G) Next, boron ions 180, for example, are introduced by oblique ion implantation, and the conductor regions 31, 32 (for example, ErSi ₂ , TiSi) on the first gate electrode side formed by the p ⁺ polysilicon gate electrode 22 ₂ , CoSi ₂ , NiSi), impurity diffusion layers 140 and 142 (FIG. 30) are formed (FIGS. 31 to 33).

  The structure of the semiconductor switch according to the seventh embodiment of the present invention shown in FIG. 30 can be manufactured by the manufacturing steps shown in FIGS. 6 to 23 and FIGS.

(Modification of the seventh embodiment)
Similarly, as shown in FIG. 30, the semiconductor switch according to the modification of the seventh embodiment of the present invention includes a semiconductor region 34 having a predetermined work function, which is defined by the first and second main surfaces. The first and second gate insulating films 19 disposed on the first and second main surfaces so as to sandwich the semiconductor region 34, and the first gate insulating film 19 are disposed on the first and second main surfaces, respectively. A second gate electrode 20 having a work function larger than the work function; a first gate electrode 22 disposed on the first gate insulating film 19 and having a work function smaller than the work function of the semiconductor region 34; A main current supply conductor region 32 and a main current receiving conductor region 31 disposed so as to be connected to the semiconductor region 34 and sandwiching the semiconductor region 34 in a direction in which the second main surface extends, and on the second gate electrode 20 side The main current supply conductor area And a 32 and the impurity diffusion layers 144 and 146 which are respectively disposed on the surface of the main current receiving conductor region 31, the electron affinity of the impurity diffusion layers 144 and 146 is greater than the electron affinity of the semiconductor region 34.

For example, when the second gate electrode 20 is formed of n ⁺ polysilicon and the impurity diffusion layers 144 and 146 are formed as n ⁺ regions, the electron affinity of the impurity diffusion layers 144 and 146 is the electron affinity of the semiconductor region 34. Greater than affinity.

  Such an impurity diffusion layer can of course be formed symmetrically on the first gate electrode 22 side as well as on the second gate electrode side.

The conductor regions 31 and 32 are formed of erbium silicide (ErSi ₂ ), titanium silicide (TiSi ₂ ), cobalt silicide (CoSi ₂ ), nickel silicide (NiSi), or the like. A Schottky junction is formed between the conductor regions 31 and 32 and the semiconductor region 34.

By using such a structure, a semiconductor switch can be realized with a fine structure. In particular, when erbium silicide (ErSi ₂ ) is used as the conductor regions 31 and 32, since the barrier against electrons is low, a high driving force can be obtained in the nMOSFET operation realized on the second gate electrode 20 side. Further, similarly to the seventh embodiment, during the by providing the impurity diffusion layers 140 and 142 made of p ⁺ layer on the surface of erbium silicide (ErSi _2), and erbium silicide (ErSi ₂₎ and the semiconductor region 34 Therefore, a high driving force can be obtained even in the pMOSFET operation realized on the first gate electrode 22 side.

(Eighth embodiment)
FIG. 34 shows a schematic sectional view of a semiconductor switch according to the eighth embodiment of the present invention. As shown in FIG. 34, the semiconductor switch according to the seventh embodiment of the present invention includes a semiconductor region 34 having a predetermined work function defined by the first and second main surfaces, and a semiconductor region 34. The first and second gate insulating films 19 disposed on the first and second main surfaces so as to be sandwiched between the first gate insulating film 19 and the work function of the semiconductor region 34 are smaller. A first gate electrode 22 having a work function, a second gate electrode 20 disposed on the second gate insulating film 19 and having a work function larger than that of the semiconductor region 34, and a first main surface The main current supply conductor region 32 and the main current receiving conductor region 31 are arranged so as to be connected to the semiconductor region 34 and sandwich the semiconductor region 34 in the extending direction, and the side walls of the first and second gate electrodes 22 and 20. Insulating film between gates 1 Through 0 and an arranged charge storage layer 150.

For example, the semiconductor region 34 is non-doped silicon (Si), the first gate electrode 22 is p ⁺ polysilicon, the second gate electrode 20 is n ⁺ polysilicon, and the conductor regions 31 and 32 are erbium silicide (ErSi ₂ ). , titanium silicide (TiSi _2), cobalt silicide (CoSi _2), formed by a two-Tsu Kell silicide (NiSi), and the like. A Schottky junction is formed between the conductor regions 31 and 32 and the semiconductor region 34.

  By using such a structure, a semiconductor switch can be realized with a fine structure. As shown in FIG. 34, in the charge storage layer 150 on the side wall of the first gate electrode 22, the charge storage layer 150 is adjacent to the charge storage layer 150 through the gate insulating film 19 by setting an excess state of electrons or a shortage of holes. Hole inversion layers 160 and 162 are formed on the surface of the semiconductor region 34 by inducing holes. The hole inversion layers 160 and 162 can increase the hole tunneling probability at the Schottky junction between the conductor regions 31 and 32. Accordingly, a high driving force can be obtained in the operation of the pMOSFET realized on the first gate electrode 22 side.

  Further, in the charge storage layer 150 on the side wall of the second gate electrode 20, the surface of the semiconductor region 34 adjacent to the charge storage layer 150 through the gate insulating film 19 is obtained by setting the electron shortage state or the hole excess state. Then, electron inversion layers 164 and 166 are formed by inducing electrons. Since the electron inversion layers 164 and 166 can increase the electron tunneling probability at the Schottky junction between the conductor regions 31 and 32, the electron inversion layers 164 and 166 are high in the nMOSFET operation realized on the second gate electrode 20 side. Driving force can be obtained. The amount of charge in the charge storage layer 150 is adjusted by the tunnel current from the semiconductor region 34 or the first and second gate electrodes 22, 20, or hot carrier injection from the semiconductor region 34.

In the operation as a semiconductor switch, a low level voltage is applied to the first gate electrode 22 and a high level voltage is applied to the second gate electrode 20 when the switch is on. When off, a high level voltage is applied to the first gate electrode 22 and a low level voltage is applied to the second gate electrode 20. The potential of the charge storage layer 150 on the side wall of the first gate electrode (p ⁺ gate) 22 is set to a low level, and the potential of the charge storage layer 150 on the side wall of the second gate electrode (n ⁺ gate) 20 is set to a high level. .

(Ninth embodiment)
The present invention can be applied not only to a double gate structure formed of the plate-like semiconductor region 50 but also to a planar silicon on insulator (SOI) structure. FIG. 35 is a schematic sectional view of a semiconductor switch according to the ninth embodiment of the present invention. A buried oxide film region (BOX) 114 is buried in an n well region 112 formed in the p-type semiconductor substrate 110, and an n ⁺ contact region 118 is formed by an n ⁺ diffusion layer. A second gate terminal 132 is connected to the n ⁺ contact region 118, and a second gate voltage V _GN is applied. On the other hand, on the BOX 114, in the example of FIG. 35, three Schottky transistors are formed that are separated from each other by insulating isolation regions 116 such as shallow trench isolation (STI). First gate electrodes 220, 221, and 222 made of p ⁺ polysilicon gate electrodes are formed through a gate insulating film 149 with respect to a channel region made of the semiconductor regions 140, 142, and 144. Further, the first gate terminals 134, 136, and 138 are connected to the first gate electrodes 220, 221, and 222, respectively, and the first gate voltage V _GP is applied thereto. The first gate terminals 134, 136, and 138 may be connected so as to be electrically common. Each source / drain region of each Schottky transistor is a conductor region 120, 122, 124, 126, 128, 130, and a Schottky junction is formed between the channel region composed of the semiconductor regions 140, 142, 144. doing. These source / drain regions formed of the conductor regions 120, 122, 124, 126, 128, and 130 can be formed of, for example, TiSi ₂ , CoSi ₂ , NiSi, PtSi, ErSi ₂ , or the like. According to the semiconductor switch of the ninth embodiment of the present invention, since it has a planar SOI structure, it can be easily formed simultaneously with an LSI having a planar structure, and can be easily applied to DRAM, SRAM, and the like. There is an advantage.

In FIG. 35, a structure in which the conductivity type is reversed can be formed. That is, a p-well region may be formed on an n-type semiconductor substrate, and a Schottky transistor having an n ⁺ polysilicon gate electrode having an SOI structure may be formed. In that case, 118 is formed as a p ⁺ contact region, and the first gate terminal 132 is connected to the second gate electrodes 220, 221, and 222 made of n ⁺ polysilicon gate electrodes. The second gate terminals 134, 136, and 138 are connected.

(Tenth embodiment)
The semiconductor switches according to the first to ninth embodiments of the present invention can be applied to various LSIs. Among them, an application example to a DRAM is shown as an eighth embodiment in FIG. Shown in In FIG. 36, SWs indicated by 68 and 70 indicate the semiconductor switches according to the first to ninth embodiments of the present invention. In FIG. 36, memory cells 60 at positions where word lines WL0 to WLn and bit lines BL0 to BLn intersect are arranged. A row decoder 62 is connected to the word lines WL0 to WLn, and a column decoder 64 is connected to the bit lines BL0 to BLn via a sense amplifier (SA) 66 and semiconductor switches (SW) 68 and 70. As shown in FIG. 36, the semiconductor switches (SW) 68 and 70 are disposed between the bit lines BL0 to BLn and the data lines 76 and 78 for the purpose of selecting the bit lines BL0 to BLn. The data lines 76 and 78 are connected to the data input / output line 74 via the I / O buffer 72. Further, a row address data line 82 is connected to the row decoder 62, and a column address data line 80 is connected to the column decoder 64.

  In application of the semiconductor switch according to the tenth embodiment of the present invention to a DRAM, it is necessary to consider process compatibility with other LSIs formed at the same time. When realized, a semiconductor switch with a fine structure can be realized in a DRAM while maintaining an efficient switching operation.

(Eleventh embodiment)
The semiconductor switches according to the first to ninth embodiments of the present invention can be applied to various LSIs. Among them, an application example to an SRAM is shown as an eleventh embodiment in FIG. Shown in In FIG. 37, the CMOS semiconductor switch indicated by 90 represents the semiconductor switch according to the first to ninth embodiments of the present invention. 37, SRAM memory cells are arranged at positions where word lines WL0 to WLn and bit lines (BL0, BL0 bar),..., (BLm, BLm bar) intersect. As shown in FIG. 37, each SRAM memory cell includes two nMOS transistors 96 and 100, two pMOS transistors 94 and 98, and two semiconductor switches 90. Two CMOS inverters arranged between the power supply voltage V _DD and the ground potential constitute a latch-up circuit connected by feeding back the output to the input, and further between the bit lines BL0 and BL bar. A semiconductor switch 90 is arranged to realize switching of write holding. Compared to the case of application to the DRAM shown in FIG. 37 in which semiconductor switches are arranged corresponding to the bit lines, two semiconductor switches 90 are arranged corresponding to the memory cells in the case of application to the SRAM shown in FIG. The number of semiconductor switches used is much greater.

In the application of the semiconductor switch in the eleventh embodiment of the present invention to the SRAM, it is necessary to consider process compatibility with other LSIs formed at the same time. In the case of realization, it is possible to realize a semiconductor switch with a fine structure in an SRAM while maintaining an efficient switching operation.

  As described above, the present invention has been described according to the embodiment. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, embodiments, and operational techniques will be apparent to those skilled in the art. Therefore, the technical scope of the present invention is determined only by the invention specifying matters according to the scope of claims reasonable from the above description. Furthermore, it is needless to say that the semiconductor devices disclosed by the embodiments of the present invention can be operated by being combined with each other. As described above, the present invention can be implemented with various modifications without departing from the spirit of the present invention.

The circuit diagram of a CMOS switch. The circuit diagram of a CMOSFET switch. FIG. 3 is a schematic cross-sectional structure diagram of a semiconductor switch including a Schottky barrier transistor as the semiconductor switch according to the first embodiment of the present invention. FIG. 4 is a diagram illustrating a characteristic example of a semiconductor switch including a Schottky barrier transistor as the semiconductor switch according to the first embodiment of the present invention. FIG. 2 is a schematic bird's-eye view of a semiconductor switch including a Schottky barrier transistor as the semiconductor switch according to the first embodiment of the present invention. FIG. 6 is a schematic top view showing a gate insulating film forming step as one manufacturing step of the method for manufacturing the semiconductor switch according to the first embodiment of the present invention. FIG. 8 is a schematic side view corresponding to FIG. 7. FIG. 8 is a schematic sectional view taken along the line II in FIGS. 6 and 7. FIG. 5 is a schematic top view showing a gate electrode patterning step as one manufacturing step of the method for manufacturing the semiconductor switch according to the first embodiment of the present invention. FIG. 10 is a schematic side view corresponding to FIG. 9. FIG. 11 is a schematic sectional view taken along the line II of FIG. 9 and FIG. 10. FIG. 5 is a schematic top view showing a gate insulating film removal step of a source / drain part as one manufacturing step of the method for manufacturing a semiconductor switch according to the first embodiment of the present invention. FIG. 13 is a schematic side view corresponding to FIG. 12. FIG. 14 is a schematic sectional view taken along the line II of FIG. 12 and FIG. 13. FIG. 3 is a schematic top view showing a silicide formation step as one manufacturing step of the method for manufacturing the semiconductor switch according to the first embodiment of the present invention. FIG. 16 is a schematic side view corresponding to FIG. 15. FIG. 17 is a schematic sectional view taken along the line II of FIG. 15 and FIG. 16. FIG. 5 is a schematic top view showing a gate impurity introduction step as one manufacturing step of the method for manufacturing a semiconductor switch according to the first embodiment of the present invention. FIG. 19 is a schematic side view corresponding to FIG. 18. FIG. 20 is a schematic sectional view taken along the line II of FIG. 18 and FIG. 19. FIG. 3 is a schematic top view showing a gate electrode separation step as one manufacturing step of the method for manufacturing a semiconductor switch according to the first embodiment of the present invention. FIG. 22 is a schematic side view corresponding to FIG. 21. FIG. 23 is a schematic sectional view taken along the line II of FIG. 21 and FIG. 22. FIG. 6 is a schematic cross-sectional structure diagram of a Schottky barrier transistor switch as a semiconductor switch according to a second embodiment of the present invention. The typical cross-section figure of a Schottky barrier transistor switch as a semiconductor switch concerning a 3rd embodiment of the present invention. The typical cross-section figure of a diffusion layer transistor switch as a semiconductor switch concerning a 4th embodiment of the present invention. Bird's eye view of diffusion layer transistor switch of FIG. The typical cross-section figure of a hybrid transistor switch as a semiconductor switch concerning a 5th embodiment of the present invention. The typical cross-section figure of a hybrid transistor switch as a semiconductor switch concerning a 6th embodiment of the present invention. FIG. 10 is a schematic cross-sectional structure diagram of a semiconductor switch according to a seventh embodiment of the invention. The typical top view showing the diffusion layer introduction process in one manufacturing process of the manufacturing method of the semiconductor switch concerning a 7th embodiment of the present invention. FIG. 32 is a schematic side view corresponding to FIG. 31. FIG. 33 is a schematic cross-sectional structure diagram taken along the line II of FIG. 31 and FIG. 32. FIG. 10 is a schematic sectional view of a semiconductor switch according to an eighth embodiment of the present invention. 15 shows an application example of the semiconductor switch according to the seventh embodiment of the present invention to an SOI structure. 15 shows an application example of a semiconductor switch according to an eighth embodiment of the present invention to a DRAM. 15 shows an application example of a semiconductor switch according to a ninth embodiment of the present invention to an SRAM. The typical cross-section figure of CMOSFET of a comparative example.

Explanation of symbols

2,134,136,138 ... first gate terminal 4,132 ... second gate terminal 6 ... input terminal 8 ... output terminals 10,94,98,102 ... pMOS transistors 12,96,100,104 ... nMOS transistors 14 ... n-type semiconductor substrate or n-well region 16 ... p-well region 18, 116 ... insulation isolation regions 19, 149 ... gate insulating film 20 ... second gate electrode (n ⁺ polysilicon gate electrode)
22: First gate electrode (p ⁺ polysilicon gate electrode)
24, 26 ... n ⁺ source / drain regions 28, 30 ... p ⁺ source / drain regions 31, 32, 42, 44, 46, 48, 120, 122, 124, 126, 128, 130 ... conductor regions 34, 40, 50, 140, 142, 144 ... semiconductor region 36 ... buried insulating film 38 ... protective film 52, 56 ... p ⁺ diffusion layer 54, 58 ... n ⁺ diffusion layer 60 ... memory cell 62 ... row decoder 64 ... column decoder 66 ... sense Amplifier (SA)
68, 70, 90 ... semiconductor switch 72 ... I / O buffer 74 ... data input / output lines 76, 78 ... data line 80 ... column address data line 82 ... row address data line 110 ... p-type semiconductor substrate 112 ... n well region 114 ... Built-in oxide film region (BOX)
118 ... n + contact regions 140, 142, 144, 146 ... impurity diffusion layers 150, 152, 154, 156 ... charge storage layers 160, 162 ... hole inversion layers 164, 166 ... electron inversion layers 170 ... inter-gate insulating films 180 ... Boron ion (B)
220, 221, 222 ... first gate electrode 421, 461 ... first conductor region 442, 482 ... second conductor region V _IN ... input voltage V _OUT T ... output voltage V _GP ... applied to the first gate terminal Voltage V _GN ... voltage applied to the second gate terminal

Claims (8)

A semiconductor region having a predetermined work function defined by the first and second main surfaces;
First and second gate insulating films respectively disposed on the first and second main surfaces so as to sandwich the semiconductor region;
A first gate electrode disposed on the first gate insulating film and having a work function smaller than the work function;
A second gate electrode disposed on the second gate insulating film and having a work function larger than the work function;
A semiconductor switch comprising: a main current supply region and a main current receiving region, which are arranged so as to be connected to the semiconductor region and sandwich the semiconductor region in a direction in which the first main surface extends.   2. The semiconductor switch according to claim 1, wherein each of the main current supply region and the main current receiving region is a conductor region metallurgically bonded to the semiconductor region.   The semiconductor switch according to claim 1, wherein the conductor region is disposed on a surface of the semiconductor region. A hole conduction type diffusion layer disposed on the surface of the semiconductor region on both sides of the first gate electrode;
The semiconductor switch according to claim 3, further comprising: an electron conduction type diffusion layer disposed on a surface of the semiconductor region on both sides of the second gate electrode.   The work function of the first conductor region disposed on the surface of the semiconductor region on both sides of the first gate electrode is larger than that of the semiconductor region, and is disposed on the surface of the semiconductor region on both sides of the second gate electrode. 5. The semiconductor switch according to claim 3, wherein a work function of the second conductor region is smaller than that of the semiconductor region.   And further comprising impurity diffusion layers respectively disposed on the surfaces of the main current supply region and the main current receiving region on the first gate electrode side, and the electron affinity of the impurity diffusion layer is smaller than the electron affinity of the semiconductor region. The semiconductor switch according to claim 2, wherein: A semiconductor region having a predetermined work function defined by the first and second main surfaces;
First and second gate insulating films respectively disposed on the first and second main surfaces so as to sandwich the semiconductor region;
A first gate electrode disposed on the first gate insulating film and having a work function smaller than the work function;
A second gate electrode disposed on the second gate insulating film and having a work function larger than the work function;
A main current supply conductor region and a main current receiving conductor region disposed so as to be connected to the semiconductor region and sandwich the semiconductor region in a direction extending the second main surface;
An impurity diffusion layer disposed on the surfaces of the main current supply conductor region and the main current receiving conductor region on the second gate electrode side, and the electron affinity of the impurity diffusion layer is higher than the electron affinity of the semiconductor region. A semiconductor switch that is large.   8. The semiconductor switch according to claim 1, further comprising a charge storage layer disposed on sidewalls of the first and second gate electrodes. 9.

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