EP0815552B1 - Procede d'adressage d'un ecran plat utilisant une precharge des pixels, circuit de commande permettant la mise en oeuvre du procede et son application aux ecrans de grandes dimensions - Google Patents

Procede d'adressage d'un ecran plat utilisant une precharge des pixels, circuit de commande permettant la mise en oeuvre du procede et son application aux ecrans de grandes dimensions Download PDF

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Publication number
EP0815552B1
EP0815552B1 EP97900254A EP97900254A EP0815552B1 EP 0815552 B1 EP0815552 B1 EP 0815552B1 EP 97900254 A EP97900254 A EP 97900254A EP 97900254 A EP97900254 A EP 97900254A EP 0815552 B1 EP0815552 B1 EP 0815552B1
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EP
European Patent Office
Prior art keywords
voltage
ven
lines
transistors
exp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP97900254A
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German (de)
English (en)
French (fr)
Other versions
EP0815552A1 (fr
Inventor
François Maurice
Eric Sanson
Bruno Mourey
Hugues Lebrun
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales Avionics LCD SA
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Thales Avionics LCD SA
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Publication date
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Publication of EP0815552A1 publication Critical patent/EP0815552A1/fr
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Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0204—Compensation of DC component across the pixels in flat panels

Definitions

  • the present invention relates to a method for addressing a flat screen, more particularly a liquid crystal screen using a pixel preload.
  • the present invention also relates to a circuit for control of the columns of such a screen allowing the implementation of the process as well as applying the process to large screens dimensions.
  • Liquid crystal displays with direct vision or projection usually consist of rows (selection rows) and columns (data lines) at the intersections of which the pixel electrodes connected through transistors to these lines.
  • the grids of these transistors form the selection lines and are controlled by peripheral control circuits, generally called “drivers” which scan the lines and make passing the transistors of each line allowing, by the lines of data connected to the other peripheral control circuits, charge the pixel electrodes and modify the optical properties of the liquid crystal between these electrodes and the counter electrode (or reference electrode) thus allowing the formation of images on the screen.
  • Figure 1 shows the equivalent electrical diagram of a flat screen pixel addressed by line control circuits and columns.
  • the electrode and counter electrode surrounding the liquid crystal form a capacity 1 whose charge (most often constituted by video data) is transmitted by column 2 through the transistor 3 controlled by the selection line 4.
  • Figure 2 as to it represents the chronograms of operation of this pixel, Vs being the signal sent by the selection line of a row of pixels, Vc the video signal sampled on the selected row of pixels and Vp the effective charge of one of these pixels.
  • Vs being the signal sent by the selection line of a row of pixels
  • Vc the video signal sampled on the selected row of pixels
  • Vp the effective charge of one of these pixels.
  • the pixel voltage Vp across the crystal liquid should be equal to the column voltage Vc, i.e. +/- V.
  • each transistor 3 when it is in the on state, has a resistance Ron which is not zero, so the charge of the pixel exhibits an exponential characteristic (as shown in FIG. 2) a time constant which is not zero since it is equal to the product Ron x C, C being the value of the capacity 1 of the pixel.
  • the residual convergence error is equal to Ven + in positive frame (negative value) or Ven- in negative frame (positive value), different from the +/- V values of the charging voltage Vc.
  • FIG. 3 Another known solution is shown in Figure 3.
  • a screen 5 made up of pixels 6 is addressed by a circuit control line 7 and a column control circuit 8 formed by samplers controlled by a shift register.
  • the charge of a sampler is none other than the distributed capacity of the column ordered 9.
  • This column must be loaded for a very long time short, with the above-mentioned convergence problems compounded by the the charging time is only a fraction of the time address a line 9. Indeed, during this time line, it is necessary successively sample the video on all columns of the screen. For this reason, the creation of screens with integrated drivers has need to date the use of high semiconductor mobility, such as mono or polycrystalline silicon.
  • the present invention provides a new process addressing to overcome the drawbacks mentioned above.
  • the subject of the present invention is a method for addressing a flat screen composed of rows and columns to intersections of which pixels are located, characterized in that, at the start of each sampling of the video signal to be displayed on the screen, a voltage (Vr) greater than the useful voltage range (V) is applied on the selected pixel for a time tr, then the useful voltage is sampled for a time ts.
  • the present invention also relates to a circuit for control of the columns of a flat screen of the type comprising samplers controlled by the outputs of a shift register, characterized in that each sampler consists of three MIS type transistors connected in parallel so that their first electrode is connected to the video signal and their second electrode at the controlled column, which gate of the first transistor being connected to one of the outputs of the shift register and the gates of the second and third transistors being connected to two clocks chosen so that both transistors are activated, one for perform the preload of the even lines, the other of the odd lines.
  • the voltage of the clocks applied to the second and third transistors is chosen from so that when a transistor is not used for preloading, it receives on its grid a negative voltage allowing later compensate for capacitive couplings when this voltage returns to zero.
  • the three transistors are identical and are transistors produced in a thin layer or TFT.
  • This solution allows compensate for large capacitive couplings because the transistors used to make samplers are big. It allows more equally distribute the "stress" or fatigue on the three transistors which are of the same size which increases the lifetime of the transistors.
  • the present invention also relates to the application of the method above for large screens.
  • the present invention therefore relates to a method for addressing a flat screen with rows and columns to intersections of which pixels are located, in which X circuits of lines are each connected to Y lines, characterized in that, for a time tr, the preload of the pixels located is carried out on the lines connected to the first line control circuit, to a voltage (Vr) greater than the useful voltage range (V), then we successively sample the Y lines and start the operation again above for the remaining X-1 control circuits.
  • the present invention also relates to a method for addressing a flat screen with rows and columns to intersections of which pixels are located in which X circuits of control lines are each connected to Y lines, characterized in that we simultaneously preload the first line of the X circuits line control at a voltage Vr greater than the voltage range useful (V) and we then successively sample said line of X control circuits lines and we start again the above operation for the Y-1 other lines of each of the X line control circuits.
  • a-Si amorphous silicon
  • FIG. 5 represents an exemplary embodiment of a circuit for column control of a screen allowing the implementation of the process according to the invention.
  • This control circuit is formed by transistors made of amorphous silicon.
  • This control circuit 11 is, from preferably made up of several video inputs operating in parallel to reduce the frequency of demultiplexing accordingly.
  • the column control circuit has five video inputs DB1 to DB5 and six signal inputs from demultiplexing DW1 to DW6, which allows thirty columns to be loaded 12.
  • Each column 12 is controlled by a single transistor 13 which serves successively at the preload to reach the voltage Vr during the time tr, and at convergence to the video voltage value which appropriate.
  • FIG. 6 represents the chronogram of operation of the screen of FIG. 5 when it is used according to the method of the invention.
  • a voltage Vr greater than the voltage useful is applied to all columns via signals DW1 to DW6.
  • the entries DW1 to DW6 are selected successively, as represented by DW1 to DW6, for each signal DB1 to DB5, the useful voltage is sampled during ts.
  • FIG. 7 represents a preferred embodiment of a circuit column control implementing the present invention.
  • each sampler consists of three transistors 16, 17 and 18 which are preferably identical and mounted in parallel.
  • the first electrodes or drains of the three transistors 16, 17 and 18 receive the input video signal 14 while their second electrode or source charges column 15 at order.
  • the gate of transistor 16 is connected at output of a shift register and receives a demultiplexing signal 19 while the gates 20 and 21 of the other two transistors 17 and 18 are connected to two clocks which are described in more detail below.
  • the use of the three transistors makes it possible to compensate for the couplings capacitive which are important with a single large transistor and distribute stress on the transistors, which extends the service life.
  • FIG. 8 represents the timing diagram of a circuit of command lines of the type of that of figure 7.
  • the clock signals applied to transistors 17 and 18 are such that one of the transistors performs the preload of the odd lines while the other performs the preload of even lines.
  • the other transistor 18 receives on its gate 21 a negative pulse of for example -22V until the end of time lines, so that at the end of line time, we can compensate for the coupling of the convergence transistor by means of a positive pulse on the control electrode 21.
  • the gate of transistor 16 will receive a pulse of duration Ts so as to achieve convergence. Preload takes approximately twice as long (2 ⁇ sec) as the convergence (0.9 ⁇ sec), so that the duty cycle of operation of the three transistors is equivalent, which distributes equitably stress.
  • the transistor In the case of a screen with a very large number of lines or with a very large number of elementary pixels, the transistor is undersized to avoid having too large coupling capacities.
  • the basic diagram can be of the type of that of figure 1.
  • Figure 9 which relates to a screen whose column control circuit is identical to the circuit of FIG. 5 and where the lines are grouped by five, each group being controlled by a register lines R1, R2, R3 ... for packets of five lines, we do first a simultaneous preload on lines L1 to L5, then we sequentially samples these same lines L1 to L5. Then we simultaneously preloads lines L6 to L10, etc.
  • This mode of operation is not compatible with control circuits usual (order of five lines at a time). It therefore requires a special electronics.
  • the preload is carried out using a voltage Vr greater than the useful voltage V + / V-.
  • the present invention applies in particular to flat screens with liquid crystals controlled by an active matrix of transistors (AMLCD) in thin layers, and in general for any application requiring a sampler whose relative precision is more important than absolute precision.
  • AMLCD active matrix of transistors

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)
EP97900254A 1996-01-11 1997-01-09 Procede d'adressage d'un ecran plat utilisant une precharge des pixels, circuit de commande permettant la mise en oeuvre du procede et son application aux ecrans de grandes dimensions Expired - Lifetime EP0815552B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR9600259 1996-01-11
FR9600259A FR2743658B1 (fr) 1996-01-11 1996-01-11 Procede d'adressage d'un ecran plat utilisant une precharge des pixels circuit de commande permettant la mise en oeuvre du procede et son application aux ecrans de grandes dimensions
PCT/FR1997/000039 WO1997025706A1 (fr) 1996-01-11 1997-01-09 Procede d'adressage d'un ecran plat utilisant une precharge des pixels, circuit de commande permettant la mise en oeuvre du procede et son application aux ecrans de grandes dimensions

Publications (2)

Publication Number Publication Date
EP0815552A1 EP0815552A1 (fr) 1998-01-07
EP0815552B1 true EP0815552B1 (fr) 2003-05-28

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EP97900254A Expired - Lifetime EP0815552B1 (fr) 1996-01-11 1997-01-09 Procede d'adressage d'un ecran plat utilisant une precharge des pixels, circuit de commande permettant la mise en oeuvre du procede et son application aux ecrans de grandes dimensions

Country Status (7)

Country Link
US (1) US6359608B1 (ko)
EP (1) EP0815552B1 (ko)
JP (1) JP4547047B2 (ko)
KR (1) KR100445675B1 (ko)
DE (1) DE69722309T2 (ko)
FR (1) FR2743658B1 (ko)
WO (1) WO1997025706A1 (ko)

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US5426447A (en) * 1992-11-04 1995-06-20 Yuen Foong Yu H.K. Co., Ltd. Data driving circuit for LCD display
US5510807A (en) * 1993-01-05 1996-04-23 Yuen Foong Yu H.K. Co., Ltd. Data driver circuit and associated method for use with scanned LCD video display
DE69411223T2 (de) * 1993-04-30 1999-02-18 International Business Machines Corp., Armonk, N.Y. Verfahren und Vorrichtung zum Eliminieren des Übersprechens in einer Flüssigkristall-Anzeigeeinrichtung mit aktiver Matrix
JPH06337400A (ja) * 1993-05-31 1994-12-06 Sharp Corp マトリクス型表示装置及び駆動方法
JP3482683B2 (ja) * 1994-04-22 2003-12-22 ソニー株式会社 アクティブマトリクス表示装置及びその駆動方法
JP3451717B2 (ja) * 1994-04-22 2003-09-29 ソニー株式会社 アクティブマトリクス表示装置及びその駆動方法
JPH07319429A (ja) * 1994-05-30 1995-12-08 Matsushita Electric Ind Co Ltd 液晶画像表示装置の駆動方法および液晶画像表示装置
JP3424387B2 (ja) * 1995-04-11 2003-07-07 ソニー株式会社 アクティブマトリクス表示装置
JP3110980B2 (ja) * 1995-07-18 2000-11-20 インターナショナル・ビジネス・マシーンズ・コーポレ−ション 液晶表示装置の駆動装置及び方法

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Publication number Publication date
FR2743658B1 (fr) 1998-02-13
EP0815552A1 (fr) 1998-01-07
WO1997025706A1 (fr) 1997-07-17
JP4547047B2 (ja) 2010-09-22
KR100445675B1 (ko) 2004-12-08
DE69722309T2 (de) 2004-04-08
KR19980702958A (ko) 1998-09-05
FR2743658A1 (fr) 1997-07-18
DE69722309D1 (de) 2003-07-03
US6359608B1 (en) 2002-03-19
JPH11502325A (ja) 1999-02-23

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