WO2006038187A1

WO2006038187A1 - Arbitrary addressable row decoder with start/stop resetting of pixels

Info

Publication number: WO2006038187A1
Application number: PCT/IB2005/053261
Authority: WO
Inventors: John Edward Dean; Lucian Remus Albu; Rafael Aquino
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2004-10-06
Filing date: 2005-10-04
Publication date: 2006-04-13

Abstract

A display apparatus and method includes a display matrix and blanking circuitry. The display matrix includes a plurality of rows of pixels. Display data is sequentially written to each of the plurality of rows of pixels. The blanking circuitry resets at least one row of the plurality of rows of pixels prior to data's being written to the one or more rows. The one or more rows are designated by a start row address and an end row address.

Description

ARBITRARY ADDRESSABLE ROW DECODER WITH START/STOP RESETTING

OF PIXELS

Displays devices are used in a variety of applications. For example, display devices are found in televisions, computer monitors, personal digital assistants (PDAs) and cell phones. As is known, display devices may be based on a variety of technologies. These technologies include CRT, flat panel liquid crystal (LC), plasma, digital light processing (DLP), liquid crystal projection (commonly known as high temperature polysilicon or HTPS) and liquid crystal on silicon (LCOS), to name only a few. Some of these display technologies (e.g. DLP, HTPS, and LCOS displays) include a plurality of pixels arranged in a matrix which may be operated in a color sequential fashion

In a color sequential matrix display, pixels are arranged in rows and columns in the form of a matrix and an optical system illuminates the display with temporally separated wavelengths of light (typically red, green, and blue). Electrical signals scan the rows of the matrix and write video data to the pixels in specific patterns to form images on the display. Each row of pixels may be scanned many times per second. Each scanning line may be specific to a particular display color (e.g. three primary colors). A plurality of scanning lines may drive the display at the same time.

After a pixel has been scanned, material attributes of the pixel may be set according to the address of the pixel. Accordingly, it may be necessary for a pixel to be reset before it is scanned in each scanning cycle. If the pixels are not reset prior to each sequential scanning, undesirable influence from a previous scan period may affect display quality (e.g., color accuracy). Further, the amount of time that the pixel is reset prior to being rescanned may have an effect on display qualities (e.g., contrast and/or brightness). Accordingly, it is desirable to control the amount of rows that are reset prior to the scan, so that brightness and contrast can be controlled.

However, in some matrix displays, there is little flexibility in the number of rows that can be reset prior to the scan of a pixel. Additionally, a large amount of logic is needed to reset pixels during operation of the display. A large amount of logic requires additional circuitry, which can be unnecessarily costly. Additionally, in current displays, it may be difficult to support bi-directional scanning in a display or wraparound of a reset operation during operation of a display. Bidirectional scanning allows the display to be oriented in different directions, at the discretion of the end user. The wraparound relates to the resetting of rows of pixels in a sequential order when the sequential rows are not contiguous (i.e. sequential resetting of the bottom row in the matrix display and then the top row in the matrix display).

What is needed, therefore, is a method and apparatus that substantially overcomes at least the short comings of the current displays. In accordance with an example embodiment, a display apparatus includes a display matrix and blanking circuitry. The display matrix includes a plurality of rows of pixels. Display data is sequentially written to each of the plurality of rows of pixels. The blanking circuitry is adapted to reset at least one row of the plurality of rows of pixels prior to data's being written to the at least one row. The one (or more) row(s) is (are) designated by a start row address and an end row address.

In accordance with another example embodiment, a method includes sequentially writing of display data to each row of a plurality of rows of pixels of a display matrix of the display apparatus. The method also includes resetting the one row (or more) of the plurality of rows of pixels prior to display data's being written. The one row (or more) is designated by a start row address and an end row address.

The invention is best understood from the following detailed description when read with the accompanying drawing figures. It is emphasized that the various features are not necessarily drawn to scale. In fact, the dimensions may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1 is a schematic view of a blanking chain, in accordance with an example embodiment.

Fig. 2 is a diagram of a start/stop row decoder, in accordance with an example embodiment. Fig. 3 is an diagram of blank chain block, in accordance with an example embodiment. Fig. 4 is a diagram illustrating an individual row of a blank chain, in accordance with an example embodiments.

Fig. 5 is an output stage of an individual row, in accordance with an example embodiment. Fig. 6 is an example timing diagram, in accordance with an example embodiment.

In the following detailed description, for purposes of explanation and not limitation, example embodiments disclosing specific details are set forth in order to provide a thorough understanding of the example embodiments. However, it will be apparent to one having ordinary skill in the art having had the benefit of the present disclosure that other embodiments that depart from the specific details disclosed herein. Moreover, descriptions of well-known devices, methods, systems and protocols may be omitted so as to not obscure the description of the present invention. Nonetheless, such devices, methods, systems and protocols that are within the purview of one of ordinary skill in the art may be used in accordance with the example embodiments. Finally, wherever practical, like reference numerals refer to like features.

Briefly, in accordance with illustrative embodiments, methods and apparati provide for resetting (i.e. blanking) a plurality of rows of a display apparatus (e.g. LCOS, LCD, DLP, or plasma display), using a relatively small amount of logic circuitry. Illustratively, at least one of a plurality of rows of pixels resets prior to the display's being written. The one or more row(s) is(are) designated by a start row address and an end row address.

Table 1

Fig. 1 illustrates a simplified blanking chain, in accordance with example embodiments of the present invention. For simplicity, 8 blocks for 8 rows are shown and a bidirectional scanning feature is not illustrated. However, one of ordinary skill in the art having had the benefit of the present disclosure, will appreciate that more blocks (e.g. 1024 blocks for a 1024 row display) may be implemented based on certain factors, such as the resolution of the display. Block 10 is a block at the uppermost row of a display, while block 22 is a block at the lowermost row of the display. Blocks 16 are intermediate blocks that are between blocks 10 and 22. Each block outputs a blanking signal (i.e. blank(i)) based on input signals (e.g. start(i) and stop(i)) and feedback from a previous block (e.g. link(i)).

Each block includes a logical OR gate and a logical AND gate. For example, Block 10 includes OR gate 14 and AND gate 12; block 16 includes OR gate 20 and AND gate 18; block 22 includes OR gate 26 and AND gate 24. The OR gates [14, 20, and 26] receive start signals start(i), which corresponds to the row of that block. The OR gates [14, 20, and 26] also receive the link(i) signal from a previous block in the scanning sequence. The AND gates [12, 18, and 24] receive the outputs of the OR gates [14, 20, and 26] and inverted stop signals to output blanking signals blank(i) and feed back signals link(i). Accordingly, the blanking signal blank(i) will have a 'high' level if either the previous block was blanked (as indicated by the link(i) signal) or the row receives a start signal (start(i)), provided that that block does not receive a stop signal (stop(i)).

For example, referring to Table 1, row 2 receives the start signal start(2) and row 6 receives the stop signal stop(6). As such, and as illustrated in Fig. 1, rows 0, 1, 2, and 7 do not output a blanking signal (i.e. blank(O), blank(l), blank(2), and blank(7)). However, rows 3, 4, 5, and 6 do output a blanking signal (i.e. blank (3), blank(4), blank(5), and blank(6)). The skew in the rows is due to the illustrative implementation of the blanking signal for a given row's being generated in the previous row. To wit, row 2 outputs a blanking signal blank(3) for row 3, because both inputs to AND gate 18 have a high level. In row 3, the blanking output (blank(4)) will have a high level (i.e. link(2) has a high level) will be positive, and stop(3) is at a low level (which gets inverted to a high level prior to being input to AND gate 18) for row 3. However, the blanking signal blank(7) output from row 6 will be negative, because the stop(6) signal is positive (resulting in a low level input into AND gate 18).

It is noted that the processing of each row in the blanking chain, affects the next row. Accordingly, if a stop signal stop(6) is a part of the sixth row, row 6 will still be blank.

Table 2

Illustrative embodiments of the present invention support wraparound. During the row scanning sequence, rows to be blanked can be bridged between the bottom rows of the display and the top rows of the display, as illustrated in Table 2. This is made possible because the blanking output of row 7 is input into the OR gate 14 of row 0. The number of rows to be blank can be determined by the input of a start row address and an end row address as this corresponds to the scanning operation of a display. As illustrated in Fig. 1, the logic is relatively simple and allows for flexible implementation.

Fig. 2 is a diagram of a start/stop row decoder 27, in accordance with example embodiments. The start/stop row decoder includes two row selectors, one blank chain, and one output stage. A plurality of signals are input into the start/stop row decoder 27. The start_addr signal carries the address of the next row that will have pixels updated. The stop_addr signal carries the address of the last row that will be blanked in keeping with the present illustrative embodiment. All rows between the stop_addr and start_addr will be blanked. The clear signal is a link clear signal. When the clear signal is at a high level, link(i) is cleared. The row_sync signal is the synchronous latching signal of the row_blank(i) and row_sel(i) buses. The row_sync signal pulses high once per row. The up_down signal assigns the direction of the scan and therefore the direction of the blanking relative to the current row. The row_enable signal is a high active pulse that is distributed to all rows and gated with the row_sel(i) bus. The blank_enable signal is a high active pulse that is distributed to all rows and gated with the row_blank(i) bus. Embodiment also supports birow (the addressing of pairs of rows) and allrow (the addressing of all the rows), which may be enhancing features of a display apparatus. The row_selector Ul translates the start_addr signal into the row_start(i) bus, while the row_selector U2 translates the stop_addr signal into the row_stop(i) bus. Both the row_start(i) bus and the row_stop(i) bus are input into the blank_chain U3. The blank chain generates two buses (e.g. row_blank(i) and row_sel(i)) which are output from the blank_chain U3 to the output_stage U4. Figure 1 illustrates embodiments of logic circuit structures which are similar to the logic circuit structure of blank_chain U3.

Figure 3 illustrates an example blank_chain block which supports bidirectionality, link clear, synchronization, and birow. The repeatable link structure may be implemented in integrated display circuits. The circuit for each individual link [28, 30, and 32] is illustrated in detail in Figure 4, in accordance with embodiments. The circuit of Figure 4 includes inverters [34, 38], multiplexers [36, 52], OR gates [40, 48, and 50], AND gate 42, and Flip Flops [44 and 46]. One of ordinary skill in the art would appreciate the implementation of the. example circuit illustrated in Figure 4.

In accordance with certain illustrative embodiments, circuitry can be simplified by removing birow, thus eliminating the 4-input multiplexer of figure 4. For example, if the 4-input multiplexer is eliminated, the sig_row_sel(i) signal would be set equal to the row_start(i) signal.

The circuitry for one individual row of the output_stage of the example embodiment shown in Fig. 2 is shown in Fig. 5. Figure 5 is the circuitry which is required for passing the row_en, blk_en or allrow signals to the output rowen(i). The following is an illustrative logical truth table for this block: Table 3

The example circuitry illustrated in Figure 5 includes AND gates [54 and 56] and OR gates [58 and 60]. Figure 6 is an example timing diagram, in accordance with example embodiments.

The detailed timing pipeline illustrates a snapshot of row m being selected and rows m+1, m+2, and m+3 being blanked, followed by row n being's selected with rows n+1 and n+2 blanked. The blank_enable pulses may be relatively narrow and may be applied only during the black period of the ramp. The row enable pulses may be relatively wide and applied for the entire active portion of the ramp. The clear input may be applied just before and after the start_addr signal and stop_addr signal changes. The row_sync may be applied before the start_addr signal and stop_addr signal change.

In view of this disclosure it is noted that the various methods and devices described herein can be implemented in hardware and software known to one skilled in the art. Further, the various methods and parameters are included by way of example only and not in any limiting sense. In view of this disclosure, those skilled in the art can implement the various example devices and methods in determining their own techniques and needed equipment to effect these techniques, while remaining within the scope of the appended claims.

Claims

CLAIMS:

1. A display apparatus comprising: a display matrix including a plurality of rows of pixels, wherein display data is sequentially written to each of the plurality of rows of pixels; blanking circuitry, which is adapted to reset at least one row of the plurality of rows of pixels prior to display data's being written to the at least one row, and wherein the at least one row is designated by a start row address and an end row address.

2. The display apparatus of claim 1, wherein the start row address is an address of a next row of the plurality of rows of pixels.

3. The display apparatus of claim 1 , wherein the end row address is an address of a row that will be reset by the blanking circuitry.

4. The display apparatus of claim 1, wherein the blanking circuitry resets all rows between the start row address and the end row address.

5. The display apparatus of claim 1, wherein the blanking circuitry supports bidirectional writing of display data.

6. The display apparatus of claim 1, wherein the blanking circuitry supports a wraparound.

7. The display apparatus of claim 1, wherein the blanking circuitry comprises: a start row address selector; , an end row address selector; a blank chain; and an output stage.

8. The display apparatus of claim 7, wherein the blank chain comprises: a plurality of blocks, and each block of the plurality of blocks corresponds to a row of the plurality of rows of pixels; and a plurality of feedback connections, each of which connects a block of the plurality of blocks to an adjacent block.

9. The display apparatus of claim 1, comprising an arbitrary addressable row decoder which writes display data to the display matrix.

10. The display apparatus of claim 1, wherein the display apparatus is one of: a flat panel liquid crystal display (LCD); a liquid crystal on silicon (LCOS) display; a plasma display (PDP); and a digital light processing (DLP) display. a high temperature polysilicon (HTPS) display.

11. A method of resetting a display apparatus, the method comprising: sequentially writing display data to each row of a plurality of rows of pixels of a display matrix of the display apparatus; and resetting at least one row of the plurality of rows of pixels prior to display data's being written, wherein the at least one row is designated by a start row address and an end row address.

12. The method of claim 11, wherein the start row address is an address of a next row of the plurality of rows of pixels.

13. The method of claim 11, wherein the end row address is an address of a row to be reset.

14. The method of claim 11, wherein all rows between the start row address and the end row address are reset.

15. The method of claim 1, wherein the resetting is implemented by blanking circuitry.

16. The method of claim 15, wherein the blanking circuitry supports at least one of bidirectional writing of display data and a wraparound.

17. The method of claim 15, wherein the blanking circuitry comprises: a start row address selector; an end row address selector; a blank chain; and an output stage.

18. The method of claim 17, wherein: the blank chain comprises: a plurality of blocks, each of which corresponds to a row of the plurality of rows of pixels; and a plurality of feedback connections, each of which connects a block of the plurality of blocks to an adjacent block.

19. The method of claim 11, wherein the display apparatus comprises an arbitrary addressable row decoder, which writes display data to the display matrix.

20. The method of claim 11, wherein the display apparatus is selected one of: a liquid crystal display; a liquid crystal on silicon display; a plasma display; and a digital light processing display.