EP0815552B1 - Method for addressing a flat screen using pixel precharging, driver for carrying out the method, and use thereof in large screens - Google Patents

Description

The present invention relates to a method for addressing a flat screen, more particularly a liquid crystal screen using a pixel preload. The present invention also relates to a circuit for control of the columns of such a screen allowing the implementation of the process as well as applying the process to large screens dimensions.

Liquid crystal displays with direct vision or projection usually consist of rows (selection rows) and columns (data lines) at the intersections of which the pixel electrodes connected through transistors to these lines. The grids of these transistors form the selection lines and are controlled by peripheral control circuits, generally called "drivers" which scan the lines and make passing the transistors of each line allowing, by the lines of data connected to the other peripheral control circuits, charge the pixel electrodes and modify the optical properties of the liquid crystal between these electrodes and the counter electrode (or reference electrode) thus allowing the formation of images on the screen.

Figure 1 shows the equivalent electrical diagram of a flat screen pixel addressed by line control circuits and columns. The electrode and counter electrode surrounding the liquid crystal form a capacity 1 whose charge (most often constituted by video data) is transmitted by column 2 through the transistor 3 controlled by the selection line 4. Figure 2 as to it represents the chronograms of operation of this pixel, Vs being the signal sent by the selection line of a row of pixels, Vc the video signal sampled on the selected row of pixels and Vp the effective charge of one of these pixels. Theoretically, at the end of a sampling pulse, the pixel voltage Vp across the crystal liquid, should be equal to the column voltage Vc, i.e. +/- V.

The problem with this type of addressing is that in practice, the voltage Vp is different from the load voltage Vc of the column. In Indeed, each transistor 3, when it is in the on state, has a resistance Ron which is not zero, so the charge of the pixel exhibits an exponential characteristic (as shown in FIG. 2) a time constant which is not zero since it is equal to the product Ron x C, C being the value of the capacity 1 of the pixel. When the charging time has elapsed, the residual convergence error is equal to Ven + in positive frame (negative value) or Ven- in negative frame (positive value), different from the +/- V values of the charging voltage Vc.

This results in an error on the RMS voltage which directs the crystal liquid of the order of (Ven + -Ven -) / 2. However, the electro-optical specifications of the screen impose a maximum value for this error of around 5 to 10 mV for a nematic effect in a 90 ° helix. The product RC (resistance by capacity) must therefore typically be 7 to 8 times more low than the addressing time to reach a convergence rate compatible with a quality application. This results in limits on the number of addressable lines and the size of the pixels. In this case, it is necessary to decrease R, ie to widen the transistor. It is not realistic beyond a relationship between width and length of the channel which exceeds a few units. On the other hand, when the pulse Vs applied on the selection line returns to the low state (see figure 2), the coupling noise between the line and the pixel becomes excessive in the event that the width of the transistor exceeds a certain value.

Another known solution is shown in Figure 3. In in this case, a screen 5 made up of pixels 6 is addressed by a circuit control line 7 and a column control circuit 8 formed by samplers controlled by a shift register. The charge of a sampler is none other than the distributed capacity of the column ordered 9. This column must be loaded for a very long time short, with the above-mentioned convergence problems compounded by the the charging time is only a fraction of the time address a line 9. Indeed, during this time line, it is necessary successively sample the video on all columns of the screen. For this reason, the creation of screens with integrated drivers has need to date the use of high semiconductor mobility, such as mono or polycrystalline silicon.

To remedy the above drawbacks and allow the use of thin film transistors made of silicon, it is proposed in particular in PCT / FR94 / 16428, to carry out a pixel preload at a voltage lower than the useful voltage. The use of such a voltage presents a number disadvantages. In particular, it does not resolve the problem of convergence

The present invention provides a new process addressing to overcome the drawbacks mentioned above.

Consequently, the subject of the present invention is a method for addressing a flat screen composed of rows and columns to intersections of which pixels are located, characterized in that, at the start of each sampling of the video signal to be displayed on the screen, a voltage (Vr) greater than the useful voltage range (V) is applied on the selected pixel for a time tr, then the useful voltage is sampled for a time ts.

Preferably, the precharge voltage (Vr) is chosen such that Ven + = Ven- where Ven + and Ven- represent the residual error respectively in positive frame and in negative frame. In this case, the precharge voltage is obtained by the following formulas: Fri + = ( Vr - V +) exp - ts τ ( vg - vt - V +) and Fri - = ( Vr-V- ) EXP- ts τ ( vg - vt - V -) where Vg is the voltage on the gate of the transistor during sampling, and Vt its threshold voltage.

The condition Ven + = Ven- is written: ( Vr - vt ) = ( Vr - V -) EXP- ts ( 1 τ ( vg - vt - V -) - 1 τ ( vg - vt - V +) ) or τ ( vg - vt - V -) = Ron ( vg - vt - V -) xC and Ron = 1 μ Cox W The ( vg - vt - V -) therefore τ ( V ) is of the form Cte / V
hence : ( Vr - V +) = ( Vr - V -) EXP- ts τ ( V + - V -) either : Vr = V + ( V + - V -) EXP- ts τ ( V + - V -) 1-EXP- ts τ ( V + - V -)

The present invention also relates to a circuit for control of the columns of a flat screen of the type comprising samplers controlled by the outputs of a shift register, characterized in that each sampler consists of three MIS type transistors connected in parallel so that their first electrode is connected to the video signal and their second electrode at the controlled column, which gate of the first transistor being connected to one of the outputs of the shift register and the gates of the second and third transistors being connected to two clocks chosen so that both transistors are activated, one for perform the preload of the even lines, the other of the odd lines.

According to another characteristic of the invention, the voltage of the clocks applied to the second and third transistors is chosen from so that when a transistor is not used for preloading, it receives on its grid a negative voltage allowing later compensate for capacitive couplings when this voltage returns to zero.

Preferably, the three transistors are identical and are transistors produced in a thin layer or TFT. This solution allows compensate for large capacitive couplings because the transistors used to make samplers are big. It allows more equally distribute the "stress" or fatigue on the three transistors which are of the same size which increases the lifetime of the transistors.

The present invention also relates to the application of the method above for large screens.

The present invention therefore relates to a method for addressing a flat screen with rows and columns to intersections of which pixels are located, in which X circuits of lines are each connected to Y lines, characterized in that, for a time tr, the preload of the pixels located is carried out on the lines connected to the first line control circuit, to a voltage (Vr) greater than the useful voltage range (V), then we successively sample the Y lines and start the operation again above for the remaining X-1 control circuits.

The present invention also relates to a method for addressing a flat screen with rows and columns to intersections of which pixels are located in which X circuits of control lines are each connected to Y lines, characterized in that we simultaneously preload the first line of the X circuits line control at a voltage Vr greater than the voltage range useful (V) and we then successively sample said line of X control circuits lines and we start again the above operation for the Y-1 other lines of each of the X line control circuits.

• la figure 1, déjà décrite, représente le schéma électrique équivalent d'un pixel d'un écran à cristaux liquides,
• la figure 2, déjà décrite, représente les chronogrammes du fonctionnement du pixel de la figure 1,
• la figure 3, déjà décrite, représente une structure connue d'un écran commandé par des circuits de commande lignes et colonnes,
• la figure 4 illustre un procédé d'adressage d'un écran à cristaux liquides selon la présente invention,
• la figure 5 représente un mode de réalisation d'un circuit de commande colonne connu mettant en oeuvre le procédé d'adressage selon la présente invention,
• la figure 6 représente le chronogramme d'un circuit de commande colonne selon la figure 5,
• la figure 7 représente un mode de réalisation préférentiel d'un circuit de commande colonne mettant en oeuvre le procédé selon la présente invention,
• la figure 8 représente le chronogramme de fonctionnement du circuit de commande colonne de la figure 7, et
• la figure 9 représente schématiquement une partie d'un écran plat de grandes dimensions connecté à des circuits de commande lignes et colonnes utilisant le procédé de la présente invention.

The present invention will be better understood and additional advantages will appear on reading the description which follows, illustrated by the following figures:

• FIG. 1, already described, represents the equivalent electrical diagram of a pixel of a liquid crystal screen,
• FIG. 2, already described, represents the timing diagrams of the operation of the pixel of FIG. 1,
• FIG. 3, already described, represents a known structure of a screen controlled by row and column control circuits,
• FIG. 4 illustrates a method for addressing a liquid crystal screen according to the present invention,
• FIG. 5 represents an embodiment of a known column control circuit implementing the addressing method according to the present invention,
• FIG. 6 represents the timing diagram of a column control circuit according to FIG. 5,
• FIG. 7 represents a preferred embodiment of a column control circuit implementing the method according to the present invention,
• FIG. 8 represents the chronogram of operation of the column control circuit of FIG. 7, and
• FIG. 9 schematically represents a part of a large flat screen connected to row and column control circuits using the method of the present invention.

As shown in Figure 4, for a time reset to zero tr (or "reset" time), we sample on the load a voltage Vr greater than the useful voltage and we sample for a time ts the useful voltage (between + V and -V). Since we seeks to reach the useful voltage (between + V and -V) from a value higher voltage, the residual convergence error is always same sign and equal to (Ven + -Ven -) / 2, which minimizes the error on the RMS voltage.

In the case where the pixel transistors are made of amorphous silicon (a-Si) and have a threshold voltage of a few volts, there is a precharge voltage Vr such that the convergence errors Ven + and Ven- to reach the two extremes of the useful voltage range (+ V, -V) are equal (Ven + = -Ven-). The error on the RMS voltage is then zero. This voltage Vr can be obtained using the formula below: Fri + = ( Vr - V +) exp - ts τ ( vg - vt - V +) and Fri - = ( Vr-V- ) EXP- ts τ ( vg - vt - V -) where Vg is the voltage on the gate of the transistor during sampling, and Vt its threshold voltage.

The condition Ven + = Ven- is written: ( Vr - vt ) = ( Vr - V -) EXP- ts ( 1 τ ( vg - vt - V -) - 1 τ ( vg - vt - V +) ) or τ ( vg - vt - V -) = Ron ( vg - vt - V -) xC and Ron = 1 μ Cox W The ( vg - vt - V -) therefore τ ( V ) esi of the form Cte / V
hence : ( Vr - V +) = ( Vr - V -) EXP- ts τ ( V + - V -) either : Vr = V + ( V + - V -) EXP- ts τ ( V + - V -) 1-EXP- ts τ ( V + - V -)

FIG. 5 represents an exemplary embodiment of a circuit for column control of a screen allowing the implementation of the process according to the invention. This control circuit is formed by transistors made of amorphous silicon. This control circuit 11 is, from preferably made up of several video inputs operating in parallel to reduce the frequency of demultiplexing accordingly. In the example voluntarily simplified in FIG. 5, the column control circuit has five video inputs DB1 to DB5 and six signal inputs from demultiplexing DW1 to DW6, which allows thirty columns to be loaded 12. Each column 12 is controlled by a single transistor 13 which serves successively at the preload to reach the voltage Vr during the time tr, and at convergence to the video voltage value which appropriate.

FIG. 6 represents the chronogram of operation of the screen of FIG. 5 when it is used according to the method of the invention. During time tr, a voltage Vr greater than the voltage useful is applied to all columns via signals DW1 to DW6. Then, the entries DW1 to DW6 are selected successively, as represented by DW1 to DW6, for each signal DB1 to DB5, the useful voltage is sampled during ts.

FIG. 7 represents a preferred embodiment of a circuit column control implementing the present invention. In in this case, each sampler consists of three transistors 16, 17 and 18 which are preferably identical and mounted in parallel. As clearly shown in Figure 7, the first electrodes or drains of the three transistors 16, 17 and 18 receive the input video signal 14 while their second electrode or source charges column 15 at order. On the other hand, the gate of transistor 16 is connected at output of a shift register and receives a demultiplexing signal 19 while the gates 20 and 21 of the other two transistors 17 and 18 are connected to two clocks which are described in more detail below. The use of the three transistors makes it possible to compensate for the couplings capacitive which are important with a single large transistor and distribute stress on the transistors, which extends the service life.

FIG. 8 represents the timing diagram of a circuit of command lines of the type of that of figure 7. The numerical values are only given as an example. In fact, the clock signals applied to transistors 17 and 18 are such that one of the transistors performs the preload of the odd lines while the other performs the preload of even lines. In addition, when one of the transistors, for example the transistor 17 receives on the gate 20 a pulse of preload for a time tr, the other transistor 18 receives on its gate 21 a negative pulse of for example -22V until the end of time lines, so that at the end of line time, we can compensate for the coupling of the convergence transistor by means of a positive pulse on the control electrode 21. The gate of transistor 16 will receive a pulse of duration Ts so as to achieve convergence. Preload takes approximately twice as long (2µsec) as the convergence (0.9µsec), so that the duty cycle of operation of the three transistors is equivalent, which distributes equitably stress.

In the case of a screen with a very large number of lines or with a very large number of elementary pixels, the transistor is undersized to avoid having too large coupling capacities. The basic diagram can be of the type of that of figure 1. To improve the operation of such a screen in which either the transistor is too small to correctly load the pixel in a conventional way, i.e. number of lines is so high that we have very few time for charging, we can also use a diagram of operation with a preload of the type of FIG. 4.

In this case, it is preferable to work in bundles of lines. Thus, as shown in Figure 9, which relates to a screen whose column control circuit is identical to the circuit of FIG. 5 and where the lines are grouped by five, each group being controlled by a register lines R1, R2, R3 ... for packets of five lines, we do first a simultaneous preload on lines L1 to L5, then we sequentially samples these same lines L1 to L5. Then we simultaneously preloads lines L6 to L10, etc. This mode of operation is not compatible with control circuits usual (order of five lines at a time). It therefore requires a special electronics.

We can also if the screen uses for example five circuits of command lines, such as R1, R2, R3, ..., for six hundred lines, load simultaneously these five control circuits, and we use the function often present with "output enable" to successively manage the simultaneous preload for five lines, such as the first five lines L1, L6, I11 in the embodiment of FIG. 9, controlled by these five circuits R1, R2 ..., then the successive addressing of these five lines. However, this solution requires a memory of frame to be able to store and therefore reconstruct the video image.

In all cases, the preload is carried out using a voltage Vr greater than the useful voltage V + / V-.

The present invention applies in particular to flat screens with liquid crystals controlled by an active matrix of transistors (AMLCD) in thin layers, and in general for any application requiring a sampler whose relative precision is more important than absolute precision.

Claims (8)

1. Method for addressing a flat screen composed of lines and columns, with pixels located at their intersections, which applies to the selected pixel for a time tr, at the start of each sampling of the video signal to be displayed on the screen, a precharge voltage (Vr) and then samples the working voltage for a time ts, characterized in that, the precharge voltage is higher than the working voltage range (V).
2. Method according to Claim 1, characterized in that the precharge voltage (Vr), chosen such that Ven+ = Ven- where Ven+ and Ven- represent the residual error respectively in positive video and in negative video, is obtained by the following formula: Ven + = (Vr-V+)exp - ts τ(Vg - Vt - V+) and Ven-=(Vr-V-)exp- ts τ(Vg - Vt - V-)    where Vg is the gate voltage of the transistor during the sampling and Vt is its threshold voltage, and the condition Ven+ = Ven minus is written: (Vr-Vt) = (Vr-V-)exp-ts 1τ(Vg-Vt-V-) - 1τ(Vg-Vt-V+) ) or τ (Vg-Vt-V-) = Ron(Vg-Vt-V-)xC and Ron=1µCoxWL (Vg - Vt - V-) , therefore (V) is of the form CTE / V
   whence (Vr-V+)=(Vr-V-)exp- ts τ(V+-V-) i.e. Vr=V+(Vr+-V-)exp- ts τ(V +-V-) 1 - exp- ts τ(V +-V-) .
3. Column driver for a flat screen, of the type comprising samplers driven by the outputs of a shift register, for implementing the method according to either of claims 1 and 2, in which driver each sampler consists of three MIS-type transistors (16, 17, 18) mounted in parallel so that their first electrode is connected to the video signal (14) and their second electrode is connected to the driven column (15), the gate (19) of the first transistor being connected to one of the outputs of the shift register and the gates (20, 21) of the second and third transistors being connected to two clocks chosen so that one of the two transistors is activated to precharge the even frames and the other is activated to precharge the odd frames.
4. Driver according to Claim 3, in which the clock voltage applied to the second and third transistors is chosen so that, when a transistor is not being used for the precharging, its gate receives a negative voltage compensating for capacitive coupling when the gate voltage subsequently rises again.
5. Driver according to either of Claims 3 and 4, in which the three transistors are identical.
6. Circuit according to any one of Claims 3 to 5, in which the three transistors are produced in thin-film technology.
7. Method for addressing a flat screen according to Claim 1, in which X line drivers are each connected to Y lines, characterized in that, for a time tr, the pixels located on the lines connected to the first line driver are precharged to a voltage (Vr) higher than the working voltage (V), then the Y lines are sampled successively and the above operation is repeated for the X-1 remaining drivers.
8. Method for addressing a flat screen according to Claim 1, in which X line drivers are each connected to Y lines, characterized in that, the first line of each of the X line drivers is precharged to a voltage Vr higher than the working voltage range (V) and the said line of the X line drivers is sampled successively and the above operation is repeated for the Y-1 other lines.

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