EP3079142B1 - Method for displaying images on a matrix screen - Google Patents

Description

The invention relates to a method for displaying images on an active matrix screen. This type of screen has been widely developed in recent years, in particular for screens of the liquid crystal type known by their Anglo-Saxon abbreviation: LCD. More recently other types of screens using light-emitting diodes have been developed, in particular using organic diodes or micro diodes, known by their English abbreviation: OLED, respectively µLED.

Each of the pixels of an active matrix screen contains at least one transistor which acts as a switch connected to a storage component which makes it possible to store a useful signal for the duration of a frame. In the case of a liquid crystal display, these two elements are sufficient to excite the crystal. In the case of a diode screen, each pixel contains a second transistor which makes it possible to control the supply of the light-emitting diode as a function of the useful signal stored in the storage component.

It is known to control the display analogically. More precisely, once per frame, each pixel receives, via its transistor, a voltage representative of the brightness that the pixel must display. This voltage is stored in the storage component, for example a capacitor. For an LCD pixel, the voltage is directly applied to the electrodes surrounding the liquid crystal. For a diode pixel, the voltage is applied to the second transistor configured as a follower to supply the diode in proportion to the stored voltage.

Analog control has several drawbacks:
Voltage leaks at the capacitor may occur during the frame time. This results in a flickering phenomenon (known in the Anglo-Saxon literature under the name of "flickering") which is amplified under the influence of the temperature during the duration of the frame.

Upstream of the first transistor, the voltages pass through conductors of the matrix, generally column conductors. When addressing a pixel line, the voltage variations occurring on the column conductors can disturb the pixels of the other unaddressed lines, by capacitive coupling between the column conductors and the unaddressed storage capacitors. This results in artifacts in the displayed image.

In the case of a diode screen, the light-emitting diodes may require a high bias voltage. The entire pixel must be compatible with this voltage. The voltage stored in the capacitor must then be equal to the bias voltage of the diode to which the gate-source voltage of the second transistor is added. Current CMOS technologies being limited to around 5V, the voltage applied to the light-emitting diode is then capped at less than 4V, which can represent a limitation of the achievable performance in terms of screen brightness.

Still in the case of a diode screen, the diode supply follower transistors may have non-uniform characteristics which causes a phenomenon of spatial noise in the display, because for the same control voltage for separate pixels, the polarization of the diode can then vary from one pixel to another.

In addition, the follower transistor works in saturated mode and it must absorb a voltage difference inversely proportional to the illumination of the light-emitting diode. The power dissipated in this transistor causes significant heating, which can cause heat dissipation problems, especially when this transistor is implanted in an internal layer of the screen.

It is also known to control the display digitally. This type of control has been implemented in particular for light-emitting diode screens and also for screens based on micro-mirrors for projectors using components known in Anglo-Saxon literature under the name of DLP for the abbreviation of "Digital Light Processing". For the diode pixels, the components of each of the pixels are arranged in the same way as for an analog-controlled diode pixel. There is a first transistor for storing information in a capacitor and a second transistor controlling the ignition of the diode according to the information stored in the capacitor. To the unlike analog control, the control of the diodes of each of the pixels is ensured, for digital control, in all or nothing, that is to say, the diode is either connected at its maximum voltage, therefore on, or disconnected, therefore extinct. The brightness of the diode is controlled by modulating the width of the pulse applied between its terminals. The visual perception, because of the inertia of the eye, is the average of the sum of all the times of lighting of the diode.

The command is binary. It applies two possible voltage levels to the gate of the second transistor, which works in switch mode. The amplitude between these two levels must be sufficient to block or not block the second transistor, which can be achieved with relatively low voltage values.

• Réduction de la dissipation sur le second transistor qui fonctionne en mode interrupteur. La tension entre son drain et sa source est très faible lorsqu'il est passant.
• Tension de commande binaire et de faible amplitude.
• Immunité aux différents couplages et fuites, car les pixels fonctionnent en mode binaire.
• Pas d'impact des dispersions des caractéristiques des composants du pixel du fait de leur utilisation en tout ou rien.
• Pas de limitation de luminosité liée à la tension présente aux bornes du condensateur, puisque le second transistor ne travaille pas en mode saturé mais en mode interrupteur.

Digital control has several advantages over analog control:

• Reduction of dissipation on the second transistor which operates in switch mode. The voltage between its drain and its source is very low when it is on.
• Binary and low amplitude control voltage.
• Immunity to different couplings and leaks, because the pixels operate in binary mode.
• No impact of dispersions of the characteristics of the pixel components due to their use in all or nothing.
• No brightness limitation linked to the voltage present across the capacitor, since the second transistor does not work in saturated mode but in switch mode.

The main drawback of digital control is the high operating frequency of the matrix. Indeed, to modulate the pulse width on the light-emitting diode of each pixel, it is necessary to address each pixel and therefore each line several times per frame.

This drawback appears in particular with a binary code modulation control method well known in the English literature under the acronym BCM for "Binary Code Modulation". This method is also known under the name of "Time Gray Scale Method".

In this family of control methods, the brightness of a pixel is coded in the form of a binary word. Each bit of the binary word controls the diode for a duration proportional to the weight of the bit.

The light-emitting diode is controlled for a time proportional to the weight of the bit of the value to be displayed. For example, the most significant bit (MSB) drives the diode for half the duration of the frame (for example 10 ms for a frequency of 50 images / second). The next bit (MSB-1) represents a quarter of this duration, and so on up to the least significant bit (LSB). By Convention, the diode is lit when the value of a bit is 1 and is off when the value of a bit is 0. The opposite convention is of course possible.

For example, if the brightness of a pixel is coded on 8 bits, a value of the binary word of 01010101 (= 85) will give a brightness of the pixel in a ratio of 85/256 compared to the maximum brightness of the pixel.

For such control, it is necessary to access the pixel 8 times per frame, thus defining 8 subframes. During the sequential writing of the matrix it is often necessary to extinguish the light-emitting diodes in order to allow the complete addressing of the matrix and to respect the proportion between the different durations of the sub-frames. This extinction duration can be estimated at the duration of control of the least significant bit. The reduction in brightness is P / 2 ^P , with P equal to the number of brightness bits. The loss is, for example, of the order of 3% for P = 8 and 1% for P = 10 bits. These losses of luminosity can be sometimes acceptable, but the necessary operating frequencies can be prohibitive for large matrices.

fps définissant le nombre d'images par seconde et N_ligne le nombre de lignes de la matrice.For fast addressing, for example based on the duration of the least significant bit, the frequency F _line to which each line of the matrix must be addressed is equal to: $${\mathrm{F}}_{\mathrm{line}}=\mathrm{fps}*{\mathrm{NOT}}_{\mathrm{line}}*2^{\mathrm{P}}$$

fps defining the number of images per second and N _line the number of lines of the matrix.

The frequency F _pix at which one must write in each of the pixels of a line is the frequency F _line multiplied by the number of pixels per line which corresponds to the number of columns N _col of the matrix: $${\mathrm{F}}_{\mathrm{pix}}={\mathrm{F}}_{\mathrm{line}}*{\mathrm{NOT}}_{\mathrm{collar}}$$

For a matrix format of 640 columns by 480 lines, format known as VGA, for a coding of the brightness on 10 bits, the frequency F _pix is then greater than 15GHz and for a format of 1920 columns by 1200 lines, format known as WUXGA, still for 10-bit coding, the frequency F _pix is then 118GHz. These frequencies are in practice difficult to achieve by low-cost technologies. They also involve significant consumption.

It would be possible to parallelize the inputs in order to reduce the frequencies involved, but this would be to the detriment of the simplicity and the number of additional inputs to be implemented.

By admitting a loss of brightness, it is possible to increase the writing time. For example, for a brightness coded on 10 bits, with a reduction of brightness of 10%, the frequencies in play would be reduced by a factor 10. Even with this concession on the maximum brightness of the screen, the frequencies for large formats still remain very high.

The document US2003 / 011314 describes an example of an active matrix OLED screen.

The invention aims to overcome all or part of the problems mentioned above by proposing a digital control method making it possible to reduce the frequency of addressing of the pixels.

To this end, the invention relates to an image display method as defined by claim 1.
The dependent claims define other embodiments of the display method.

The choice of the first current line from which repetitions are performed is completely arbitrary. i represents a line pointer which increments with each write and the complete sequence of writes is carried out after 2 ^P -1 writes.

For each current line i, the entries made on lines i + 2 ^j occupy a period T _i . Advantageously, the 2 ^P -1 periods T _i have equal durations.

Advantageously, the duration of a period T _i is equal to the duration of an image frame divided by 2 ^P -1.

In a particular embodiment of the matrix, each of the pixels further comprises a switch making it possible to control the display component as a function of a state of the bit written in the memory. For each of the pixels, the switch is actuated to control the display component as a function of the bit written in the memory for a period extending between two successive writes.

In another particular embodiment of the matrix, the method can also consist, for each of the pixels, in activating the display component after writing to the corresponding memory. The writes to lines i + 2 ^j made from the current line i are made during a period. The display component is activated for a duration extending from the end of the period during which the bit of brightness was written until the end of the next period during which a new writing is carried out in the pixel concerned.

In this other embodiment, the memory of each pixel is called the first memory. Each pixel advantageously includes a second binary memory making it possible to transmit the bit written in the first memory to the display component to activate it. The addressing means control the first memory by means of a first signal allowing the writing and control the second memory by means of a second signal distinct from the first signal and allowing the activation of the display component.

If the brightness is expressed in a number of R useful bits and the number of lines N is greater than 2 ^R -1 then we can add to the binary word a number T of bits whose values are equal to zero, corresponding to an extinction display components so that N is less than or equal to 2 ^P -1 with P = R + T.

Alternatively, if the brightness is expressed in a number of S useful bits and the number of lines N is greater than 2 ^S -1, the matrix is divided into zones controlled separately, each of the zones having a number of lines less than or equal to 2 ^S -1.

If the matrix includes a number of useful lines U less than 2 ^P -1 then the distribution of the writes is configured to chain the writes on N lines with N = 2 ^P -1 including U useful lines and V virtual lines with U + V = N. For virtual lines, the binary word contains only value bits corresponding to an extinction of the display component.

For each current line i given, the writes on the lines i + 2 ^j , from j = 1 to j = P of the different bits are advantageously ordered so as to minimize an error over a desired duration separating two successive writes of the same pixel .

For each current line i given, the writes to the lines i + 2 ^j , from j = 1 to j = P of the different bits can be carried out for a duration less than the duration of a period equal to the duration of a frame divided by the number of lines written.

• la figure 1 représente schématiquement un écran matriciel destiner à fonctionner avec un procédé conforme à l'invention ;
• les figures 2a, 2b et 2c représentent trois exemples de schémas de pixels pouvant être implantés dans l'écran matriciel de la figure 1 ;
• la figure 3 illustre une étape d'écriture de données de luminosité dans les pixels de l'écran de la figure 1 ;
• les figures 4a à 4p représentent un enchainement de périodes d'écriture dans des mémoires des pixels de la matrice ;
• les figures 5, 6 et 7 représentent des exemples de registres permettant de piloter la matrice ;
• les figures 8a et 8b représentent sous forme de chronogramme un premier mode d'enchainement des périodes d'écriture décrites précédemment ;
• les figures 9 et 10 représentent des variantes du chronogramme des figures 8a et 8b ;
• les figures 11a et 11b représentent deux variantes de schéma de pixels pouvant être implantés dans l'écran matriciel de la figure 1 ;
• la figure 12 représente une variante de chronogramme adaptée aux pixels des figures 11a et 11b ;
• les figures 13 et 14 illustrent la mise en œuvre du procédé de l'invention à tout format de matrice.

The invention will be better understood and other advantages will appear on reading the detailed description of an embodiment given by way of example, description illustrated by the attached drawing in which:

• the figure 1 schematically represents a matrix screen intended to operate with a method according to the invention;
• the Figures 2a, 2b and 2c represent three examples of pixel diagrams that can be implanted in the matrix screen of the figure 1 ;
• the figure 3 illustrates a step of writing brightness data in the pixels of the screen of the figure 1 ;
• the figures 4a to 4p represent a sequence of writing periods in the memories of the pixels of the matrix;
• the figures 5 , 6 and 7 represent examples of registers making it possible to control the matrix;
• the figures 8a and 8b represent in the form of a chronogram a first method of linking the writing periods described above;
• the figures 9 and 10 represent variants of the chronogram of figures 8a and 8b ;
• the Figures 11a and 11b represent two variants of pixel diagram that can be implanted in the matrix screen of the figure 1 ;
• the figure 12 represents a variation of chronogram adapted to the pixels of Figures 11a and 11b ;
• the Figures 13 and 14 illustrate the implementation of the method of the invention in any matrix format.

For the sake of clarity, the same elements will have the same references in the different figures.

The figure 1 represents a matrix screen 10 comprising a display area 11 formed of pixels 12 organized in rows and columns, a line addressing circuit 13 and a horizontal register 14. Each pixel 12 lights up as a function of a luminosity datum expressed in the form of a binary word. The line addressing circuit 13 selects the lines of the matrix one by one and for each pixel 12 of a selected line, the binary word stored in the horizontal register 14 and representing the brightness is transferred bit by bit to the pixel 12 corresponding.

The Figures 2a, 2b and 2c represent three examples of 12 pixel schemes that can be implemented in the screen of the figure 1 . These three examples of pixels can be implemented in a monochrome or color screen. For a color screen, we sometimes use the name "color pixel" which is actually formed by juxtaposition of several pixels each associated with a color filter. Each group of pixels receives separate brightness controls for each color. The method of the invention is illustrated from pixels implemented in a monochrome screen and can be transposed to the control of a color screen by replicating the command of each of the elementary pixels forming the color pixel.

The figure 2a schematically represents the main components of a pixel 12a with liquid crystals. The pixel 12a comprises a switch 20, a storage capacitor 21 and a liquid crystal cell 22. The pixel 12a is connected to a column conductor 23 carrying the brightness data coming from the horizontal register 14. The switch 20, for example formed by a transistor, makes it possible to transfer the brightness data from the column conductor 23 to the capacitor 21. The pixel 12a is also connected to a line conductor 24 connected to the line addressing circuit 13. The switch 20 is controlled by the line conductor 24. The data stored in the capacitor 21 forms a voltage directly applied to one of the electrodes of the cell 22. The data stored in the capacitor 21 is binary. One of the binary states makes cell 22 transparent and the other state makes cell 22 opaque. In the case of a backlit screen 10, the cell 22 therefore lets light pass as a function of the binary state of the data stored in the capacitor 21. The cell operates in all or nothing mode as a function of the binary state of the data stored in the capacitor 21.

The figure 2b schematically represents the main components of a pixel 12b with light-emitting diode. We find in pixel 12b the switch 20 and the storage capacitor 21, both connected to conductors 23 and 24. In place of cell 22, pixel 12b includes a light-emitting diode 25 and a second switch 26 allowing supply the diode 25 by means of a supply voltage V _DD . The switch 26 can also be a transistor. The switch 26 is controlled by the data stored in the capacitor 21.

The figure 2c represents a pixel 12c forming a variant of pixel 12b. In the pixel 12c, the capacitor 21 is replaced by a binary memory 27. This memory makes it possible to store binary information. The binary memory can be formed by a flip-flop connected to its input to the column conductor 23 and to its output to the control terminal of the switch 26. The memory 27 is controlled by the line conductor 24. The modification of the information stored in memory 27 occurs during a command carried on the line conductor 24.

Such a memory can also be implemented for a liquid crystal pixel in replacement of the capacitor 21 of the pixel 12a. The implementation of a memory can be advantageous for a matrix comprising pixels produced using CMOS technology. The switches 20 and 26 as well as the memory 27 then all use the same technology.

Thereafter, the term memory will be used as well for a capacitor as for any other component or block of component making it possible to memorize binary information. As such, the capacitor 21 is assimilated to a memory.

The invention can be implemented for any type of pixel making it possible to emit light such as those comprising a light-emitting diode, to control the light passing through it such as those comprising a liquid crystal cell or to control the reflection of light like those implemented in a screen or a projector based on micro-mirrors. Subsequently the component of the pixel used to emit or control the light will be called the display component.

In the piloting method of the invention, the brightness control of a pixel is done by means of a binary word representing a fraction of the maximum brightness of the pixel. To display an image, each pixel is assigned a brightness value coded in the form of a binary word. During the duration of an image, the different bits of the binary word are written in the memory of the pixel and used by the display component operating all or nothing during a fraction of the duration of the image. This fraction of time depends on the weight of the bit in the binary word. The most significant bit is used by the display component for substantially half of the duration of an image, the next bit for the quarter of the duration of the image and so on by dividing the fraction by two up to 'to the least significant bit. Screen 10 allows for example to display 50 images per second. The retinal persistence of a user makes it possible to average these fractions of duration to reconstitute the average brightness of the pixel. The method of the invention consists in writing line by line the different bits of the binary words in the different memories of the corresponding pixels so as to reduce the writing frequency necessary to scan the whole matrix.

It is possible to deactivate the display component for a certain time by controlling the backlight for a liquid crystal or micro-mirror screen or by disconnecting the diode supply.

The invention is concerned with the sequence of writing periods in the different pixels of the matrix.

• à partir d'une ligne courante i, écrire sur les lignes i+2^j, de j=1 à j=P, le bit de poids j de chaque mot binaire associé aux différents pixels des lignes i+2^j ;
• répéter 2^P-1 fois les écritures mentionnées plus haut en décalant le pointeur i de la ligne courante d'une unité à chaque répétition ;

le rang du pointeur i d'une ligne étant déterminé modulo 2^P-1 de façon à être compris entre 1 et 2^P-1.More precisely, from a matrix of N lines, i representing the pointer of a current line, by considering the bits of each binary word arranged according to their weight from j = 1 to j = P, 1 representing the bit of weight weak and P the most significant bit, the method consists in chaining the following writes during the duration of an image frame:

• from a current line i, write on the lines i + 2 ^j , from j = 1 to j = P, the bit of weight j of each binary word associated with the different pixels of the lines i + 2 ^j ;
• repeat 2 ^P -1 times the above mentioned writes by shifting the pointer i of the current line by one unit at each repetition;

the rank of the pointer i of a line being determined modulo 2 ^P -1 so as to be between 1 and 2 ^P -1.

• Le bit de poids faible LSB (j=1) est écrit sur la ligne : (N-1) +2¹ = N+1 = 1.
• Le bit LSB+1 (j=2) est écrit sur la ligne : (N-1) +2² = N+3 = 3.
• Le bit LSB+2 (j=3) est écrit sur la ligne : (N-1) +2³ = N+7 = 7.
• Et ainsi de suite jusqu'au bit de poids fort (j=P) qui est écrit sur la ligne : (N-1) + 2^P = 2N = N.

By considering a matrix comprising N lines with N = 2 ^P -1, during a particular period where i is fixed at N-1, P lines are written during this period. With the numbering convention for the modulo 2 ^P -1, N lines in this case:

• The least significant bit LSB (j = 1) is written on the line: (N-1) +2 ¹ = N + 1 = 1.
• The LSB + 1 bit (j = 2) is written on the line: (N-1) +2 ² = N + 3 = 3.
• The LSB + 2 bit (j = 3) is written on the line: (N-1) +2 ³ = N + 7 = 7.
• And so on until the most significant bit (j = P) which is written on the line: (N-1) + 2 ^P = 2N = N.

During a given period, we have just written the least significant bit on a given line (i + 1 with the convention previously used). This same line will be written again at the immediately following period. On the other hand, for the line on which the most significant bit has just been written, it will be necessary to wait substantially N / 2 periods for this same line to be rewritten. This method makes it possible to maintain a writing usable by the display component for a variable duration as a function of the weight of the written bit. This duration is substantially equal to (2 ^{d /} 2 ^P ) x (frame duration / 2).

For each current line i, the entries made on lines i + 2 ^j occupy a period T _i . In other words, each of the repetitions occupies a period T _i . To make a complete frame, 2 ^P -1 periods T _i are linked. Advantageously, the different periods have the same duration. This makes it possible to respect the agreement on a frame between the value of the binary word and the sum of the activation times of the display component.

To limit the losses of brightness compared to a maximum brightness corresponding to a complete activation of the display component during a complete frame, the different periods occupy the entire frame. In other words, the duration of a period T _i is equal to the duration (T _frame ) of an image frame divided by 2 ^P -1.

The figure 3 visually represents on a frame the durations usable for each of the bits of the binary word coding the brightness of each of the pixels. Each row of the matrix being scanned during a frame, the durations between each rewrite can be expressed in number of lines representing fractions of the total duration of the frame. On the figure 3 , half the rows in the matrix contain MSB-1 most significant bits, a quarter of the rows contain MSB-1 weight bits, the eighth of the rows contain MSB-2 weight bits and so on up to one line, the lowest line on the figure 3 , containing least significant bits.

The implementation of the invention makes it possible to significantly reduce the frequency of addressing and writing of the different bits of the binary word representing the brightness of each of the pixels of the matrix. With digital control of the prior art, the line frequency is given by: $${\mathrm{F}}_{\mathrm{line}}=\mathrm{fps}*{\mathrm{NOT}}_{\mathrm{line}}*2^{\mathrm{P}}$$

With digital control implementing the invention, the line frequency becomes: $${\mathrm{F}}_{\mathrm{line}}=\mathrm{fps}*\left(2^{\mathrm{P}}-1\right)*\mathrm{P}$$

The frequency is lowered in a ratio close to: N _line / P.

The figures 4a to 4p represent an example of a sequence of writing periods in the memories of the different pixels of the matrix. More specifically, in the example illustrated with the figures 4a to 4p , the brightness is coded on 4 bits. It is understood that the brightness can be coded on a larger (or smaller) number of bits. So that a user perceives practically no difference in brightness between two successive levels of coding the brightness of a pixel, coding on 8 to 10 bits may be suitable. In the example illustrated, the matrix comprises N = 15 lines of pixels, which corresponds to 2 ^P -1 lines, P representing the number of bits of the brightness coding. The invention is not limited to this number of lines. We will see later how to increase or decrease the number of lines compared to 2 ^P -1.

Conventionally, the binary words coding the brightness, include bits identified D0, D1, D2 and D3, ordered from the least significant bit D0 also called LSB for its English abbreviation: “Low Significant Bit” to the most significant bit D3 also called MSB for its Anglo-Saxon abbreviation: "Most Significant Bit".

During the first writing period, represented on the figure 4a , the most significant bit D3 is written on the first line of the matrix, the bit of least significant D0 is written on the second line, bit D1 is written on the fourth line of the matrix and bit D2 is written on the eighth line of the matrix. For each column 23 of the matrix, only one bit can be written simultaneously. The four writes of bits D0 to D3 are carried out successively during the first period. For this first period, the last line is considered as the current line i (i = N).

For the second period, represented on the figure 4b , we shift the current line i by one rank: i = N + 1 modulo 2 ^P -1, that is to say i = 1. More specifically, during the second period, represented on the figure 4b , the most significant bit D3 is written on the second line of the matrix, the least significant bit D0 is written on the third line, the bit D1 is written on the fifth line of the matrix and the bit D2 is written on the ninth row of the matrix.

Periods 3 to 15 are then linked in the same way by shifting the current line at each period by one line. During the eighth period, represented on the figure 4h , bit D2 is written on the eighth line. Having reached the last row of the matrix, the shifts made for the ninth period are done in a rotating fashion, that is to say that the shifts are incremented by one unit modulo the number of rows in the matrix. In other words, it is considered that the fifteenth line of the matrix is followed by the first line and during the ninth period the bit D2 is written on the first line of the matrix.

During period 15, represented on the figure 4o , the current line is line 14. During periods 1 to 15 all the lines of the matrix were written with all the bits of the binary words representing the brightness of the different pixels of the matrix. The figure 4p represents a period 16 for a new image or frame. This period 16 is similar to period 1 with new values of the binary words corresponding to the new image.

In practice it is possible to start the sequence of writing periods at any line of the matrix. The complete sequence is carried out after 2 ^P -1 writing periods.

The figure 5 represents an example of shift register which can be used in line addressing circuit 13 to generate the line selection signals Li, signals conveyed on the line conductors 24. For each line i, the signal Li is formed using P flip-flops D: Di-1 to Di-P connected in series. The output of the Di-P flip-flop forms the signal Li of line i and is connected to the input of the Di + 1-1 flip-flop. A clock signal CLK is common to all the flip-flops D. Tokens J are introduced at the input of flip-flop D1-1 with a time difference of 2 ^j times the duration of a period. This embodiment of the line addressing circuit 13 has a drawback due to the large number of flip-flops which have to switch simultaneously. This implies significant and significant consumption peaks. The congestion on the surface of this type of register is also penalizing.

The figure 6 represents an alternative allowing to realize the line addressing circuit 13. This alternative is more compact and less energy consuming. The line addressing circuit 13 comprises an address decoder 31, an adder 32, a shift register 33 at P bits and a counter 34 at P bits, P = 4 in the example shown. The counter 34 receives a clock CLK operating at the frequency of each period. The shift register 33 receives a clock P times faster than the clock of the counter 34 and a Start start token at the start of each period. The shift register 33 shifts the start signal to the rhythm of its clock, which allows a binary number equal to 2 ^P to be sent to the adder 32. The adder 32 also receives the output of the counter 34. The adder 32 performs the addition of the binary number and the output of the counter 34. The result of the addition is transmitted to the decoder P to N, here a decoder 4 to 16 of which only 15 outputs are connected, each to a line conductor 24 of the matrix 11. By period, the rows of rank 2 ^j + k are addressed successively, k representing an integer incremented by one by the counter 34 to each new period.

The figure 7 shows an exemplary embodiment of the horizontal register 14 which comprises two shift registers 41 and 42 having as many bits as there are lines in the matrix. Register 41 is used as a buffer for recording the brightness data. The register 42 is used for the sequential writing of the lines addressed by the line addressing circuit 13.

The figures 8a and 8b represent in writing form the writing periods described above. These timing diagrams can be easily implemented using the line addressing circuits described on the figures 5 and 6 . The figures 8a and 8b allow to illustrate a first embodiment of succession of the different writings within the periods.

At the top of the chronogram, a regular CLK clock makes it possible to clock the different entries of the different periods. Under the representation of the CLK clock are represented, line by line, the writings of the different bits of the words representing the brightness of the different pixels.

During the first period, four clock ticks t ₁ to t ₄ occur. At the first top t ₁ , the bit D3 of the first line is written. At the second top t ₂ , the bit D0 of the second line is written. In the third top t ₃ , the bit D1 of the fourth line is written and in the fourth top t ₄ , the bit D2 of the eighth line is written.

At each period, the offset of a current line described above allows the complete chronogram of the Figures 4a and 4b from the first period to period 16 represented on the figure 8b .

This first embodiment has the advantage of a regular clock and of writing in the order of the bit weights. However, the duration for each bit is not exactly a multiple of the duration of a period because of the division of the period into four phases. For example, the least significant bit D0 can be used by the display component for a period of ¾ period and the bit D1 for 1 + ¾ period. This quantization error is due to the choice of the sequence of the different bits. This error may be acceptable for coding binary words on a larger number of bits.

The figure 9 represents a timing diagram of a second embodiment of the sequence of entries making it possible to reduce the error previously described. There is always a regularly distributed clock. To simplify, only the first periods are shown in this figure. In this second embodiment, during the first period, at the first top t ₁ , the bit D0 of the second line is written. At the second top t ₂ , the bit D3 of the first line is written. In the third top t ₃ , the bit D2 of the sixth line is written and in the fourth top t ₄ , the bit D1 of the eighth line is written. In this embodiment, the least significant bit D0 can be used by the display component for a duration of 1 + ¼ of period, the bit D1 for 1 + ¾ of period, the bit D2 for 3 + ½ of period , bit D3 for 8 + ¼ period. The error on the duration remains this time less than half the duration expected for the least significant bit D0. This error is typically of the same order of magnitude as that of a digital-analog converter often used in a horizontal register implemented in an analog control. It is possible to empirically test different schedules of the brightness bits in order to minimize the quantization error.

The figure 10 represents a timing diagram of a third embodiment of the sequence of writes also making it possible to reduce the error on the durations of use of the different bits. The four phases of a period are this time generated for a duration less than that of the period whose duration is equal to the duration of an image frame divided by the number of lines written 2 ^P -1. To illustrate this embodiment, the four phases are for example generated during half of the period. This is achieved by doubling the clock frequency. The error is then halved.

It is of course possible to couple the second and third embodiments by proposing a sequence of the bits different from the natural sequence in the order of the weights of the bits and by increasing the clock frequency to concentrate the writes of the different bits in only part of each of the periods.

It is possible to completely eliminate the quantization error whatever the scheduling used for writing the different brightness bits by activating the display component for a period extending from the end of a period during which the bit of brightness was written until the end of the next period during which a new writing is carried out in the same pixel. This duration activation can be obtained by adding in the pixel a second memory controlled by a specific line signal.

The figure 11a represents a pixel 12d making it possible to implement this activation duration offset from the writing. In this pixel, we find, as in pixel 12b, the switch 20, the storage capacitor 21, both connected to the conductors 23 and 24, the light-emitting diode 25 and the switch 26 enabling the diode 25 to be supplied by means of the supply voltage V _DD . In pixel 12d, the capacitor 21 does not directly control the switch 26. A new switch 41 is interposed between the capacitor 21 and the control grid of the switch 26. The switch 41 is controlled by a specific signal conveyed on an additional line conductor 42 distinct from the conductor 24. A parasitic capacitance 43 present at the common point of the switches 26 and 41 acts as a second memory controlled by the specific signal. If necessary, it is of course possible to add a capacitor in addition to the stray capacitance. The specific signal makes it possible to transmit the charges stored in the capacitor 21 to the stray capacitance 43 at the desired time.

The figure 11b represents a pixel 12e forming a variant to pixel 12d also making it possible to implement the offset of the activation time with respect to writing. We find in pixel 12e, as in pixel 12c, the binary memory 27 receiving information to be stored by the column conductor 23 and controlled by the row conductor 24. We also find the light-emitting diode 25 and the switch 26 allowing d 'supply the diode 25 by means of a supply voltage V _DD . In pixel 12e, the binary memory 27 does not directly control the switch 26. A second binary memory 45 is interposed between the binary memory 27 and the control grid for the switch 26. The memory 45 is driven by the signal specific carried on the additional line conductor 42.

The figure 12 represents in the form of a timing diagram the signals conveyed on the line conductors 24 and 42. As previously on the figures 8 , 9 and 10 , the time axis carries the different writing periods of the matrix. To simplify understanding, we have kept a resolution of brightness on 4 bits. The chronogram of the figure 12 resumes the natural scheduling of the writing of the different brightness bits, scheduling presented on figures 8a and 8b . For each of the 15 rows of the matrix, two signals S1 and S2 are represented, the signal S1 conveyed by the conductor 24 and the signal S2 by the conductor 42. The signals S1 conveyed by the various conductors 24 are identical to those described in l help from figure 8a .

During the first period, and more precisely at the first top t ₁ , the bit D3 of the first line is written. This bit is conveyed by the column conductor 23 and the top t ₁ forms the signal S1 conveyed by the conductor 24 of the first line. For the signal S2 conveyed by the conductor 42, a rising edge allows the content of the memory 27, or the voltage present in the capacitor 21 to control the switch 26. The state, passing or blocked, of the switch 26 is maintained as long as a new rising edge does not appear on the conductor 42. To prevent writing in the memory 27 (or on the capacitor 21) disturbing the control of the switch 26, a falling edge appears on the signal S2 at the start of the first period shortly before the appearance of the bit D3 at the top t ₁ .

For the second line, bit D0 is written to top t ₂ of the first period and bit D3 is written to top t ₁ of the second period. For the signal S2 of this second line, a first rising edge occurs at the end of the first period authorizing the activation of the diode 25 by the value of the bit D0. A second rising edge occurs at the end of the second period authorizing the activation of the diode 25 by the value of the bit D3. The diode was activated by bit D0 for exactly one period.

The signals S1 and S2 of the third line are temporally offset by a period with respect to the signals of the second line.

For the fourth line, the bit D1 is written at the top t ₃ of the first period and the bit D0 is written at the top t ₂ of the third period. For the signal S2 of this second line, a first rising edge occurs at the end of the first period authorizing the activation of the diode 25 by the value of the bit D1. A second rising edge occurs at the end of the third period authorizing the activation of the diode 25 by the value of the bit D3. The diode 25 was activated by the bit D1 during exactly two periods separating the two rising edges occurring at the end of the first period and at the end of the third period. And so on for the different bits D0 which activate the diode 25 during one period, the bits D1 during two periods, the bits D2 during four periods and the D3 bits for eight periods. More generally, the weight bits j activate the display component for 2 ^j periods.

Pixels 11d and 11e as well as the associated timing diagram shown on the figure 12 , refer to a diode 25. It is understood that these variants can be implemented for any other type of display component, such as for example a liquid crystal cell or a micro mirror.

The method described above has a limitation in the existence of a link between the number N of lines of the matrix and the number P of bits of resolution of the binary word representing the luminosity. More precisely: N = 2 ^P - 1. For example, an eight-bit resolution requires a 255-line matrix and a 10-bit resolution requires a 1023-line matrix.

It is possible to overcome this limitation, for example if one wishes to address a matrix having a number of lines double that which the preceding link imposes, for example 510 lines for a resolution of 8 bits. A first solution consists in artificially increasing the number of bits by one by systematically assigning a 0 to the new least significant bit LSB. This solution can also be implemented if one wishes to multiply the number of lines by any power of two. For example, to quadruple the number of lines, two additional bits can be added.

The figure 13 offers an alternative to adding a least significant bit. More specifically, the line addressing circuit is duplicated and each circuit operates separately. On the figure 13 , two line addressing circuits 13a and 13b are shown, each addressing one half of the matrix 11. More generally, the matrix 11 is divided into zones, 11a and 11b in the example shown, each of the zones having a number of lines less than or equal to 2 ^P -1. Here again, it is possible to multiply the number of line addressing circuits by any integer.

Widely used video formats rarely have line numbers corresponding to powers of two. It is nevertheless possible to implement the method of the invention for any format. In this Indeed, to free oneself from this constraint, it is possible to choose a number of lines 2 ^P -1, addressed by the method of the invention, greater than the number of real lines of the matrix. Beyond the actual lines, the remaining addressed lines will be virtual by assigning them a zero brightness value.

The figure 14 describes the implementation of such virtual lines. Several periods are represented there in a similar way to the representation of figures 3 or 4 . The total number of lines addressed 2 ^P - 1 is represented along a vertical axis. The number of real lines U of the matrix is equal to (2 ^P - 1) - V, V representing the number of virtual lines remaining addressed and whose luminosity value is advantageously zero.

The principle of implementing virtual lines can of course be combined with the multiplication of the number of lines described above. This allows the method of the invention to be used without any limitation on the number of real rows of the matrix, whether this number is less than or greater than 2 ^P - 1.

Claims (11)

1. Method for displaying images on a matrix screen (10) comprising several rows of pixels (12, 12a, 12b, 12c), the rows being ordered from i=1 to i=N, N representing the number of rows,
   each pixel comprising a display component (22, 25) and a memory (21, 27),
   the matrix screen (10) comprising addressing means (13) for each of the rows and data transfer means (20) to the memory (21, 27) of each of the pixels (12),
   the method consisting in controlling the brightness of each of the pixels (12) of the matrix screen (10) by means of a binary word comprising several bits (D0, D1, D2, D3) written successively through the data transfer means (20), into the memory (21, 27) and by controlling the display component (22, 25) as a function of a state of the bit written into the memory (21, 27), the bits of each binary word being ranked according to their weight from j=1 to j=P,
   the method being characterized in that it consists in sequencing the following writes for the duration (T_frame) of an image frame:

   • from a current row i, writing on the rows i+2^j, from j=1 to j=P, the bit of weight j of each binary word associated with the different pixels of the rows i+2^j;

   • repeating, 2^P-1 times, the writes mentioned above by shifting a pointer of the current row by one unit on each repetition;

   the pointer of a row being determined: i modulo 2^P-1 so as to lie between 1 and 2^P-1.
2. Method according to Claim 1, characterized in that, for each current row i, the writes performed on the rows i+2^j occupy a period T_i, and in that the 2^P-1 periods T_i have equal durations.
3. Method according to Claim 2, characterized in that the duration of a period T_i is equal to the duration (T_frame) of an image frame divided by 2^P-1.
4. Method according to one of the preceding claims, characterized in that each of the pixels (12b, 12c) further comprises a switch (26) making it possible to control the display component (25) as a function of a state of the bit written into the memory (21, 27) and in that, for each of the pixels, the switch (26) is actuated to drive the display component (25) as a function of the bit written into the memory (21, 27) for a duration extending between two successive writes.
5. Method according to any one of Claims 1 to 3, characterized in that it consists, for each of the pixels (12d, 12e), in activating the display component (22, 25) after writing in the corresponding memory (21, 27), in that the writes on the rows i+2^j performed from the current row i are performed during a period, and in that the display component (22, 25) is activated for a duration extending from the end of the period during which the brightness bit (D0 to D3) was written to the end of the next period during which a new write is performed in the pixel concerned (12d, 12e).
6. Method according to Claim 5, characterized in that the memory (21, 27) of each pixel (12, 12a to 12e) is called first memory, in that each pixel (12d, 12e) comprises a second binary memory (43, 45) making it possible to pass the bit (D0 to D3) written in the first memory (21, 27) to the display component (22, 25) to activate it, in that the addressing means (13) drive the first memory (21, 27) by means of a write-enabling first signal (S1) and drive the second memory (43, 45) by means of a second signal (S2) distinct from the first signal (S1) and making it possible to activate the display component (22, 25).
7. Method according to any one of the preceding claims, characterized in that if the brightness is expressed as a number of R bits and the number of rows N is greater than 2^R-1, then the binary word has added to it a number T of bits whose values are equal to zero, corresponding to a switching off of the display components so that N is less than or equal to 2^P-1 with P = R+T.
8. Method according to any one of Claims 1 to 6, characterized in that, if the brightness is expressed as a number of S bits and the number of rows N is greater than 2^S-1, the matrix is divided into areas (11a, 11b) driven separately, each of the areas (11a, 11b) having a number of rows less than or equal to 2^S-1.
9. Method according to any one of the preceding claims, characterized in that, if the matrix comprises a number of rows U, called number of real rows, less than 2^P-1, then the distribution of the writes is configured to sequence the writes on N rows with N = 2^P-1 with U real rows and V rows called virtual rows with U+V = N, and in that, for the virtual rows, the binary word contains only bits of a value corresponding to a switching off of the display component.
10. Method according to any one of the preceding claims, characterized in that, for each given current row i, the writes on the rows i+2^j, from j=1 to j=P, of the different bits are ordered so as to minimize an error over a desired duration separating two successive writes of a same pixel (12).
11. Method according to any one of the preceding claims, characterized in that, for each given current row i, the writes on the rows i+2^j, from j=1 to j=P, of the different bits are performed for a duration less than the duration of a period equal to the duration of a frame divided by the number of rows written 2^P-1.

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