EP3079142B1 - Bildanzeigeverfahren auf matrix-bildschirm - Google Patents

Bildanzeigeverfahren auf matrix-bildschirm Download PDF

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EP3079142B1
EP3079142B1 EP16164462.0A EP16164462A EP3079142B1 EP 3079142 B1 EP3079142 B1 EP 3079142B1 EP 16164462 A EP16164462 A EP 16164462A EP 3079142 B1 EP3079142 B1 EP 3079142B1
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rows
memory
bit
bits
duration
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French (fr)
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EP3079142A1 (de
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Josep Segura Puchades
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0857—Static memory circuit, e.g. flip-flop
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0224—Details of interlacing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed

Definitions

  • the invention relates to a method for displaying images on an active matrix screen.
  • This type of screen has been widely developed in recent years, in particular for screens of the liquid crystal type known by their Anglo-Saxon abbreviation: LCD. More recently other types of screens using light-emitting diodes have been developed, in particular using organic diodes or micro diodes, known by their English abbreviation: OLED, respectively ⁇ LED.
  • Each of the pixels of an active matrix screen contains at least one transistor which acts as a switch connected to a storage component which makes it possible to store a useful signal for the duration of a frame. In the case of a liquid crystal display, these two elements are sufficient to excite the crystal. In the case of a diode screen, each pixel contains a second transistor which makes it possible to control the supply of the light-emitting diode as a function of the useful signal stored in the storage component.
  • each pixel receives, via its transistor, a voltage representative of the brightness that the pixel must display.
  • This voltage is stored in the storage component, for example a capacitor.
  • the voltage is directly applied to the electrodes surrounding the liquid crystal.
  • the voltage is applied to the second transistor configured as a follower to supply the diode in proportion to the stored voltage.
  • Analog control has several drawbacks: Voltage leaks at the capacitor may occur during the frame time. This results in a flickering phenomenon (known in the Anglo-Saxon literature under the name of "flickering") which is amplified under the influence of the temperature during the duration of the frame.
  • the voltages pass through conductors of the matrix, generally column conductors.
  • the voltage variations occurring on the column conductors can disturb the pixels of the other unaddressed lines, by capacitive coupling between the column conductors and the unaddressed storage capacitors. This results in artifacts in the displayed image.
  • the light-emitting diodes may require a high bias voltage.
  • the entire pixel must be compatible with this voltage.
  • the voltage stored in the capacitor must then be equal to the bias voltage of the diode to which the gate-source voltage of the second transistor is added.
  • Current CMOS technologies being limited to around 5V, the voltage applied to the light-emitting diode is then capped at less than 4V, which can represent a limitation of the achievable performance in terms of screen brightness.
  • the diode supply follower transistors may have non-uniform characteristics which causes a phenomenon of spatial noise in the display, because for the same control voltage for separate pixels, the polarization of the diode can then vary from one pixel to another.
  • the follower transistor works in saturated mode and it must absorb a voltage difference inversely proportional to the illumination of the light-emitting diode.
  • the power dissipated in this transistor causes significant heating, which can cause heat dissipation problems, especially when this transistor is implanted in an internal layer of the screen.
  • the control of the diodes of each of the pixels is ensured, for digital control, in all or nothing, that is to say, the diode is either connected at its maximum voltage, therefore on, or disconnected, therefore extinct.
  • the brightness of the diode is controlled by modulating the width of the pulse applied between its terminals.
  • the visual perception, because of the inertia of the eye, is the average of the sum of all the times of lighting of the diode.
  • the command is binary. It applies two possible voltage levels to the gate of the second transistor, which works in switch mode. The amplitude between these two levels must be sufficient to block or not block the second transistor, which can be achieved with relatively low voltage values.
  • the main drawback of digital control is the high operating frequency of the matrix. Indeed, to modulate the pulse width on the light-emitting diode of each pixel, it is necessary to address each pixel and therefore each line several times per frame.
  • the brightness of a pixel is coded in the form of a binary word.
  • Each bit of the binary word controls the diode for a duration proportional to the weight of the bit.
  • the light-emitting diode is controlled for a time proportional to the weight of the bit of the value to be displayed.
  • the most significant bit (MSB) drives the diode for half the duration of the frame (for example 10 ms for a frequency of 50 images / second).
  • the next bit (MSB-1) represents a quarter of this duration, and so on up to the least significant bit (LSB).
  • the diode is lit when the value of a bit is 1 and is off when the value of a bit is 0.
  • the opposite convention is of course possible.
  • the frequency F pix at which one must write in each of the pixels of a line is the frequency F line multiplied by the number of pixels per line which corresponds to the number of columns N col of the matrix:
  • F pix F line * NOT collar
  • the frequency F pix is then greater than 15GHz and for a format of 1920 columns by 1200 lines, format known as WUXGA, still for 10-bit coding, the frequency F pix is then 118GHz.
  • WUXGA format of 1920 columns by 1200 lines
  • the invention aims to overcome all or part of the problems mentioned above by proposing a digital control method making it possible to reduce the frequency of addressing of the pixels.
  • the invention relates to an image display method as defined by claim 1.
  • the dependent claims define other embodiments of the display method.
  • i represents a line pointer which increments with each write and the complete sequence of writes is carried out after 2 P -1 writes.
  • the entries made on lines i + 2 j occupy a period T i .
  • the 2 P -1 periods T i have equal durations.
  • the duration of a period T i is equal to the duration of an image frame divided by 2 P -1.
  • each of the pixels further comprises a switch making it possible to control the display component as a function of a state of the bit written in the memory.
  • the switch is actuated to control the display component as a function of the bit written in the memory for a period extending between two successive writes.
  • the method can also consist, for each of the pixels, in activating the display component after writing to the corresponding memory.
  • the writes to lines i + 2 j made from the current line i are made during a period.
  • the display component is activated for a duration extending from the end of the period during which the bit of brightness was written until the end of the next period during which a new writing is carried out in the pixel concerned.
  • each pixel is called the first memory.
  • Each pixel advantageously includes a second binary memory making it possible to transmit the bit written in the first memory to the display component to activate it.
  • the addressing means control the first memory by means of a first signal allowing the writing and control the second memory by means of a second signal distinct from the first signal and allowing the activation of the display component.
  • the matrix is divided into zones controlled separately, each of the zones having a number of lines less than or equal to 2 S -1.
  • the binary word contains only value bits corresponding to an extinction of the display component.
  • the figure 1 represents a matrix screen 10 comprising a display area 11 formed of pixels 12 organized in rows and columns, a line addressing circuit 13 and a horizontal register 14. Each pixel 12 lights up as a function of a luminosity datum expressed in the form of a binary word.
  • the line addressing circuit 13 selects the lines of the matrix one by one and for each pixel 12 of a selected line, the binary word stored in the horizontal register 14 and representing the brightness is transferred bit by bit to the pixel 12 corresponding.
  • the Figures 2a, 2b and 2c represent three examples of 12 pixel schemes that can be implemented in the screen of the figure 1 . These three examples of pixels can be implemented in a monochrome or color screen. For a color screen, we sometimes use the name "color pixel" which is actually formed by juxtaposition of several pixels each associated with a color filter. Each group of pixels receives separate brightness controls for each color.
  • the method of the invention is illustrated from pixels implemented in a monochrome screen and can be transposed to the control of a color screen by replicating the command of each of the elementary pixels forming the color pixel.
  • the figure 2a schematically represents the main components of a pixel 12a with liquid crystals.
  • the pixel 12a comprises a switch 20, a storage capacitor 21 and a liquid crystal cell 22.
  • the pixel 12a is connected to a column conductor 23 carrying the brightness data coming from the horizontal register 14.
  • the switch 20, for example formed by a transistor, makes it possible to transfer the brightness data from the column conductor 23 to the capacitor 21.
  • the pixel 12a is also connected to a line conductor 24 connected to the line addressing circuit 13.
  • the switch 20 is controlled by the line conductor 24.
  • the data stored in the capacitor 21 forms a voltage directly applied to one of the electrodes of the cell 22.
  • the data stored in the capacitor 21 is binary. One of the binary states makes cell 22 transparent and the other state makes cell 22 opaque. In the case of a backlit screen 10, the cell 22 therefore lets light pass as a function of the binary state of the data stored in the capacitor 21.
  • the cell operates in all or nothing mode as a function of the binary state of the
  • FIG 2b schematically represents the main components of a pixel 12b with light-emitting diode.
  • pixel 12b includes a light-emitting diode 25 and a second switch 26 allowing supply the diode 25 by means of a supply voltage V DD .
  • the switch 26 can also be a transistor. The switch 26 is controlled by the data stored in the capacitor 21.
  • the figure 2c represents a pixel 12c forming a variant of pixel 12b.
  • the capacitor 21 is replaced by a binary memory 27.
  • This memory makes it possible to store binary information.
  • the binary memory can be formed by a flip-flop connected to its input to the column conductor 23 and to its output to the control terminal of the switch 26.
  • the memory 27 is controlled by the line conductor 24. The modification of the information stored in memory 27 occurs during a command carried on the line conductor 24.
  • Such a memory can also be implemented for a liquid crystal pixel in replacement of the capacitor 21 of the pixel 12a.
  • the implementation of a memory can be advantageous for a matrix comprising pixels produced using CMOS technology.
  • the switches 20 and 26 as well as the memory 27 then all use the same technology.
  • the term memory will be used as well for a capacitor as for any other component or block of component making it possible to memorize binary information.
  • the capacitor 21 is assimilated to a memory.
  • the invention can be implemented for any type of pixel making it possible to emit light such as those comprising a light-emitting diode, to control the light passing through it such as those comprising a liquid crystal cell or to control the reflection of light like those implemented in a screen or a projector based on micro-mirrors. Subsequently the component of the pixel used to emit or control the light will be called the display component.
  • the brightness control of a pixel is done by means of a binary word representing a fraction of the maximum brightness of the pixel.
  • each pixel is assigned a brightness value coded in the form of a binary word.
  • the different bits of the binary word are written in the memory of the pixel and used by the display component operating all or nothing during a fraction of the duration of the image. This fraction of time depends on the weight of the bit in the binary word.
  • the most significant bit is used by the display component for substantially half of the duration of an image, the next bit for the quarter of the duration of the image and so on by dividing the fraction by two up to 'to the least significant bit.
  • Screen 10 allows for example to display 50 images per second.
  • the retinal persistence of a user makes it possible to average these fractions of duration to reconstitute the average brightness of the pixel.
  • the method of the invention consists in writing line by line the different bits of the binary words in the different memories of the corresponding pixels so as to reduce the writing frequency necessary to scan the whole matrix.
  • the invention is concerned with the sequence of writing periods in the different pixels of the matrix.
  • the entries made on lines i + 2 j occupy a period T i .
  • each of the repetitions occupies a period T i .
  • 2 P -1 periods T i are linked.
  • the different periods have the same duration. This makes it possible to respect the agreement on a frame between the value of the binary word and the sum of the activation times of the display component.
  • the different periods occupy the entire frame.
  • the duration of a period T i is equal to the duration (T frame ) of an image frame divided by 2 P -1.
  • the figure 3 visually represents on a frame the durations usable for each of the bits of the binary word coding the brightness of each of the pixels.
  • Each row of the matrix being scanned during a frame the durations between each rewrite can be expressed in number of lines representing fractions of the total duration of the frame.
  • half the rows in the matrix contain MSB-1 most significant bits
  • a quarter of the rows contain MSB-1 weight bits
  • the eighth of the rows contain MSB-2 weight bits and so on up to one line, the lowest line on the figure 3 , containing least significant bits.
  • the frequency is lowered in a ratio close to: N line / P.
  • the figures 4a to 4p represent an example of a sequence of writing periods in the memories of the different pixels of the matrix. More specifically, in the example illustrated with the figures 4a to 4p , the brightness is coded on 4 bits. It is understood that the brightness can be coded on a larger (or smaller) number of bits. So that a user perceives practically no difference in brightness between two successive levels of coding the brightness of a pixel, coding on 8 to 10 bits may be suitable.
  • the binary words coding the brightness include bits identified D0, D1, D2 and D3, ordered from the least significant bit D0 also called LSB for its English abbreviation: “Low Significant Bit” to the most significant bit D3 also called MSB for its Anglo-Saxon abbreviation: "Most Significant Bit”.
  • the most significant bit D3 is written on the first line of the matrix
  • the bit of least significant D0 is written on the second line
  • bit D1 is written on the fourth line of the matrix
  • bit D2 is written on the eighth line of the matrix.
  • Periods 3 to 15 are then linked in the same way by shifting the current line at each period by one line.
  • bit D2 is written on the eighth line.
  • the shifts made for the ninth period are done in a rotating fashion, that is to say that the shifts are incremented by one unit modulo the number of rows in the matrix. In other words, it is considered that the fifteenth line of the matrix is followed by the first line and during the ninth period the bit D2 is written on the first line of the matrix.
  • the current line is line 14.
  • the current line is line 14.
  • all the lines of the matrix were written with all the bits of the binary words representing the brightness of the different pixels of the matrix.
  • the figure 4p represents a period 16 for a new image or frame. This period 16 is similar to period 1 with new values of the binary words corresponding to the new image.
  • the figure 5 represents an example of shift register which can be used in line addressing circuit 13 to generate the line selection signals Li, signals conveyed on the line conductors 24.
  • the signal Li is formed using P flip-flops D: Di-1 to Di-P connected in series.
  • the output of the Di-P flip-flop forms the signal Li of line i and is connected to the input of the Di + 1-1 flip-flop.
  • a clock signal CLK is common to all the flip-flops D.
  • Tokens J are introduced at the input of flip-flop D1-1 with a time difference of 2 j times the duration of a period.
  • This embodiment of the line addressing circuit 13 has a drawback due to the large number of flip-flops which have to switch simultaneously. This implies significant and significant consumption peaks. The congestion on the surface of this type of register is also penalizing.
  • the figure 6 represents an alternative allowing to realize the line addressing circuit 13. This alternative is more compact and less energy consuming.
  • the counter 34 receives a clock CLK operating at the frequency of each period.
  • the shift register 33 receives a clock P times faster than the clock of the counter 34 and a Start start token at the start of each period.
  • the shift register 33 shifts the start signal to the rhythm of its clock, which allows a binary number equal to 2 P to be sent to the adder 32.
  • the adder 32 also receives the output of the counter 34.
  • the adder 32 performs the addition of the binary number and the output of the counter 34.
  • the result of the addition is transmitted to the decoder P to N, here a decoder 4 to 16 of which only 15 outputs are connected, each to a line conductor 24 of the matrix 11.
  • the rows of rank 2 j + k are addressed successively, k representing an integer incremented by one by the counter 34 to each new period.
  • the figure 7 shows an exemplary embodiment of the horizontal register 14 which comprises two shift registers 41 and 42 having as many bits as there are lines in the matrix.
  • Register 41 is used as a buffer for recording the brightness data.
  • the register 42 is used for the sequential writing of the lines addressed by the line addressing circuit 13.
  • the figures 8a and 8b represent in writing form the writing periods described above. These timing diagrams can be easily implemented using the line addressing circuits described on the figures 5 and 6 .
  • the figures 8a and 8b allow to illustrate a first embodiment of succession of the different writings within the periods.
  • a regular CLK clock makes it possible to clock the different entries of the different periods.
  • the CLK clock are represented, line by line, the writings of the different bits of the words representing the brightness of the different pixels.
  • This first embodiment has the advantage of a regular clock and of writing in the order of the bit weights.
  • the duration for each bit is not exactly a multiple of the duration of a period because of the division of the period into four phases.
  • the least significant bit D0 can be used by the display component for a period of 3 ⁇ 4 period and the bit D1 for 1 + 3 ⁇ 4 period.
  • This quantization error is due to the choice of the sequence of the different bits. This error may be acceptable for coding binary words on a larger number of bits.
  • the figure 9 represents a timing diagram of a second embodiment of the sequence of entries making it possible to reduce the error previously described.
  • the first periods are shown in this figure.
  • the bit D0 of the second line is written.
  • the bit D3 of the first line is written.
  • the bit D2 of the sixth line is written and in the fourth top t 4 , the bit D1 of the eighth line is written.
  • the least significant bit D0 can be used by the display component for a duration of 1 + 1 ⁇ 4 of period, the bit D1 for 1 + 3 ⁇ 4 of period, the bit D2 for 3 + 1 ⁇ 2 of period , bit D3 for 8 + 1 ⁇ 4 period.
  • the error on the duration remains this time less than half the duration expected for the least significant bit D0.
  • This error is typically of the same order of magnitude as that of a digital-analog converter often used in a horizontal register implemented in an analog control. It is possible to empirically test different schedules of the brightness bits in order to minimize the quantization error.
  • the figure 10 represents a timing diagram of a third embodiment of the sequence of writes also making it possible to reduce the error on the durations of use of the different bits.
  • the four phases of a period are this time generated for a duration less than that of the period whose duration is equal to the duration of an image frame divided by the number of lines written 2 P -1.
  • the four phases are for example generated during half of the period. This is achieved by doubling the clock frequency. The error is then halved.
  • the figure 11a represents a pixel 12d making it possible to implement this activation duration offset from the writing.
  • the switch 20 the storage capacitor 21, both connected to the conductors 23 and 24, the light-emitting diode 25 and the switch 26 enabling the diode 25 to be supplied by means of the supply voltage V DD .
  • the capacitor 21 does not directly control the switch 26.
  • a new switch 41 is interposed between the capacitor 21 and the control grid of the switch 26.
  • the switch 41 is controlled by a specific signal conveyed on an additional line conductor 42 distinct from the conductor 24.
  • a parasitic capacitance 43 present at the common point of the switches 26 and 41 acts as a second memory controlled by the specific signal. If necessary, it is of course possible to add a capacitor in addition to the stray capacitance.
  • the specific signal makes it possible to transmit the charges stored in the capacitor 21 to the stray capacitance 43 at the desired time.
  • the figure 11b represents a pixel 12e forming a variant to pixel 12d also making it possible to implement the offset of the activation time with respect to writing.
  • the binary memory 27 receiving information to be stored by the column conductor 23 and controlled by the row conductor 24.
  • the binary memory 27 does not directly control the switch 26.
  • a second binary memory 45 is interposed between the binary memory 27 and the control grid for the switch 26. The memory 45 is driven by the signal specific carried on the additional line conductor 42.
  • the figure 12 represents in the form of a timing diagram the signals conveyed on the line conductors 24 and 42.
  • the time axis carries the different writing periods of the matrix.
  • the chronogram of the figure 12 resumes the natural scheduling of the writing of the different brightness bits, scheduling presented on figures 8a and 8b .
  • For each of the 15 rows of the matrix two signals S1 and S2 are represented, the signal S1 conveyed by the conductor 24 and the signal S2 by the conductor 42.
  • the signals S1 conveyed by the various conductors 24 are identical to those described in l help from figure 8a .
  • the bit D3 of the first line is written.
  • This bit is conveyed by the column conductor 23 and the top t 1 forms the signal S1 conveyed by the conductor 24 of the first line.
  • the signal S2 conveyed by the conductor 42 a rising edge allows the content of the memory 27, or the voltage present in the capacitor 21 to control the switch 26.
  • the state, passing or blocked, of the switch 26 is maintained as long as a new rising edge does not appear on the conductor 42.
  • a falling edge appears on the signal S2 at the start of the first period shortly before the appearance of the bit D3 at the top t 1 .
  • bit D0 is written to top t 2 of the first period and bit D3 is written to top t 1 of the second period.
  • bit D0 is written to top t 2 of the first period and bit D3 is written to top t 1 of the second period.
  • bit D0 is written to top t 2 of the first period and bit D3 is written to top t 1 of the second period.
  • bit D0 is written to top t 2 of the first period and bit D3 is written to top t 1 of the second period.
  • bit D0 is written to top t 2 of the first period
  • bit D3 is written to top t 1 of the second period.
  • the signals S1 and S2 of the third line are temporally offset by a period with respect to the signals of the second line.
  • the bit D1 is written at the top t 3 of the first period and the bit D0 is written at the top t 2 of the third period.
  • a first rising edge occurs at the end of the first period authorizing the activation of the diode 25 by the value of the bit D1.
  • a second rising edge occurs at the end of the third period authorizing the activation of the diode 25 by the value of the bit D3.
  • the diode 25 was activated by the bit D1 during exactly two periods separating the two rising edges occurring at the end of the first period and at the end of the third period. And so on for the different bits D0 which activate the diode 25 during one period, the bits D1 during two periods, the bits D2 during four periods and the D3 bits for eight periods. More generally, the weight bits j activate the display component for 2 j periods.
  • Pixels 11d and 11e as well as the associated timing diagram shown on the figure 12 refer to a diode 25. It is understood that these variants can be implemented for any other type of display component, such as for example a liquid crystal cell or a micro mirror.
  • N 2 P - 1.
  • N 2 P - 1.
  • an eight-bit resolution requires a 255-line matrix and a 10-bit resolution requires a 1023-line matrix.
  • a first solution consists in artificially increasing the number of bits by one by systematically assigning a 0 to the new least significant bit LSB. This solution can also be implemented if one wishes to multiply the number of lines by any power of two. For example, to quadruple the number of lines, two additional bits can be added.
  • the figure 13 offers an alternative to adding a least significant bit. More specifically, the line addressing circuit is duplicated and each circuit operates separately. On the figure 13 , two line addressing circuits 13a and 13b are shown, each addressing one half of the matrix 11. More generally, the matrix 11 is divided into zones, 11a and 11b in the example shown, each of the zones having a number of lines less than or equal to 2 P -1. Here again, it is possible to multiply the number of line addressing circuits by any integer.
  • the figure 14 describes the implementation of such virtual lines.
  • Several periods are represented there in a similar way to the representation of figures 3 or 4 .
  • the total number of lines addressed 2 P - 1 is represented along a vertical axis.
  • the number of real lines U of the matrix is equal to (2 P - 1) - V, V representing the number of virtual lines remaining addressed and whose luminosity value is advantageously zero.

Claims (11)

  1. Bildanzeigeverfahren an einem Matrix-Bildschirm (10), beinhaltend mehrere Pixelzeilen (12, 12a, 12b, 12c), wobei die Zeilen geordnet sind von i=1 bis i=N, wobei N die Anzahl der Zeilen darstellt,
    wobei jeder Pixel eine Anzeigekomponente (22, 25) und einen Speicher (21, 27) beinhaltet,
    wobei der Matrix-Bildschirm (10) Adressierungsmittel (13) einer jeden der Zeilen Datenübertragungsmittel (20) an den Speicher (21, 27) eines jeden der Pixel (12) beinhaltet,
    wobei das Verfahren darin besteht, die Helligkeit eines jeden der Pixel (12) des Matrix-Bildschirms (10) mithilfe eines binären Wortes zu steuern, welches mehrere Bits (D0, D1, D2, D3) beinhaltet, welche nacheinander über die Datenübertragungsmittel (20) in den Speicher (21, 27) geschrieben werden, und durch Ansteuern der Anzeigekomponente (22, 25) entsprechend eines Zustandes des in den Speicher (21, 27) geschriebenen Bits, wobei die Bits eines jeden binären Wortes gemäß ihres Gewichts von j=1 bis j=P geordnet sind,
    wobei das Verfahren dadurch gekennzeichnet ist, dass es darin besteht, folgende Schreiboperationen während der Dauer (Ttrame) eines Bildrahmens zu verketten:
    • anhand einer laufenden Zeile i, Schreiben in den Zeilen i+2j, von j=1 bis j=P, das Gewichtsbit j eines jeden binären Wortes, welches den unterschiedlichen Pixeln der Zeilen i+2j zugeordnet ist;
    • 2P-1-maliges Wiederholen der oben genannten Schreiboperationen, unter Verschiebung eines Zeigers der laufenden Zeile um eine Einheit bei jeder Wiederholung;
    wobei der Zeiger einer Zeile wie folgt bestimmt wird: i Modulo 2P-1, sodass er zwischen 1 und 2P-1 liegt.
  2. Verfahren nach Anspruch 1, dadurch gekennzeichnet, dass, für jede laufende Zeile i, die an den Zeilen i+2j vorgenommenen Schreiboperationen eine Periode Ti belegen und dadurch, dass die 2P-1 Perioden Ti von gleicher Dauer sind.
  3. Verfahren nach Anspruch 2, dadurch gekennzeichnet, dass die Dauer einer Periode Ti gleich der Dauer (Ttrame) eines Bildrahmens geteilt durch 2P-1 ist.
  4. Verfahren nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass jeder der Pixel (12b, 12c) zudem einen Schalter (26) beinhaltet, welcher es ermöglicht, die Anzeigekomponente (25) entsprechend des Zustandes des in den Speicher (21, 27) geschriebenen Bits anzusteuern und dadurch, dass für jeden der Pixel der Schalter (26) betätigt wird, um die Anzeigekomponente (25) entsprechend des in den Speicher (21, 27) geschriebenen Bits über eine Dauer zu steuern, welche zwischen zwei aufeinanderfolgenden Schreiboperationen währt.
  5. Verfahren nach einem der Ansprüche 1 bis 3, dadurch gekennzeichnet, dass es darin besteht, für jeden der Pixel (12d, 12e) die Anzeigekomponente (22, 25) nach dem Schreiben in den entsprechenden Speicher (21, 27) zu aktivieren, dadurch, dass die Schreiboperationen an den Zeilen i+2j ab der laufenden Zeile i über eine Periode durchgeführt werden, und dadurch, dass die Anzeigekomponente (22, 25) über eine Dauer aktiviert wird, welche vom Ende der Periode, während welcher das Helligkeitsbit (D0 bis D3) geschrieben wurde, bis zum Ende der folgenden Periode währt, während welcher eine neue Schreiboperation in dem betreffenden Pixel (12d, 12e) bewerkstelligt wird.
  6. Verfahren nach Anspruch 5, dadurch gekennzeichnet, dass der Speicher (21, 27) eines jeden Pixels (12, 12a bis 12e) erster Speicher genannt wird, dadurch, dass jeder Pixel (12d, 12e) einen zweiten linearen Speicher (43, 45) beinhaltet, welcher es ermöglicht, das in den ersten Speicher (21, 27) geschriebene Bit (D0 bis D3) zur Anzeigekomponente (22, 25) passieren zu lassen, um diese zu aktivieren, dadurch, dass die Adressierungsmittel (13) den ersten Speicher (21, 27) mithilfe eines ersten Signals (S1) steuern, welches ein Schreiben ermöglicht und den zweiten Speicher (43, 45) mithilfe eines zweiten Signals (S2) steuern, welches sich von dem ersten Signal (S1) unterscheidet und die Aktivierung der Anzeigekomponente (22, 25) ermöglicht.
  7. Verfahren nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass, wenn die Helligkeit in einer Anzahl von R Bits ausgedrückt wird und die Anzahl der Zeilen N größer ist als 2R-1, man die Anzahl der Bits des binären Wortes mit T Bits erhöht, deren Werte gleich null sind, was einem Ausschalten der Anzeigekomponenten in einer Weise entspricht, dass N kleiner oder gleich 2P-1 ist, wobei P = R+T.
  8. Verfahren nach einem der Ansprüche 1 bis 6, dadurch gekennzeichnet, dass, wenn die Helligkeit in einer Anzahl von S Bits ausgedrückt wird und die Anzahl der Zeilen N größer ist als 2S-1 ist, man die Matrix in Zonen (11a, 11b) unterteilt, welche separat gesteuert werden, wobei jede der Zonen (11a, 11b) eine Anzahl an Zeilen kleiner oder gleich 2S -1 aufweist.
  9. Verfahren nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass, wenn die Matrix eine Anzahl von U Zeilen beinhaltet, genannt Anzahl tatsächlicher Zeilen, kleiner als 2P-1, die Verteilung der Schreiboperationen konfiguriert ist, um die Schreiboperationen an N Zeilen zu verketten, wobei N = 2P-1, davon U tatsächliche Zeilen und V virtuelle Zeilen genannte Zeilen, wobei U+V = N, dadurch, dass bei den virtuellen Zeilen das binäre Wort nur Bits enthält, deren Wert einer Abschaltung der Anzeigekomponente entspricht.
  10. Verfahren nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass bei jeder gegebenen laufenden Zeile i die Schreiboperationen an den Zeilen i+2j, von j=1 bis j=P, der unterschiedlichen Bits so geordnet sind, dass ein Fehler über eine gewünschte Dauer, welche zwei aufeinanderfolgende Schreiboperationen des gleichen Pixels (12) trennt, minimiert wird.
  11. Verfahren nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass bei jeder gegebenen laufenden Zeile i die Schreiboperationen an den Zeilen i+2j, von j=1 bis j=P, der unterschiedlichen Bits innerhalb einer Dauer bewerkstelligt werden, welche die Dauer einer Periode unterschreitet, welche gleich der Dauer eines Rahmens, geteilt durch die Anzahl der geschriebenen Linien 2P-1, ist.
EP16164462.0A 2015-04-10 2016-04-08 Bildanzeigeverfahren auf matrix-bildschirm Active EP3079142B1 (de)

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FR3079957B1 (fr) * 2018-04-05 2021-09-24 Commissariat Energie Atomique Dispositif et procede d'affichage d'images avec une memorisation de donnees realisee dans les pixels
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FR3125358A1 (fr) 2021-07-16 2023-01-20 Commissariat A L'energie Atomique Et Aux Energies Alternatives Dispositif d'affichage interactif et procédé de fabrication d'un tel dispositif
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US20160300525A1 (en) 2016-10-13

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