EP0815552A1 - Method for addressing a flat screen using pixel precharging, driver for carrying out the method, and use thereof in large screens - Google Patents
Method for addressing a flat screen using pixel precharging, driver for carrying out the method, and use thereof in large screensInfo
- Publication number
- EP0815552A1 EP0815552A1 EP97900254A EP97900254A EP0815552A1 EP 0815552 A1 EP0815552 A1 EP 0815552A1 EP 97900254 A EP97900254 A EP 97900254A EP 97900254 A EP97900254 A EP 97900254A EP 0815552 A1 EP0815552 A1 EP 0815552A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- voltage
- ven
- lines
- transistors
- addressing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0202—Addressing of scan or signal lines
- G09G2310/0205—Simultaneous scanning of several lines in flat panels
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0243—Details of the generation of driving signals
- G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0243—Details of the generation of driving signals
- G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0204—Compensation of DC component across the pixels in flat panels
Definitions
- the present invention relates to a method for addressing a flat screen, more particularly a liquid crystal screen using a pixel preload.
- the present invention also relates to a circuit for controlling the columns of such a screen allowing the implementation of the method as well as the application of the method to large screens.
- Direct vision or projection liquid crystal screens are generally composed of lines (selection lines) and columns (data lines) at the intersections of which are located the pixel electrodes connected through transistors to these lines.
- the gates of these transistors form the selection lines and are controlled by the peripheral control circuits, generally called “drivers" (in English) which scan the lines and make the transistors of each line pass, allowing, by the data lines connected to the other peripheral control circuits, to charge the electrodes of the pixels and modify the optical properties of the liquid crystal included between these electrodes and the counter-electrode (or reference electrode) thus allowing the formation of images on the screen.
- FIG. 1 represents the equivalent electrical diagram of a flat screen pixel addressed by row and column control circuits.
- the electrode and the counter-electrode framing the liquid crystal form a capacitor 1, the charge (most often constituted by video data) is transmitted by the column 2 through the transistor 3 controlled by the selection line 4.
- the figure 2 represents the operating timing diagrams for this pixel, Vs being the signal sent by the selection line of a row of pixels, Vc the video signal sampled on the selected row of pixels and Vp the effective load of one of these pixels.
- Vs being the signal sent by the selection line of a row of pixels
- Vc the video signal sampled on the selected row of pixels
- Vp the effective load of one of these pixels.
- the pixel voltage Vp across the liquid crystal should be equal to the column voltage Vc, ie + / - V.
- each transistor 3 when it is in the on state, has a resistance Ron which is not zero, so that the charge of the pixel has an exponential characteristic (as shown in FIG. 2) of time constant which is not zero since equal to the product Ron x C, C being the value of the capacity 1 of the pixel.
- the residual convergence error is equal to Ven + in positive frame (negative value) or Ven- in negative frame (positive value), different from the values +/- V of the charging voltage Vc .
- FIG. 3 Another known solution is shown in FIG. 3.
- a screen 5 made up of pixels 6 is addressed by a line control circuit 7 and a column control circuit 8 formed by samplers controlled by a shift register.
- the load of a sampler is none other than the distributed capacity of the column 9.
- This column must be loaded for a very short time, with the convergence problems mentioned above aggravated by the fact that the charging time is only a fraction of the time when a row is addressed 9. Indeed, during this line time, it is necessary to successively sample the video on all the columns of the screen. For this reason, the production of screens with integrated drivers has hitherto required the use of semiconductor with high mobility, such as mono or polycrystalline silicon.
- the present invention proposes a new addressing method making it possible to remedy the drawbacks mentioned above. Consequently, the subject of the present invention is a method for addressing a flat screen composed of rows and columns at the intersections of which pixels are located, characterized in that, at the start of each sampling of the video signal to be displayed on the 'screen, a voltage (Vr) greater than the useful voltage range (V) is applied to the selected pixel for a time tr, then the useful voltage is sampled for a time ts.
- Vg is the voltage on the gate of the transistor during sampling, and Vt its threshold voltage.
- Ven + Ven- is written:
- the present invention also relates to a circuit for controlling the columns of a flat screen of the type comprising samplers controlled by the outputs of a shift register, characterized in that each sampler consists of three MIS type transistors mounted in parallel so that their first electrode is connected to the video signal and their second electrode to the controlled column, which gate of the first transistor is connected to one of the outputs of the shift register and the gates of the second and third transistors being connected to two clocks chosen so that the two transistors are activated, one to perform the preload of the even lines, the other of the odd lines.
- the voltage of the clocks applied to the second and third transistors is chosen so that when a transistor is not used for preloading, it receives on its gate a negative voltage allowing later to compensate for capacitive couplings when this voltage returns to zero.
- the three transistors are identical and are transistors produced in a thin layer or TFT.
- This solution makes it possible to compensate for large capacitive couplings because the transistors used to produce samplers are large. It also makes it possible to distribute “stress” or fatigue evenly over the three transistors which are the same size, which increases the lifetime of the transistors.
- the present invention also relates to the application of the above addressing method to large screens.
- the present invention therefore relates to a method for addressing a flat screen comprising rows and columns at the intersections of which pixels are located, in which X line control circuits are each connected to Y lines, characterized in that , for a time tr, the preload of the pixels located on the lines connected to the first line control circuit is carried out, at a voltage (Vr) greater than the useful voltage range (V), then the Y lines are sampled successively and the above operation is repeated for the remaining X-1 control circuits.
- the present invention also relates to a method for addressing a flat screen comprising rows and columns at the intersections of which are located pixels in which X row control circuits are each connected to Y rows, characterized in that simultaneously preloads the first line of the X line control circuits at a voltage Vr greater than the useful voltage range (V), and said line of the X line control circuits is then sampled successively and the above operation is repeated to the Y-1 other lines of each of the X line control circuits.
- Vr the useful voltage range
- FIG. 1 already described, represents the equivalent electrical diagram of a pixel of a liquid crystal screen
- FIG. 2 already described, represents the timing diagrams of the operation of the pixel of FIG. 1,
- FIG. 3 already described, represents a known structure of a screen controlled by row and column control circuits,.
- FIG. 4 illustrates a method for addressing a liquid crystal screen according to the present invention
- FIG. 5 represents an embodiment of a known column control circuit implementing the addressing method according to the present invention
- FIG. 6 represents the timing diagram of a column control circuit according to FIG. 5,
- FIG. 7 represents a preferred embodiment of a column control circuit implementing the method according to the present invention
- FIG. 8 represents the chronogram of operation of the column control circuit of FIG. 7, and
- FIG. 9 schematically represents part of a large flat screen connected to row and column control circuits using the method of the present invention.
- a voltage Vr greater than the useful voltage is sampled on the load and the useful voltage is sampled for a time ts ( between + V and -V). Since we are trying to reach the useful voltage (between -lV and -V) from a higher voltage value, the residual convergence error is always of the same sign and equal to (Ven + -Ven -) / 2, which minimizes the error on the RMS voltage.
- Vr amorphous silicon
- Ven + ⁇ Vr-V +) exp ts ⁇ ⁇ Vg-Vt-V +)
- Vg is the voltage on the gate of the transistor during sampling, and Vt its threshold voltage.
- ⁇ Vr-Vt ⁇ Vr-V-) exp-ts ⁇ -— - * resort. - - - * doneJ v ' v ' v ⁇ ⁇ ⁇ Vg-Vt-V-) ⁇ ⁇ Vg-Vt-V + y
- ⁇ Vr -V +) ⁇ Vr -V-) exp-- ⁇ ⁇ V + -V-) or ts exp-
- Vr V + ⁇ V + -V-) ⁇ ⁇ V + -V-) ts
- FIG. 5 represents an exemplary embodiment of a column control circuit of a screen allowing the implementation of the method according to the invention.
- This control circuit is formed of transistors made of amorphous silicon.
- This control circuit 11 is preferably made up of several video inputs operating in parallel to reduce the demultiplexing frequency accordingly.
- the column control circuit comprises five video inputs DB1 to DB5 and six demultiplexing signal inputs DW1 to DW6, which makes it possible to load thirty columns 12.
- Each column 12 is controlled by a single transistor 13 which is used successively for the precharge to reach the voltage Vr during the time tr, and for convergence towards the appropriate video voltage value.
- FIG. 6 represents the chronogram of operation of the screen of FIG. 5 when it is used according to the method of the invention.
- a voltage Vr greater than the useful voltage is applied to all the columns via the signals DW1 to DW6.
- the inputs DW1 to DW6 are selected successively, as represented by DW1 to DW6, for each signal DB1 to DB5, the useful voltage is sampled during ts.
- FIG. 7 represents a preferred embodiment of a column control circuit implementing the present invention.
- each sampler consists of three transistors 16, 17 and 18 which are preferably identical and mounted in parallel.
- the first electrodes or drains of the three transistors 16, 17 and 18 receive the input video signal 14 while their second electrode or source charges the column 15 to be controlled.
- the gate of transistor 16 is connected to the output of a shift register and receives a demultiplexing signal 19 while the gates 20 and 21 of the other two transistors 17 and 18 are connected to two clocks which are described more in detail below.
- FIG. 8 represents the timing diagram of a line control circuit of the type of that of FIG. 7.
- the numerical values are given only by way of example.
- the clock signals applied to the transistors 17 and 18 are such that one of the transistors performs the preload of the odd lines while the other performs the preload of the even lines.
- the other transistor 18 receives on its gate 21 a negative pulse of for example -22V up to at the end of the line time, so as to be able to compensate the coupling of the convergence transistor at the end of the line time by means of a positive pulse on the control electrode 21.
- the gate of the transistor 16 will receive a pulse of duration Ts so to achieve convergence. Preload takes approximately twice as long (2 ⁇ sec) as convergence (0.9 ⁇ sec), so the duty cycle of the three transistors is equivalent, which distributes the stress evenly.
- the transistor In the case of a screen with a very large number of lines or a very large number of elementary pixels, the transistor is undersized to avoid having excessive coupling capacities.
- the basic diagram can be of the type of that of FIG. 1. To improve the functioning of such a screen in which either the transistor is too small to correctly charge the pixel in a conventional manner, or the number of lines is so high that there is only a very short time available for charging, one can also use an operating diagram with a preload of the type of FIG. 4.
- FIG. 9 which relates to a screen whose column control circuit is identical to the circuit of FIG. 5 and where the lines are grouped by five, each group being controlled by a line register R1, R2, R3. .. for packets of five lines, we first make a simultaneous preload on lines L1 to L5, then we sequentially sample these same lines LI to L5. Then, we make a simultaneous preload of lines L6 to L10, etc.
- This mode of operation is not compatible with usual control circuits (control of five lines at a time). It therefore requires special electronics.
- the precharge is carried out using a voltage Vr greater than the useful voltage V + / V-.
- the present invention applies in particular to flat liquid crystal screens controlled by an active matrix of thin film transistors (AMLCD), and in general to any application requiring a sampler whose relative precision is more important than absolute precision.
- AMLCD active matrix of thin film transistors
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9600259 | 1996-01-11 | ||
FR9600259A FR2743658B1 (en) | 1996-01-11 | 1996-01-11 | METHOD FOR ADDRESSING A FLAT SCREEN USING A PRECHARGE OF THE PIXELS CONTROL CIRCUIT ALLOWING THE IMPLEMENTATION OF THE METHOD AND ITS APPLICATION TO LARGE DIMENSION SCREENS |
PCT/FR1997/000039 WO1997025706A1 (en) | 1996-01-11 | 1997-01-09 | Method for addressing a flat screen using pixel precharging, driver for carrying out the method, and use thereof in large screens |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0815552A1 true EP0815552A1 (en) | 1998-01-07 |
EP0815552B1 EP0815552B1 (en) | 2003-05-28 |
Family
ID=9488036
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP97900254A Expired - Lifetime EP0815552B1 (en) | 1996-01-11 | 1997-01-09 | Method for addressing a flat screen using pixel precharging, driver for carrying out the method, and use thereof in large screens |
Country Status (7)
Country | Link |
---|---|
US (1) | US6359608B1 (en) |
EP (1) | EP0815552B1 (en) |
JP (1) | JP4547047B2 (en) |
KR (1) | KR100445675B1 (en) |
DE (1) | DE69722309T2 (en) |
FR (1) | FR2743658B1 (en) |
WO (1) | WO1997025706A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9224331B2 (en) | 2006-04-28 | 2015-12-29 | Thomson Licensing S.A.S. | Organic electroluminescent display |
Families Citing this family (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2776107A1 (en) | 1998-03-10 | 1999-09-17 | Thomson Lcd | Display control system for liquid crystal display screens |
KR100295679B1 (en) * | 1999-03-30 | 2001-07-12 | 김영환 | Column driver of thin film transistor(tft) liquid crystal display(lcd) and driving method thereof |
TW567363B (en) | 1999-05-14 | 2003-12-21 | Seiko Epson Corp | Method for driving electrooptical device, drive circuit, electrooptical device, and electronic device |
JP3570362B2 (en) * | 1999-12-10 | 2004-09-29 | セイコーエプソン株式会社 | Driving method of electro-optical device, image processing circuit, electro-optical device, and electronic apparatus |
KR20010077740A (en) * | 2000-02-08 | 2001-08-20 | 박종섭 | Power saving circuit of a display panel |
FR2805650B1 (en) * | 2000-02-25 | 2005-08-05 | Thomson Lcd | METHOD FOR COMPENSATION OF A CAPACITIVE CIRCUIT PERTURBE AND APPLICATION TO MATRIX VISUALIZATION SCREENS |
JP2001282141A (en) * | 2000-03-31 | 2001-10-12 | Sony Corp | Photon control device |
GB0014074D0 (en) * | 2000-06-10 | 2000-08-02 | Koninkl Philips Electronics Nv | Active matrix array devices |
JP3723747B2 (en) * | 2000-06-16 | 2005-12-07 | 松下電器産業株式会社 | Display device and driving method thereof |
KR100685942B1 (en) * | 2000-08-30 | 2007-02-23 | 엘지.필립스 엘시디 주식회사 | Liquid crystal display device and method for driving the same |
JP4330059B2 (en) | 2000-11-10 | 2009-09-09 | カシオ計算機株式会社 | Liquid crystal display device and drive control method thereof |
US6850218B2 (en) * | 2000-12-18 | 2005-02-01 | Brillian Corporation | Frame prewriting in a liquid crystal display |
KR100365500B1 (en) * | 2000-12-20 | 2002-12-18 | 엘지.필립스 엘시디 주식회사 | Method of Driving Liquid Crystal Panel in Dot Inversion and Apparatus thereof |
CN1302313C (en) * | 2001-02-05 | 2007-02-28 | 国际商业机器公司 | Liquid crystal display device |
US20030085856A1 (en) * | 2001-11-02 | 2003-05-08 | Klein Terence R | System and method for minimizing image degradation in LCD microdisplays |
JP4007239B2 (en) * | 2003-04-08 | 2007-11-14 | ソニー株式会社 | Display device |
WO2005004490A2 (en) * | 2003-06-13 | 2005-01-13 | Lumexis Corporation | Remote interface optical network |
KR100578911B1 (en) * | 2003-11-26 | 2006-05-11 | 삼성에스디아이 주식회사 | Current demultiplexing device and current programming display device using the same |
KR100578913B1 (en) * | 2003-11-27 | 2006-05-11 | 삼성에스디아이 주식회사 | Display device using demultiplexer and driving method thereof |
KR100578914B1 (en) * | 2003-11-27 | 2006-05-11 | 삼성에스디아이 주식회사 | Display device using demultiplexer |
KR100589381B1 (en) * | 2003-11-27 | 2006-06-14 | 삼성에스디아이 주식회사 | Display device using demultiplexer and driving method thereof |
JP2005195810A (en) * | 2004-01-06 | 2005-07-21 | Nec Electronics Corp | Capacitive load drive circuit and display panel drive circuit |
CN100410995C (en) * | 2004-01-17 | 2008-08-13 | 奇美电子股份有限公司 | Asymmetrical liquid crystal screen driving method |
JP4480442B2 (en) * | 2004-03-31 | 2010-06-16 | Nec液晶テクノロジー株式会社 | Manufacturing method of liquid crystal display device |
JP4285314B2 (en) * | 2004-04-22 | 2009-06-24 | セイコーエプソン株式会社 | Electro-optic device |
KR100600350B1 (en) * | 2004-05-15 | 2006-07-14 | 삼성에스디아이 주식회사 | demultiplexer and Organic electroluminescent display using thereof |
KR100622217B1 (en) * | 2004-05-25 | 2006-09-08 | 삼성에스디아이 주식회사 | Organic electroluminscent display and demultiplexer |
FR2873227B1 (en) * | 2004-07-13 | 2006-09-15 | Thales Sa | MATRICIAL DISPLAY |
WO2006038187A1 (en) * | 2004-10-06 | 2006-04-13 | Koninklijke Philips Electronics N.V. | Arbitrary addressable row decoder with start/stop resetting of pixels |
KR100685817B1 (en) * | 2005-02-18 | 2007-02-22 | 삼성에스디아이 주식회사 | Field Sequential Liquid Crystal Display |
FR2889615B1 (en) * | 2005-08-02 | 2008-06-06 | Thales Sa | ACTIVE MATRIX FOR A LIQUID CRYSTAL DISPLAY DEVICE |
FR2889763B1 (en) * | 2005-08-12 | 2007-09-21 | Thales Sa | MATRIX DISPLAY WITH SEQUENTIAL COLOR DISPLAY AND ADDRESSING METHOD |
WO2007035739A2 (en) * | 2005-09-19 | 2007-03-29 | Lumexis, Inc. | Fiber-to-the-seat in-flight entertainment system |
FR2894369B1 (en) * | 2005-12-07 | 2008-07-18 | Thales Sa | IMPROVED ADDRESSING METHOD FOR A LIQUID CRYSTAL MATRIX DISPLAY |
FR2894370B1 (en) | 2005-12-07 | 2008-06-06 | Thales Sa | SEQUENTIAL MATRIX DISPLAY WITH LIQUID CRYSTAL COLOR |
WO2008033870A2 (en) * | 2006-09-11 | 2008-03-20 | Lumexis Corporation | Fiber-to-the-seat (ftts) fiber distribution system |
FR2913818B1 (en) * | 2007-03-16 | 2009-04-17 | Thales Sa | ACTIVE MATRIX OF AN ORGANIC ELECTROLUMINESCENT SCREEN |
TWI334126B (en) * | 2007-07-17 | 2010-12-01 | Au Optronics Corp | Voltage adjusting circuit, method, and display apparatus having the same |
FR2934919B1 (en) * | 2008-08-08 | 2012-08-17 | Thales Sa | FIELD EFFECT TRANSISTOR SHIFT REGISTER |
WO2011017233A1 (en) | 2009-08-06 | 2011-02-10 | Lumexis Corporation | Serial networking fiber-to-the-seat inflight entertainment system |
WO2011020071A1 (en) * | 2009-08-14 | 2011-02-17 | Lumexis Corp. | Video display unit docking assembly for fiber-to-the-screen inflight entertainment system |
WO2011022708A1 (en) | 2009-08-20 | 2011-02-24 | Lumexis Corp. | Serial networking fiber optic inflight entertainment system network configuration |
EP2486728A4 (en) * | 2009-10-05 | 2015-10-21 | Lumexis Corp | Inflight communication system |
JP5664034B2 (en) | 2010-09-03 | 2015-02-04 | セイコーエプソン株式会社 | Electro-optical device and electronic apparatus |
KR102061595B1 (en) | 2013-05-28 | 2020-01-03 | 삼성디스플레이 주식회사 | Liquid crystal display apparatus and driving method thereof |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2962338B2 (en) * | 1992-03-18 | 1999-10-12 | 日本電気株式会社 | Data output circuit for realizing driving method of liquid crystal display device |
US5426447A (en) * | 1992-11-04 | 1995-06-20 | Yuen Foong Yu H.K. Co., Ltd. | Data driving circuit for LCD display |
US5510807A (en) * | 1993-01-05 | 1996-04-23 | Yuen Foong Yu H.K. Co., Ltd. | Data driver circuit and associated method for use with scanned LCD video display |
EP0622772B1 (en) * | 1993-04-30 | 1998-06-24 | International Business Machines Corporation | Method and apparatus for eliminating crosstalk in active matrix liquid crystal displays |
JPH06337400A (en) * | 1993-05-31 | 1994-12-06 | Sharp Corp | Matrix type display device and method for driving it |
JP3482683B2 (en) * | 1994-04-22 | 2003-12-22 | ソニー株式会社 | Active matrix display device and driving method thereof |
JP3451717B2 (en) * | 1994-04-22 | 2003-09-29 | ソニー株式会社 | Active matrix display device and driving method thereof |
JPH07319429A (en) * | 1994-05-30 | 1995-12-08 | Matsushita Electric Ind Co Ltd | Method for driving liquid crystal image display device and liquid crystal image display device |
JP3424387B2 (en) * | 1995-04-11 | 2003-07-07 | ソニー株式会社 | Active matrix display device |
JP3110980B2 (en) * | 1995-07-18 | 2000-11-20 | インターナショナル・ビジネス・マシーンズ・コーポレ−ション | Driving device and method for liquid crystal display device |
-
1996
- 1996-01-11 FR FR9600259A patent/FR2743658B1/en not_active Expired - Fee Related
-
1997
- 1997-01-09 DE DE69722309T patent/DE69722309T2/en not_active Expired - Lifetime
- 1997-01-09 WO PCT/FR1997/000039 patent/WO1997025706A1/en active IP Right Grant
- 1997-01-09 KR KR1019970706366A patent/KR100445675B1/en not_active IP Right Cessation
- 1997-01-09 US US08/913,703 patent/US6359608B1/en not_active Expired - Lifetime
- 1997-01-09 JP JP52492497A patent/JP4547047B2/en not_active Expired - Fee Related
- 1997-01-09 EP EP97900254A patent/EP0815552B1/en not_active Expired - Lifetime
Non-Patent Citations (1)
Title |
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See references of WO9725706A1 * |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9224331B2 (en) | 2006-04-28 | 2015-12-29 | Thomson Licensing S.A.S. | Organic electroluminescent display |
Also Published As
Publication number | Publication date |
---|---|
WO1997025706A1 (en) | 1997-07-17 |
KR19980702958A (en) | 1998-09-05 |
FR2743658B1 (en) | 1998-02-13 |
FR2743658A1 (en) | 1997-07-18 |
JPH11502325A (en) | 1999-02-23 |
JP4547047B2 (en) | 2010-09-22 |
DE69722309D1 (en) | 2003-07-03 |
DE69722309T2 (en) | 2004-04-08 |
US6359608B1 (en) | 2002-03-19 |
EP0815552B1 (en) | 2003-05-28 |
KR100445675B1 (en) | 2004-12-08 |
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