EP0814396B1 - Circuit pour générer une tension de référence - Google Patents

Circuit pour générer une tension de référence Download PDF

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Publication number
EP0814396B1
EP0814396B1 EP97109351A EP97109351A EP0814396B1 EP 0814396 B1 EP0814396 B1 EP 0814396B1 EP 97109351 A EP97109351 A EP 97109351A EP 97109351 A EP97109351 A EP 97109351A EP 0814396 B1 EP0814396 B1 EP 0814396B1
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EP
European Patent Office
Prior art keywords
transistor
whose
base
collector
emitter
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP97109351A
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German (de)
English (en)
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EP0814396A3 (fr
EP0814396A2 (fr
Inventor
Stephan Weber
Udo Matter
Stefan Heinen
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Infineon Technologies AG
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Siemens AG
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Publication of EP0814396A3 publication Critical patent/EP0814396A3/fr
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/265—Current mirrors using bipolar transistors only
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/22—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only
    • G05F3/222—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only with compensation for device parameters, e.g. Early effect, gain, manufacturing process, or external variations, e.g. temperature, loading, supply voltage

Definitions

  • the invention relates to a circuit arrangement for generation a reference potential with a first transistor, the Emitter is connected to a reference potential and its Base and collector are interconnected with one another second transistor, the base of which is connected to the base of the first Transistor is connected to a first resistor, the between the collector of the first transistor and an output terminal switched to tap the reference potential is, with a second resistor that is between the collector of the second transistor and the output terminal is, with a third resistor connected between the emitter of the second transistor and the reference potential is, with a third transistor, the base of which is connected to the collector of the second transistor and its emitter with the reference potential is connected to a fourth transistor, its collector with the supply potential, its emitter with the output connector and its base with the collector of the third transistor is connected, between base and collector of the fourth transistor a first current source is switched.
  • Such a bandgap reference voltage source Circuit arrangement is for example from Paul R. Gray, Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, Second Edition 1984, pages 293 to 296 is used in a variety of integrated circuits Supply of other circuit blocks with a temperature independent Reference potential and / or several reference currents used. In the future, it will also become increasingly important that the integrated circuits especially for the Use in battery-operated devices as independently as possible work from the supply voltage. With everyone with constant Base-emitter voltage or constant base current driven, real transistor fluctuates due to the early effect the collector current as a function of the collector-emitter voltage, which in turn often directly with the supply voltage is linked. The early effect is for example with Paul R. Gray, Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, Second Edition 1984, pages 17 to 19 described. This problem is also critical therefore, because fast, modern transistors in terms of Early effects tend to have poor properties.
  • the object of the invention is to provide a circuit arrangement for Specify generation of a reference potential at which the Early effect is largely compensated for.
  • the advantage of the invention is that early compensation with low circuit complexity is achieved.
  • the first Current source a second current source is connected in parallel, which a compensation current to compensate for the current fluctuations generated the first power source.
  • the front second current source generated equalization current the difference of a first multiplied by a factor Early-dependent current and a second less early-dependent one Is current.
  • the first current source can be a fifth transistor are formed, whose emitter has a fifth resistor is connected to the supply potential whose Collector connected to the base of the fourth transistor and is based on a sixth resistance with the Supply potential is coupled. Furthermore, control means provided the one above the sixth resistor voltage dependent on the potential at the connection produce.
  • One embodiment of the invention includes control means a sixth transistor, the base of which is connected to the base of the fifth transistor and its emitter with interposition a seventh resistor with the supply potential is connected and to a seventh transistor whose base to the output terminal, whose emitter has an eighth resistor to the reference potential and its collector to the Collector of the sixth transistor is connected.
  • control means contain an eighth transistor, whose collector-emitter path is the collector-emitter path of the seventh transistor is connected in parallel and the basis of which is on the one hand via a ninth resistance with the Supply potential and secondly via a diode path and a tenth resistor in series with the reference potential is connected, as well as a ninth transistor, whose collector with the supply potential, whose emitter has a third current source with the reference potential and its base is coupled to the collector of the seventh transistor. Finally, there is a tenth transistor in the control means provided its emitter with the base of the fifth Transistor whose collector is connected to the reference potential and whose base is connected to the emitter of the ninth transistor is.
  • the third current source formed by an eleventh transistor, whose emitter over an eleventh resistor with the reference potential whose collector with the emitter of the ninth transistor and its base is connected to the base of the eighth transistor.
  • Partial current sources to form the first early-dependent Current and the second less early dependent current, on the one hand with the supply potential and on the other hand with the input circuit or the output circuit of a current mirror are connected, as well as one with the other two partial current sources coupled third partial current source, that of the first Current source is connected in parallel, can be provided.
  • junction of the current mirror and the output circuit second current source can be connected to the input of a current amplifier stage be connected, the output of which in turn is connected to the base of the ninth transistor is coupled.
  • the current amplifier stage are formed by a second current mirror.
  • the partial current sources can through the output branches Electricity bank, the input branch of which is given by the sixth Resistance is realized.
  • the input branch is given by a twelfth resistance.
  • the twelfth resistance the base-emitter path of a twelfth Transistors and a thirteenth resistor in series connected in parallel.
  • the base of a thirteenth Transistor, whose collector is connected to the supply potential and the collector of a fourteenth transistor, its base with the base of the seventh transistor and its emitter through a fourteenth resistance with the Reference potential is connected to the collector of the twelfth transistor coupled.
  • the base of a fifteenth Transistor whose collector is connected to the reference potential and whose emitter is connected to the base of the twelfth transistor is connected to the emitter of a thirteenth transistor.
  • the base of a sixteenth transistor, the Collector with the base of the fifteenth transistor and its Emitter across a fifteenth resistor with the reference potential is connected to the base of the eighth Transistor coupled.
  • npn transistor T1 provided, whose emitter with the reference potential M is connected and its base and collector together interconnected and via a common resistor R1 an output terminal U coupled to a reference potential are.
  • the base and collector of transistor T1 is the base of an npn transistor T2, whose Emitter via a resistor R3 with the reference potential M and its collector through a resistor R2 with the output termination U is coupled.
  • the emitter is also a npn transistor T4 connected, the collector with a supply potential V is connected.
  • the basis of the Transistor T4 is connected to the collector of an NPN transistor T3 connected, whose emitter to the reference potential M and Base is connected to the collector of transistor T2.
  • the base of transistor T4 is also a Current source circuit connected to the supply potential V.
  • the current source circuit has a pnp transistor T5 whose emitter is connected via a resistor R5 the supply potential V and its collector with the base of transistor T4 or the collector of transistor T3 connected is.
  • the base of transistor T5 is with the base a pnp transistor T6, whose emitter is connected via a Resistor R6 coupled to the supply potential V. is, the emitter via a resistor R6 with the supply potential V is coupled.
  • the collector of the transistor T6 is also with the collector of an NPN transistor T7 connected, the emitter via a resistor R4 to the Reference potential M is connected and its base with the Output terminal U is connected.
  • transistor T7 the collector-emitter path of an npn transistor T8 connected in parallel.
  • the base of the transistor T8 is connected with a resistor R8 connected to the supply potential V.
  • the base of transistor T8 is also connected to the input branch connected to a current mirror.
  • the input branch is through an NPN transistor T11 is formed, the base and collector interconnected as well as with the base of transistor T8 are and their emitters with the interposition of a resistor R10 is connected to the reference potential M.
  • the bases of transistors T7 and T8 are also one Resistor R7 coupled together.
  • the output branch of the current mirror is through an NPN transistor T12 formed, the base of which is connected to the base of the transistor T11 is connected and its emitter with interposition a resistor R9 connected to the reference potential M. is.
  • the collector of transistor T12 is off the base of a pnp transistor T10, the collector of which Reference potential M and its emitter with the bases of the transistors T5 and T6 is connected as well as to the emitter of one npn transistor T9, whose collector with the supply potential V and its base with the collector of the transistor T6 is connected. After all, there is resistance R11 between the bases of transistors T5 and T6 on the one hand and the supply potential V on the other hand switched.
  • the collector With the collector of transistor T6, the collector is one pnp transistor T13 connected whose emitter via a resistor R12 is connected to the supply potential V. its base with the base and collector of a pnp transistor T14, with the collector of a pnp transistor T15 as well coupled to the collector of an NPN transistor T18 is.
  • the emitters of the two transistors T14 and T15 are via a resistor R13 or R14 to the supply potential V connected.
  • the emitter of the transistor T18 is connected to the reference potential M via a resistor R17 connected.
  • the transistor T15 forms like pnp transistors T16 and T17, whose emitters each have a resistor R15 or R16 connected to the supply potential V.
  • the embodiment of Figure 2 changed so that the bases of transistors T15, T16 and T17 do not have the Resistor R11 but via a resistor R17 with the supply potential V are connected.
  • the bases of the transistors T15, T16, T17 are also with the emitter of a pnp transistor T18 and with the base of a pnp transistor T20 interconnected.
  • the collector of transistor T18 is on the reference potential M is connected.
  • the collector of the transistor T20 is based on the one hand with an NPN transistor T19 connected, the collector of the supply potential V is connected, and on the other hand with the collector one Transistor T21 connected, the base of which is connected to terminal U and its emitter with the interposition of a resistor R19 is coupled to the reference potential M.
  • the basis of the Transistor T18 and the emitter of transistor T19 are together connected to the collector of an npn transistor T22, its emitter via a resistor R20 with the reference potential M is connected and its base with the bases of the Transistors T11 and T12 is coupled.
  • a pnp transistor T23 is provided, the base of which is connected to the base of transistor T5 and its Emitter via a resistor R21 to the supply potential V is connected.
  • the collector is with an output connection I interconnected, at which the reference current can be tapped is.
  • the separate optimization of the operating voltage suppression both with regard to the band gap reference potential at the output U and the reference output current at connection I can separately by adjusting the emitter area of the Transistor T14 in relation to the emitter area of the transistor T13 and by adjusting resistors R17 and R18.
  • a smaller resistance value of the two resistors R17 and R18 causes weaker current feedback, so that the early voltage correction is correspondingly stronger. It a drop in the output current, for example be set if it is necessary to set an advance.
  • the output current through the Transistor T5 formed in conjunction with the resistor R5 Current source superimposes a compensation current by the output current which through transistor T17 in conjunction with the Resistor R16 formed current source also in the base of the transistor T4 is fed and the input circuit of the Transistors T15 influenced by transistors T9 to T14 becomes.
  • the output current given by the collector current of transistor T5 on The main reason for this is the early voltage dependency the collector currents of the transistors T5 up to T12. This dependence takes effect via transistor T4 directly to the output connection U.
  • the one superimposed Compensation current is now the difference of a first Early-dependent current of the current source with the transistor T16 in conjunction with resistor R15 and one less Early-dependent current of the current source with the transistor T15 formed in connection with the resistor R14 and with a Multiplied by the current ratio of the Transistors T13 and T14 and the ratio of the resistors R17 and R18 is given.
  • the dimensioning is like this chosen that a linear dependence of the compensation current is achieved and thus overall independence is reached by the supply voltage.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)
  • Amplifiers (AREA)

Claims (10)

  1. Circuit pour générer une tension de référence,
    avec un premier transistor (T1) dont l'émetteur est relié à un potentiel de référence (M) et dont la base et le collecteur sont interconnectés,
    avec un deuxième transistor (T2) dont la base est reliée à la base du premier transistor (T1),
    avec une première résistance (R1) montée entre le collecteur du premier transistor (T1) et une borne de sortie (U) pour prélever la tension de référence,
    avec une deuxième résistance (R2) montée entre le collecteur du deuxième transistor (T2) et la borne de sortie (U),
    avec une troisième résistance (R3) montée entre l'émetteur du deuxième transistor (T2) et le potentiel de référence (M),
    avec un troisième transistor (T3) dont la base est reliée au collecteur du deuxième transistor (T2) et dont l'émetteur est relié au potentiel de référence (M),
    avec un quatrième transistor (T4) dont le collecteur est relié à la tension d'alimentation (V), dont l'émetteur est relié à la borne de sortie (U) et dont la base est reliée au collecteur du troisième transistor (T3), entre la base et le collecteur du quatrième transistor (T4) étant montée une première source de courant (R5, T5),
       caractérisé par une deuxième source de courant (T17, R16) montée en parallèle avec la première source de courant (R5, T5), qui génère un courant de compensation pour compenser les fluctuations de courant de la première source de courant (R5, T5).
  2. Circuit selon la revendication 1, caractérisé en ce que le courant de compensation généré par la deuxième source de courant (T17, R16) est égal à la différence multipliée par un facteur entre un premier courant dépendant de l'effet Early et un deuxième courant moins dépendant de l'effet Early.
  3. Circuit selon la revendication 1 ou 2, caractérisé en ce que la première source de courant est formée par un cinquième transistor (T5) dont l'émetteur est connecté via une cinquième résistance (R5) à la tension d'alimentation (V), dont le collecteur est relié à la base du quatrième transistor (T4) et dont la base est couplée via une sixième résistance (R11) à la tension d'alimentation (V), et en ce que des moyens d'amorçage sont prévus, qui génèrent via la sixième résistance (R11) une tension dépendante de la tension appliquée à la borne (U).
  4. Circuit selon la revendication 3, caractérisé par des moyens d'amorçage avec un sixième transistor (T6) dont la base est reliée à la base du cinquième transistor (T5) et dont l'émetteur est relié par intercalage d'une septième résistance (R6) à la tension d'alimentation (V),
    avec un septième transistor (T7) dont la base est connectée à la borne de sortie (U), dont l'émetteur est connecté via une huitième résistance (R4) au potentiel de référence (M) et dont le collecteur est connecté au collecteur du sixième transistor (T6),
    avec un huitième transistor (T8) dont le trajet collecteur-émetteur est monté en parallèle avec le trajet collecteur-émetteur du septième transistor (T7) et dont la base, d'une part, est reliée via une neuvième résistance (R8) à la tension d'alimentation (V) et, d'autre part, montée en série via un trajet de diode (Tl1) et une dixième résistance (R10) avec le potentiel de référence (M),
    avec un neuvième transistor (T9) dont le collecteur est couplé à la tension d'alimentation (V), dont l'émetteur est couplé via une troisième source de courant (T12, R9) au potentiel de référence (M) et dont la base est couplée au collecteur du septième transistor (T7), et
    avec un dixième transistor (T10) dont l'émetteur est connecté à la base du cinquième transistor (T5), dont le collecteur est connecté au potentiel de référence (M) et dont la base est connectée à l'émetteur du neuvième transistor (T9).
  5. Circuit selon la revendication 4, caractérisé en ce que la troisième source de courant est formée par un onzième transistor (T12) dont l'émetteur est relié via une onzième résistance (R9) au potentiel de référence (M), dont le collecteur est relié à l'émetteur du neuvième transistor (T9) et dont la base est reliée à la base du huitième transistor (T8).
  6. Circuit selon l'une quelconque des revendications 1 à 4, caractérisé en ce que la deuxième source de courant comporte deux sources de courant partielles (R14, R15, T15, T16) couplées entre elles pour générer le premier courant dépendant de l'effet Early et le deuxième courant moins dépendant de l'effet Early, qui sont reliées d'une part à la tension d'alimentation (V) et d'autre part respectivement au circuit d'entrée et au circuit de sortie d'un miroir de courant (T18a, T19a, R17a, R18a), ainsi qu'une troisième source de courant (T17, R16) couplée, côté entrée, aux deux autres sources de courant partielles, qui est montée en parallèle avec la première source de courant (T5, R5).
  7. Circuit selon la revendication 6, caractérisé en ce que le point nodal du circuit de sortie du miroir de courant (T18a, T19a, R17a, R18a) et de la deuxième source de courant (R14, R15, T15, T16) est relié à l'entrée d'un étage d'amplification de courant (T13, T14, R12, R13) dont la sortie est couplée à la base du neuvième transistor (T9).
  8. Circuit selon la revendication 6 ou 7, caractérisé en ce que l'étage d'amplification de courant est formé par un deuxième miroir de courant (T13, T14, R12, R13).
  9. Circuit selon l'une quelconque des revendications 6 à 8, caractérisé en ce que les sources de courant partielles sont formées par les branches de sortie d'un banc de courant dont la branche d'entrée est donnée par la sixième résistance (R11).
  10. Circuit selon l'une quelconque des revendications 6 à 8, caractérisé en ce que les sources de courant partielles sont formées par les branches de sortie d'un banc de courant dont la branche d'entrée est donnée par une douzième résistance (R17),
    en ce que la douzième résistance (R17) est montée en parallèle avec le trajet base-émetteur d'un douzième transistor (T20) monté en série avec une treizième résistance (R18),
    en ce que la base d'un treizième transistor (T19) dont le collecteur est connecté à la tension d'alimentation (V), et le collecteur d'un quatorzième transistor (T21) dont la base est reliée à la base du septième transistor (T7) et dont l'émetteur est relié via une quatorzième résistance (R19) au potentiel de référence (M), sont couplés au collecteur du douzième transistor (T20),
    en ce que la base d'un quinzième transistor (T18) dont le collecteur est relié au potentiel de référence (M) et dont l'émetteur est relié à la base du douzième transistor (T20), est connecté à l'émetteur du treizième transistor (T19), et en ce que la base d'un seizième transistor (T22) dont le collecteur est relié à la base du quinzième transistor (T18) et dont l'émetteur est relié via une quinzième résistance (R20) au potentiel de référence (M), est couplée à la base du huitième transistor (T8).
EP97109351A 1996-06-20 1997-06-09 Circuit pour générer une tension de référence Expired - Lifetime EP0814396B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19624676 1996-06-20
DE19624676A DE19624676C1 (de) 1996-06-20 1996-06-20 Schaltungsanordnung zur Erzeugung eines Referenzpotentials

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EP0814396A2 EP0814396A2 (fr) 1997-12-29
EP0814396A3 EP0814396A3 (fr) 1998-12-09
EP0814396B1 true EP0814396B1 (fr) 2000-09-27

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EP97109351A Expired - Lifetime EP0814396B1 (fr) 1996-06-20 1997-06-09 Circuit pour générer une tension de référence

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US (1) US5969566A (fr)
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DE (2) DE19624676C1 (fr)

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EP1184769A3 (fr) * 2000-08-09 2004-09-22 Mitsubishi Denki Kabushiki Kaisha Générateur de tension, circuit de sortie de détection d'erreurs, et générateur de courant
JP4212036B2 (ja) * 2003-06-19 2009-01-21 ローム株式会社 定電圧発生器
EP1501001A1 (fr) * 2003-07-22 2005-01-26 STMicroelectronics Limited Circuit de polarisation
JP4721726B2 (ja) * 2005-02-25 2011-07-13 富士通セミコンダクター株式会社 差動増幅器
US7893754B1 (en) * 2009-10-02 2011-02-22 Power Integrations, Inc. Temperature independent reference circuit
US8634218B2 (en) 2009-10-06 2014-01-21 Power Integrations, Inc. Monolithic AC/DC converter for generating DC supply voltage
US8310845B2 (en) 2010-02-10 2012-11-13 Power Integrations, Inc. Power supply circuit with a control terminal for different functional modes of operation
US9455621B2 (en) 2013-08-28 2016-09-27 Power Integrations, Inc. Controller IC with zero-crossing detector and capacitor discharge switching element
US9667154B2 (en) 2015-09-18 2017-05-30 Power Integrations, Inc. Demand-controlled, low standby power linear shunt regulator
US9602009B1 (en) 2015-12-08 2017-03-21 Power Integrations, Inc. Low voltage, closed loop controlled energy storage circuit
US9629218B1 (en) 2015-12-28 2017-04-18 Power Integrations, Inc. Thermal protection for LED bleeder in fault condition

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JPH0811203B2 (ja) * 1986-05-13 1996-02-07 株式会社スギノマシン 超高圧液体噴射装置
JP2575702B2 (ja) * 1987-05-09 1997-01-29 富士通 株式会社 シンセサイザ・チュ−ナ
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DE19621110C1 (de) * 1996-05-24 1997-06-12 Siemens Ag Ein-/Ausschaltbare Schaltungsanordnung zur Erzeugung eines Referenzpotentials

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Publication number Publication date
EP0814396A3 (fr) 1998-12-09
DE19624676C1 (de) 1997-10-02
EP0814396A2 (fr) 1997-12-29
DE59702395D1 (de) 2000-11-02
US5969566A (en) 1999-10-19

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