EP0809169B1 - Circuit pour générer une tension de référence pouvant être validée ou inhibée - Google Patents

Circuit pour générer une tension de référence pouvant être validée ou inhibée Download PDF

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Publication number
EP0809169B1
EP0809169B1 EP97107599A EP97107599A EP0809169B1 EP 0809169 B1 EP0809169 B1 EP 0809169B1 EP 97107599 A EP97107599 A EP 97107599A EP 97107599 A EP97107599 A EP 97107599A EP 0809169 B1 EP0809169 B1 EP 0809169B1
Authority
EP
European Patent Office
Prior art keywords
transistor
collector
base
whose
emitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP97107599A
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German (de)
English (en)
Other versions
EP0809169A3 (fr
EP0809169A2 (fr
Inventor
Stephan Weber
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
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Siemens AG
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Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0809169A2 publication Critical patent/EP0809169A2/fr
Publication of EP0809169A3 publication Critical patent/EP0809169A3/fr
Application granted granted Critical
Publication of EP0809169B1 publication Critical patent/EP0809169B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities

Definitions

  • the invention relates to a circuit arrangement that can be switched on / off to generate a reference potential with a first transistor, whose emitter has a reference potential is connected and its base and collector are interconnected are, with a second transistor whose base with the base of the first transistor is connected to a first resistor that is between the collector of the first Transistor and an output terminal for tapping the reference potential is connected, with a second resistor, the between the collector of the second transistor and the output terminal is connected, with a third resistor, the between the emitter of the second transistor and the reference potential is switched, with a third transistor, its base with the collector of the second transistor and its emitter connected to the reference potential is, and with a controlled power source that is between a Supply potential and the output connection is switched and the input side with the collector of the third transistor is coupled.
  • Circuit arrangement is for example from Paul R. Gray, Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, Second Edition, John Wiley and Sons, 1984, pages 293-296.
  • the object of the invention is a circuit arrangement that can be switched on / off to generate a reference potential, which does not have these disadvantages.
  • one Circuit arrangement of the aforementioned type of collector-emitter path the third transistor the collector-emitter path a fifth transistor connected in parallel and the base of the fifth transistor is driven by a switching signal.
  • the controlled Current source a fourth transistor whose collector with the supply potential, whose emitter with the output terminal and its base with the collector of the third Transistor is connected. Between base and collector of the fourth transistor, a further current source is connected. Furthermore, the further current source can have a sixth Have transistor whose base is connected to the output terminal and its emitter with the interposition of a fourth Resistance is connected to the reference potential.
  • a seventh transistor whose emitter is under Interposition of a fifth resistor with the supply potential is connected, its collector to the base of the fourth transistor is connected and its base with the collector of the sixth transistor is coupled, and an eighth transistor, its base and collector together and coupled to the collector of the sixth transistor are and its emitter with the interposition of a sixth Resistance is connected to the supply potential, intended.
  • the collector-emitter path of the sixth Transistor the collector-emitter path of a ninth Transistor is connected in parallel and that the base of the ninth transistor driven by the switching signal becomes.
  • a seventh resistor can be switched. Further can the switching signal via an eighth resistance of the Base of the ninth transistor are supplied.
  • a further development of the invention contains a tenth transistor, whose emitter with the bases of seventh and eighth Transistor and its collector connected to the reference potential is.
  • An eleventh transistor is also provided, its collector with the supply potential, its base with the collector of the eighth transistor and its emitter is connected to the base of the tenth transistor.
  • the base the ninth transistor is connected to the input branch a current mirror coupled, the output branch with the Base of the tenth transistor is coupled.
  • an npn transistor T1 is provided, whose emitter is connected to the reference potential M and its base and collector interconnected and over a common resistor R1 with a reference potential leading output terminal U are coupled.
  • the base and collector of transistor T1 is the base of an NPN transistor T2 connected, the emitter via a resistor R3 with the reference potential M and its collector coupled to the output terminal U via a resistor R2 is.
  • the emitter is also a npn transistor T4 connected, the collector with a supply potential V is connected.
  • the basis of the Transistor T4 is connected to the collector of an NPN transistor T3 connected, whose emitter to the reference potential M and Base is connected to the collector of transistor T2.
  • the base of transistor T4 is also a Current source circuit connected to the supply potential V.
  • the current source circuit has a pnp transistor T7 whose emitter is connected via a resistor R5 the supply potential V and its collector with the base of transistor T4 or the collector of transistor T3 connected is.
  • the base of transistor T7 is with the base of a pnp transistor T8, whose emitter is connected via a Resistor R6 coupled to the supply potential V. is.
  • the collector of transistor T8 is also with connected to the collector of an npn transistor T6, the Emitter connected to the reference potential M via a resistor R4 is and its base with the output terminal U connected is.
  • an output connection I which carries a reference current. Is to the output terminal I with the collector of a pnp transistor T16 connected, whose emitter via a resistor R14 is connected to the supply potential V and its Base connected to the bases of transistors T7 and T8 is.
  • the collector-emitter path of the transistor T3 the collector-emitter path of a pnp transistor T5 connected in parallel.
  • the emitter of the Transistor T5 connected to the base of transistor T4 and the collector of the transistor T5 is connected to the reference potential M. Its base is interposed by one Buffer stage controlled by a switching signal S.
  • the buffer stage consists of a pnp transistor T14, at the base the switching signal S is applied, whose emitter with the supply potential V is coupled and its collector with the base of the transistor T5 and with the interposition a resistor R12 coupled to the reference potential M. is.
  • a pnp transistor T5 could in the same Way also an npn transistor with appropriate polarity as well appropriate design of the switching signal S can be used.
  • the collector-emitter path of the transistor T6 the collector-emitter path of an npn transistor T9 connected in parallel.
  • the base of transistor T9 is under Interposition of a resistor R8 and another Buffer stage controlled by the switching signal S. Accordingly are the emitters and collectors of transistors T6 and T9 interconnected with each other.
  • the further buffer stage contains a pnp transistor T15, whose emitter with the supply potential V and its base with the base of the transistor T14 is connected.
  • the collector of transistor T15 is on the one hand with a connection of the resistor R8 and on the other another via a resistor R13 with the reference potential M coupled.
  • the base of transistor T9 is also connected to the input branch connected to a current mirror.
  • the input branch is through an npn transistor T13 formed, the base and collector interconnected as well as with the base of transistor T9 are and their emitters with the interposition of a resistor R10 is connected to the reference potential M.
  • the output branch of the current mirror is through an NPN transistor T12 formed, the base of which is connected to the base of the transistor T13 is connected and its emitter with interposition a resistor R9 connected to the reference potential M. is.
  • the collector of transistor T12 is on the base of a pnp transistor T10, the collector of which Reference potential M and its emitter with the bases of the transistors T7 and T8 is connected, as well as to the emitter of one NPN transistor T11, whose collector is connected to the supply potential V and its base with the collector of the transistor T8 is connected. After all, there is resistance R11 between the bases of transistors T7 and T8 on the one hand and the supply potential V on the other hand switched.
  • transistors T14 and T15 by the switching signal S locked their collector potentials are approximately the same the reference potential M.
  • the transistor T5 is then also locked and has the function of the other circuit parts no influence. In this case, transistor T4 becomes its Function controlled accordingly.
  • the transistor T15 delivers a starting current for the bandgap cell, the present Embodiment of the transistors T1 and T2 as well the resistors R1 to R3.
  • the transistors T14 and T15 controlled by the switching signal S so their respective collector potential is approximately equal to that Supply potential V.
  • the transistor T5 is also there turned on and generated at the base of transistor T4 a potential that this also in the blocking state brings. The current consumption of the bandgap cell thus goes against Zero.
  • the resistor R8 and its combination with a complementary consisting of transistors T10 and T11 Emitter followers support the shutdown process.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)
  • Amplifiers (AREA)

Claims (9)

  1. Circuit pour générer une tension de référence pouvant être validé ou inhibé, comprenant
    un premier transistor (T1) dont l'émetteur est relié à un potentiel de référence (M) et dont la base et le collecteur sont connectés l'un à l'autre,
    un deuxième transistor (T2) dont la base est reliée à la base du premier transistor (T1),
    une première résistance (R1) qui est branchée entre le collecteur du premier transistor (T1) et une borne de sortie (U) pour le prélèvement de la tension de référence,
    une deuxième résistance (R2) qui est branchée entre le collecteur du deuxième transistor (T2) et la borne de sortie (U),
    une troisième résistance (R3) qui est branchée entre l'émetteur du deuxième transistor (T2) et le potentiel de référence (M),
    un troisième transistor (T3) dont la base est reliée au collecteur du deuxième transistor (T2) et dont l'émetteur est relié au potentiel de référence (M), et
    une source de courant commandée (T4) qui est branchée entre un potentiel d'alimentation (V) et la borne de sortie (U) et qui est couplée, sur le côté d'entrée, au collecteur du troisième transistor (T3),
    caractérisé en ce que le trajet collecteur-émetteur du troisième transistor (T3) est branché en parallèle avec le trajet collecteur-émetteur d'un cinquième transistor (T5) et en ce que la base du cinquième transistor (T5) est commandée par un signal de commutation (S).
  2. Circuit selon la revendication 1, caractérisé en ce que la source de courant commandée (T4) comprend un quatrième transistor (T4) dont le collecteur est relié au potentiel d'alimentation (V), dont l'émetteur est relié à la borne de sortie (U) et dont la base est reliée au collecteur du troisième transistor (T3), et en ce qu'une source de courant supplémentaire (T7, T8, R4, R5, R6) est branchée entre la base et le collecteur du quatrième transistor (T4).
  3. Circuit selon la revendication 2, caractérisé en ce que la source de courant supplémentaire (T6, T7, T8, R4, R5, R6) comprend :
    un sixième transistor (T6) dont la base est reliée à la borne de sortie (U) et dont l'émetteur est relié au potentiel de référence (M) avec une quatrième résistance intercalée entre les deux ;
    un septième transistor (T7) dont l'émetteur est relié au potentiel d'alimentation (V) avec une cinquième résistance (R5) intercalée entre les deux, dont le collecteur est connecté à la base du cinquième transistor (T5) et dont la base est couplée au collecteur du sixième transistor (T6) ;
    un huitième transistor (T8) dont la base et le collecteur sont couplés l'un à l'autre ainsi qu'au collecteur du sixième transistor (T6) et dont l'émetteur est relié au potentiel d'alimentation (V) avec une sixième résistance (R6) intercalée entre les deux.
  4. Circuit selon l'une des revendications 2 ou 3, caractérisé en ce que le trajet collecteur-émetteur du sixième transistor (T6) est branché en parallèle avec le trajet collecteur-émetteur d'un neuvième transistor (T9) et en ce que la base du neuvième transistor (T9) est commandée par le signal de commutation (S).
  5. Circuit selon la revendication 4, caractérisé en ce qu'une septième résistance (R7) est branchée entre les bases des sixième et neuvième transistors (T6, T9).
  6. Circuit selon l'une des revendications 4 ou 5, caractérisé en ce que le signal de commutation (S) est amené à la base du neuvième transistor (T9) par le biais d'une huitième résistance (R8).
  7. Circuit selon l'une des revendications 4 à 6, caractérisé par un dixième transistor (T10) dont l'émetteur est relié aux bases des septième et huitième transistors (T7, T8) et dont le collecteur est relié au potentiel de référence, par un onzième transistor (T11) dont le collecteur est relié au potentiel d'alimentation (V), dont la base est reliée au collecteur du huitième transistor (T8) et dont l'émetteur est relié à la base du dixième transistor (T10), et par un miroir de courant (T12, T13, R9, R10) dont la branche d'entrée est couplée à la base du neuvième transistor (T9) et dont la branche de sortie est couplée à la base du dixième transistor (T10).
  8. Circuit selon l'une des revendications 3 à 7, caractérisé en ce qu'une onzième résistance (R11) est branchée entre les bases des septième et huitième transistors (T7, T8) d'une part et le potentiel d'alimentation (V) d'autre part.
  9. Circuit selon l'une des revendications 4 à 8, caractérisé en ce que le signal de commutation (S) est amené aux bases des cinquième et neuvième transistors (T5, T9) en intercalant à chaque fois un étage-tampon (T14, R12; T15, R13) entre les deux.
EP97107599A 1996-05-24 1997-05-05 Circuit pour générer une tension de référence pouvant être validée ou inhibée Expired - Lifetime EP0809169B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19621110 1996-05-24
DE19621110A DE19621110C1 (de) 1996-05-24 1996-05-24 Ein-/Ausschaltbare Schaltungsanordnung zur Erzeugung eines Referenzpotentials

Publications (3)

Publication Number Publication Date
EP0809169A2 EP0809169A2 (fr) 1997-11-26
EP0809169A3 EP0809169A3 (fr) 1998-12-09
EP0809169B1 true EP0809169B1 (fr) 2000-08-09

Family

ID=7795317

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97107599A Expired - Lifetime EP0809169B1 (fr) 1996-05-24 1997-05-05 Circuit pour générer une tension de référence pouvant être validée ou inhibée

Country Status (4)

Country Link
US (1) US5801582A (fr)
EP (1) EP0809169B1 (fr)
DE (2) DE19621110C1 (fr)
IN (1) IN191847B (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19624676C1 (de) * 1996-06-20 1997-10-02 Siemens Ag Schaltungsanordnung zur Erzeugung eines Referenzpotentials
JP4116133B2 (ja) * 1997-07-31 2008-07-09 株式会社東芝 温度依存型定電流発生回路およびこれを用いた光半導体素子の駆動回路
US6097179A (en) * 1999-03-08 2000-08-01 Texas Instruments Incorporated Temperature compensating compact voltage regulator for integrated circuit device
JP4212036B2 (ja) * 2003-06-19 2009-01-21 ローム株式会社 定電圧発生器
EP1501001A1 (fr) * 2003-07-22 2005-01-26 STMicroelectronics Limited Circuit de polarisation

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0727425B2 (ja) * 1988-12-28 1995-03-29 株式会社東芝 電圧発生回路
US5013934A (en) * 1989-05-08 1991-05-07 National Semiconductor Corporation Bandgap threshold circuit with hysteresis
US5278491A (en) * 1989-08-03 1994-01-11 Kabushiki Kaisha Toshiba Constant voltage circuit
JPH0680486B2 (ja) * 1989-08-03 1994-10-12 株式会社東芝 定電圧回路
JP3322685B2 (ja) * 1992-03-02 2002-09-09 日本テキサス・インスツルメンツ株式会社 定電圧回路および定電流回路
JP3381937B2 (ja) * 1992-05-22 2003-03-04 株式会社東芝 中間電位発生回路
JP3318365B2 (ja) * 1992-10-20 2002-08-26 富士通株式会社 定電圧回路
FR2711258A1 (fr) * 1993-10-13 1995-04-21 Philips Composants Circuit générateur de tension stabilisée du type bandgap.
US5703476A (en) * 1995-06-30 1997-12-30 Sgs-Thomson Microelectronics, S.R.L. Reference voltage generator, having a double slope temperature characteristic, for a voltage regulator of an automotive alternator

Also Published As

Publication number Publication date
US5801582A (en) 1998-09-01
DE19621110C1 (de) 1997-06-12
EP0809169A3 (fr) 1998-12-09
EP0809169A2 (fr) 1997-11-26
IN191847B (fr) 2004-01-10
DE59702125D1 (de) 2000-09-14

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