EP0809169A2 - Circuit pour générer une tension de référence pouvant être validé ou inhibée - Google Patents

Circuit pour générer une tension de référence pouvant être validé ou inhibée Download PDF

Info

Publication number
EP0809169A2
EP0809169A2 EP97107599A EP97107599A EP0809169A2 EP 0809169 A2 EP0809169 A2 EP 0809169A2 EP 97107599 A EP97107599 A EP 97107599A EP 97107599 A EP97107599 A EP 97107599A EP 0809169 A2 EP0809169 A2 EP 0809169A2
Authority
EP
European Patent Office
Prior art keywords
transistor
collector
base
emitter
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP97107599A
Other languages
German (de)
English (en)
Other versions
EP0809169B1 (fr
EP0809169A3 (fr
Inventor
Stephan Weber
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0809169A2 publication Critical patent/EP0809169A2/fr
Publication of EP0809169A3 publication Critical patent/EP0809169A3/fr
Application granted granted Critical
Publication of EP0809169B1 publication Critical patent/EP0809169B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities

Definitions

  • the invention relates to a circuit arrangement that can be switched on / off for generating a reference potential with a first transistor, whose emitter is connected to a reference potential and whose base and collector are connected to one another, with a second transistor, the base of which is connected to the base of the first transistor.
  • Such a circuit arrangement also referred to as a switchable bandgap reference, is known, for example, from Paul R. Gray, Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, Second Edition, John Wiley and Sons, 1984, pages 293 to 296.
  • reference voltage sources that can be switched on and off are being used more and more, since the reference voltage source does not consume any current when switched off should, it is advisable to switch the reference voltage source on / off by means of a switching device connected in series.
  • a pnp transistor is usually connected in series with a bandgap reference as a reference voltage source, so that the supply voltage must be higher than is actually necessary for the bandgap reference itself.
  • pnp transistors in standard technology can only be implemented as large-area lateral transistors. The base current for controlling the pnp transistor is often not negligible and increases the current consumption during operation.
  • the object of the invention is to provide a circuit arrangement which can be switched on / off for generating a reference potential and which does not have these disadvantages.
  • the switching means are included in the bandgap reference.
  • the collector-emitter path of a fifth transistor is connected in parallel and the base of the fifth transistor is controlled by a switching signal.
  • the controlled current source has a fourth transistor, the collector of which is connected to the supply potential, the emitter of which is connected to the output terminal and the base of which is connected to the collector of the third transistor. Another current source is connected between the base and collector of the fourth transistor. Furthermore, the further current source can have a sixth transistor, the base of which is connected to the output terminal and whose emitter is connected to the reference potential with the interposition of a fourth resistor.
  • a seventh transistor whose emitter is connected to the supply potential with the interposition of a fifth resistor, whose collector is connected to the base of the fourth transistor and whose base is coupled to the collector of the sixth transistor, and an eighth transistor whose base and Collector are coupled to each other and to the collector of the sixth transistor and the emitter is connected to the supply potential with the interposition of a sixth resistor.
  • the collector-emitter path of the sixth transistor is connected in parallel with the collector-emitter path of a ninth transistor and that the base of the ninth transistor is controlled by the switching signal.
  • a seventh resistor can be connected between the bases of the sixth and ninth transistor. Furthermore, the switching signal can be supplied to the base of the ninth transistor via an eighth resistor.
  • a further development of the invention includes a tenth transistor, the emitter of which is connected to the bases of the seventh and eighth transistor and the collector of which is connected to the reference potential. Furthermore, an eleventh transistor is provided, the collector of which is connected to the supply potential, the base of which is connected to the collector of the eighth transistor and the emitter of which is connected to the base of the tenth transistor. The base of the ninth transistor is coupled to the input branch of a current mirror, the output branch of which is coupled to the base of the tenth transistor.
  • An eleventh transistor can be connected between the bases of the seventh and eighth transistor on the one hand and the supply potential on the other hand, which contributes to increasing the stability.
  • the switching signal is fed to the bases of the fifth and sixth transistor, each with the interposition of a buffer stage.
  • an npn transistor T1 is provided, the emitter of which is connected to the reference potential M and the base and collector of which are connected to one another and are coupled via a common resistor R1 to an output terminal U carrying a reference potential.
  • the base of an npn transistor T2 is connected to the base and collector of the transistor T1, the emitter of which is coupled to the reference potential M via a resistor R3 and the collector of which is coupled to the output terminal U via a resistor R2.
  • the emitter of an npn transistor T4 is also connected to the output terminal U.
  • the base of the transistor T4 is connected to the collector of an npn transistor T3, the emitter of which is connected to the reference potential M and the base of which is connected to the collector of the transistor T2.
  • the base of the transistor T4 is also connected to the supply potential V via a current source circuit.
  • the current source circuit has a pnp transistor T7, the emitter of which is connected via a resistor R5 to the supply potential V and the collector of which is connected to the base of transistor T4 or the collector of transistor T3 is connected.
  • the base of the transistor T7 is connected to the base of a pnp transistor T8, the emitter of which is coupled to the supply potential V via a resistor R6.
  • the collector of the transistor T8 is also connected to the collector of an npn transistor T6, the emitter of which is connected to the reference potential M via a resistor R4 and the base of which is connected to the output terminal U.
  • an output connection I can also be provided which carries a reference current.
  • the output terminal I is connected to the collector of a pnp transistor T16, the emitter of which is connected to the supply potential V via a resistor R14 and the base of which is connected to the bases of the transistors T7 and T8.
  • the collector-emitter path of a pnp transistor T5 is connected in parallel.
  • the emitter of transistor T5 is connected to the base of transistor T4 and the collector of transistor T5 is connected to reference potential M.
  • Its base is controlled by a switching signal S with the interposition of a buffer stage.
  • the buffer stage consists of a pnp transistor T14, at the base of which the switching signal S is applied, the emitter of which is coupled to the supply potential V and the collector of which is coupled to the base of the transistor T5 and, with the interposition of a resistor R12, to the reference potential M.
  • a pnp transistor T5 an npn transistor could also be used in the same way with appropriate polarity and appropriate design of the switching signal S.
  • the collector-emitter path of transistor T6 is the collector-emitter path of an npn transistor T9 connected in parallel.
  • the base of the transistor T9 is driven by the switching signal S with the interposition of a resistor R8 and a further buffer stage. Accordingly, the emitters and the collectors of the transistors T6 and T9 are each connected to one another.
  • the further buffer stage contains a pnp transistor T15, the emitter of which is connected to the supply potential V and the base of which is connected to the base of the transistor T14.
  • the collector of the transistor T15 is coupled on the one hand to a connection of the resistor R8 and on the other hand via a resistor R13 to the reference potential M.
  • the base of transistor T9 is also connected to the input branch of a current mirror.
  • the input branch is formed by an npn transistor T13, the base and collector of which are connected to one another and to the base of the transistor T9 and whose emitter is connected to the reference potential M with the interposition of a resistor R10.
  • the output branch of the current mirror is formed by an NPN transistor T12, the base of which is connected to the base of the transistor T13 and the emitter of which is connected to the reference potential M with the interposition of a resistor R9.
  • the collector of the transistor T12 is based on a pnp transistor T10, the collector of which is connected to the reference potential M and the emitter of which is connected to the bases of the transistors T7 and T8, and of the emitter of an npn transistor T11, the collector of which is connected to the supply potential V and its base is connected to the collector of transistor T8. Finally, a resistor R11 is connected between the bases of the transistors T7 and T8 on the one hand and the supply potential V on the other.
  • transistors T14 and T15 are blocked by the switching signal S, their collector potentials are approximately equal to the reference potential M.
  • the transistor T5 is then also blocked and has no influence on the function of the other circuit parts. In this case, transistor T4 becomes its Function controlled accordingly.
  • the transistor T15 supplies a starting current for the bandgap cell, which in the present exemplary embodiment consists of the transistors T1 and T2 and the resistors R1 to R3. If, on the other hand, the transistors T14 and T15 are turned on by the switching signal S, their respective collector potential is approximately equal to the supply potential V.
  • the transistor T5 is also turned on and generates a potential at the base of the transistor T4 which also turns it off brings. The current consumption of the bandgap cell thus goes to zero.
  • Resistor R8 and its combination with a complementary emitter follower consisting of transistors T10 and T11 support the switch-off process.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)
  • Amplifiers (AREA)
EP97107599A 1996-05-24 1997-05-05 Circuit pour générer une tension de référence pouvant être validée ou inhibée Expired - Lifetime EP0809169B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19621110A DE19621110C1 (de) 1996-05-24 1996-05-24 Ein-/Ausschaltbare Schaltungsanordnung zur Erzeugung eines Referenzpotentials
DE19621110 1996-05-24

Publications (3)

Publication Number Publication Date
EP0809169A2 true EP0809169A2 (fr) 1997-11-26
EP0809169A3 EP0809169A3 (fr) 1998-12-09
EP0809169B1 EP0809169B1 (fr) 2000-08-09

Family

ID=7795317

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97107599A Expired - Lifetime EP0809169B1 (fr) 1996-05-24 1997-05-05 Circuit pour générer une tension de référence pouvant être validée ou inhibée

Country Status (4)

Country Link
US (1) US5801582A (fr)
EP (1) EP0809169B1 (fr)
DE (2) DE19621110C1 (fr)
IN (1) IN191847B (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19624676C1 (de) * 1996-06-20 1997-10-02 Siemens Ag Schaltungsanordnung zur Erzeugung eines Referenzpotentials
JP4116133B2 (ja) * 1997-07-31 2008-07-09 株式会社東芝 温度依存型定電流発生回路およびこれを用いた光半導体素子の駆動回路
US6097179A (en) * 1999-03-08 2000-08-01 Texas Instruments Incorporated Temperature compensating compact voltage regulator for integrated circuit device
JP4212036B2 (ja) * 2003-06-19 2009-01-21 ローム株式会社 定電圧発生器
EP1501001A1 (fr) * 2003-07-22 2005-01-26 STMicroelectronics Limited Circuit de polarisation

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0396996A2 (fr) * 1989-05-08 1990-11-14 National Semiconductor Corporation Circuit de seuil à bande interdite avec hystérésis
EP0411657A1 (fr) * 1989-08-03 1991-02-06 Kabushiki Kaisha Toshiba Circuit à tension constante
US5049806A (en) * 1988-12-28 1991-09-17 Kabushiki Kaisha Toshiba Band-gap type voltage generating circuit for an ECL circuit
JPH06131068A (ja) * 1992-10-20 1994-05-13 Fujitsu Ltd 定電圧回路
US5430395A (en) * 1992-03-02 1995-07-04 Texas Instruments Incorporated Temperature compensated constant-voltage circuit and temperature compensated constant-current circuit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5278491A (en) * 1989-08-03 1994-01-11 Kabushiki Kaisha Toshiba Constant voltage circuit
JP3381937B2 (ja) * 1992-05-22 2003-03-04 株式会社東芝 中間電位発生回路
FR2711258A1 (fr) * 1993-10-13 1995-04-21 Philips Composants Circuit générateur de tension stabilisée du type bandgap.
US5703476A (en) * 1995-06-30 1997-12-30 Sgs-Thomson Microelectronics, S.R.L. Reference voltage generator, having a double slope temperature characteristic, for a voltage regulator of an automotive alternator

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5049806A (en) * 1988-12-28 1991-09-17 Kabushiki Kaisha Toshiba Band-gap type voltage generating circuit for an ECL circuit
EP0396996A2 (fr) * 1989-05-08 1990-11-14 National Semiconductor Corporation Circuit de seuil à bande interdite avec hystérésis
EP0411657A1 (fr) * 1989-08-03 1991-02-06 Kabushiki Kaisha Toshiba Circuit à tension constante
US5430395A (en) * 1992-03-02 1995-07-04 Texas Instruments Incorporated Temperature compensated constant-voltage circuit and temperature compensated constant-current circuit
JPH06131068A (ja) * 1992-10-20 1994-05-13 Fujitsu Ltd 定電圧回路

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 018, no. 426 (P-1784), 9. August 1994 & JP 06 131068 A (FUJITSU LTD;OTHERS: 01), 13. Mai 1994 *

Also Published As

Publication number Publication date
IN191847B (fr) 2004-01-10
EP0809169B1 (fr) 2000-08-09
DE59702125D1 (de) 2000-09-14
US5801582A (en) 1998-09-01
EP0809169A3 (fr) 1998-12-09
DE19621110C1 (de) 1997-06-12

Similar Documents

Publication Publication Date Title
DE4221430B4 (de) Bezugsspannungsschaltung mit schnellem Hochfahren der Leistung ausgehend von einem Bereitschaftszustand mit niedriger Leistung
DE69019784T2 (de) Geschaltete Brückenanordnung.
DE69320326T2 (de) Mit niedriger Versorgungsspannung arbeitender, eine Hysteresis aufweisender Komparator
DE2210105C3 (de) Verknüpfungsschaltung
EP0814396B1 (fr) Circuit pour générer une tension de référence
EP0809169B1 (fr) Circuit pour générer une tension de référence pouvant être validée ou inhibée
EP0011704B1 (fr) Source de tension de référence, en particulier pour circuits amplificateurs
DE2506034A1 (de) Schaltungsanordnung zum elektronischen durchschalten einer wechselspannung
EP0421016A1 (fr) Convertisseur de niveau ECL-TTL
EP0374288A1 (fr) Circuit intégré diminuant le courant inverse d'un transistor polarisé inversement
DE69031019T2 (de) Ausgangssteuerungsschaltung
EP0196627B1 (fr) Montage amplificateur intégré
EP0011705B1 (fr) Amplificateur microphonique, en particulier pour installations téléphoniques
DE68919494T2 (de) Operationsverstärker.
DE3430338C2 (de) Sendeschaltung für Signalübertragungssysteme
EP0442001B1 (fr) Circuit comparateur
EP0682305B1 (fr) Circuit pour la génération d'un courant de référence
DE19717012B4 (de) Elektronische Schaltung
DE3509595A1 (de) Schaltungsanordnung
EP0578098B1 (fr) circuit de commande intégré pour une charge réactive
EP0806719B1 (fr) Circuit pour générer une tension de référence
DE19605248C1 (de) Treiberschaltung
DE3036736A1 (de) Schaltungsanordnung zur belastungsproportionalen einstellung des ansteuerstroms eines in emitterschaltung betriebenen eintakt-endstufentransistors eines transistorverstaerkers
DE1246027B (de) Logische Schaltung aus zwei in Stromuebernahme-schaltung geschalteten Transistoren
EP0495141B1 (fr) Dispositif de réglage d'amplitude

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): DE FR GB IT

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): DE FR GB IT

17P Request for examination filed

Effective date: 19990105

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

17Q First examination report despatched

Effective date: 19991021

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB IT

REF Corresponds to:

Ref document number: 59702125

Country of ref document: DE

Date of ref document: 20000914

ITF It: translation for a ep patent filed
GBT Gb: translation of ep patent filed (gb section 77(6)(a)/1977)

Effective date: 20001010

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20030512

Year of fee payment: 7

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20040427

Year of fee payment: 8

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20050131

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20050505

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20050505

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20050505

REG Reference to a national code

Ref country code: DE

Ref legal event code: R081

Ref document number: 59702125

Country of ref document: DE

Owner name: INTEL MOBILE COMMUNICATIONS GMBH, DE

Free format text: FORMER OWNER: SIEMENS AKTIENGESELLSCHAFT, 80333 MUENCHEN, DE

Effective date: 20111107

Ref country code: DE

Ref legal event code: R081

Ref document number: 59702125

Country of ref document: DE

Owner name: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH, DE

Free format text: FORMER OWNER: SIEMENS AKTIENGESELLSCHAFT, 80333 MUENCHEN, DE

Effective date: 20111107

REG Reference to a national code

Ref country code: DE

Ref legal event code: R081

Ref document number: 59702125

Country of ref document: DE

Owner name: INTEL MOBILE COMMUNICATIONS GMBH, DE

Free format text: FORMER OWNER: INTEL MOBILE COMMUNICATIONS TECHNOLOGY GMBH, 85579 NEUBIBERG, DE

Effective date: 20130326

Ref country code: DE

Ref legal event code: R081

Ref document number: 59702125

Country of ref document: DE

Owner name: INTEL MOBILE COMMUNICATIONS GMBH, DE

Free format text: FORMER OWNER: INFINEON TECHNOLOGIES AG, 85579 NEUBIBERG, DE

Effective date: 20130314

Ref country code: DE

Ref legal event code: R081

Ref document number: 59702125

Country of ref document: DE

Owner name: INTEL MOBILE COMMUNICATIONS GMBH, DE

Free format text: FORMER OWNER: INFINEON TECHNOLOGIES AG, 85579 NEUBIBERG, DE

Effective date: 20130315

Ref country code: DE

Ref legal event code: R081

Ref document number: 59702125

Country of ref document: DE

Owner name: INTEL MOBILE COMMUNICATIONS GMBH, DE

Free format text: FORMER OWNER: INTEL MOBILE COMMUNICATIONS GMBH, 85579 NEUBIBERG, DE

Effective date: 20130315

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20140430

Year of fee payment: 18

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 59702125

Country of ref document: DE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20151201