EP0374288A1 - Circuit intégré diminuant le courant inverse d'un transistor polarisé inversement - Google Patents

Circuit intégré diminuant le courant inverse d'un transistor polarisé inversement Download PDF

Info

Publication number
EP0374288A1
EP0374288A1 EP88121417A EP88121417A EP0374288A1 EP 0374288 A1 EP0374288 A1 EP 0374288A1 EP 88121417 A EP88121417 A EP 88121417A EP 88121417 A EP88121417 A EP 88121417A EP 0374288 A1 EP0374288 A1 EP 0374288A1
Authority
EP
European Patent Office
Prior art keywords
transistor
base
collector
emitter
potential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP88121417A
Other languages
German (de)
English (en)
Other versions
EP0374288B1 (fr
Inventor
Frank-Lothar Dipl.-Ing. Schwertlein (Fh)
Michael Ing. Grad. Lenz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to EP88121417A priority Critical patent/EP0374288B1/fr
Priority to AT88121417T priority patent/ATE112868T1/de
Priority to DE3851839T priority patent/DE3851839D1/de
Priority to US07/455,553 priority patent/US4945444A/en
Publication of EP0374288A1 publication Critical patent/EP0374288A1/fr
Application granted granted Critical
Publication of EP0374288B1 publication Critical patent/EP0374288B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10Regulating voltage or current
    • G05F1/46Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/569Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection
    • G05F1/571Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overvoltage detector
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10Regulating voltage or current
    • G05F1/46Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/569Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection

Definitions

  • the present invention relates to a circuit arrangement according to the preamble of patent claim 1.
  • the voltage at the output is much higher than for the supply voltage.
  • the outputs are usually wired with smoothing capacitors, i.e. Voltage regulators are usually operated with a capacitive load. For example, in the event of a short circuit at the input of a low-dropout voltage regulator - caused, for example, by switching off the voltage supply at which other consumers are connected - the voltage at the input of the voltage regulator goes to zero, while at the output the voltage is initially maintained by the smoothing capacitors.
  • inverse operation a current flows in the opposite direction to the original direction, also called reverse current, which can lead to functional impairment or even destruction of the voltage regulator, since the output transistor of the voltage regulator switches through from the output to the input of the voltage regulator in this operating mode, hereinafter referred to as inverse operation .
  • a low-dropout voltage regulator known, for example, from "Sanken New Products Information, Low-Dropout Hybrid Voltage Regulator, Sanken Electric Company"
  • an external diode is connected between the output and input of the voltage regulator as protection during inverse operation in such a way that it blocks in normal operation and in Inverse operation is leading.
  • the return current is thus carried in whole or in part via the diode.
  • the disadvantage of this is that the smoothing capacitor is again discharged quickly, just as when operating without a diode, and therefore the voltage at the output of the voltage regulator drops rapidly. However, this is particularly undesirable in the case of power supplies for microcomputer systems.
  • the object of the invention is to provide a circuit arrangement which at least reduces the reverse current of an inversely operated transistor.
  • the advantage of the invention is that due to the almost complete blocking of the transistor in inverse operation, only a small reverse current flows and the transistor itself is protected against functional impairments or destruction. This is particularly advantageous when used as an output transistor of a low-dropout voltage regulator, since the voltage at the output drops more slowly.
  • the exemplary embodiment according to FIG. 1 shows a conventional output stage of a low-dropout voltage regulator with a first transistor 4 of the PNP type, the emitter of which is acted upon by a first potential 1 and the collector of which is acted upon by a second potential 2.
  • the base of the first transistor 4, the base-emitter path of which is parallel to a resistor 6, is connected to the collector of a second transistor 5 of the NPN type, the emitter of which leads to reference potential 0 and at the base of which a control potential 3 for control in the regular manner Operating case is connected.
  • the base-collector path of the first transistor 4 is connected in parallel with a transistor 7 of the PNP type, which is operated as a diode by interconnecting the base and collector and is conducting in inverse operation.
  • FIG. 2 shows the embodiment according to FIG. 1 to the extent that the collector of a third transistor 20, whose emitter is connected to the collector and whose base is connected to the base of the first transistor 4, with the base of a fourth transistor 8 of the PNP type, which is on the emitter side at the first potential 1 and on the collector side at the base of the first transistor 4, and is connected to a second and third resistor 9, 10, the first resistor 6 and the transistor 7 operated as a diode from FIG. 1 being omitted.
  • the second resistor 9 is connected to the first potential 1 and the third resistor 10 to the collector of a fifth transistor 11 of the NPN type, the emitter of which is at reference potential 0 and the base of which is connected to the output of a comparator 12.
  • the inverting input of the comparator 12 has the first potential 1 applied to it and the non-inverting input has a reference potential 13.
  • the exemplary embodiment according to FIG. 2 is a sixth transistor 14 of the PNP type, a seventh transistor 15 of the PNP type, and an eighth transistor 19 of the NPN type and a fourth, fifth and sixth resistor 16, 17, 18 extended.
  • the base of the seventh transistor 15 is in turn connected to a fourth resistor 16 leading to the first potential 1 and to a fifth resistor 17 connected to the collector of the eighth transistor 19.
  • an additional collector of the third transistor 20 is also connected to the base of the seventh transistor 15.
  • the base of the eighth transistor 19, which is at reference potential 0 on the emitter side, is connected to the output of the comparator 12, as is the base of the fifth transistor 11.
  • the collector acts as an inverse emitter and the emitter as an inverse collector.
  • the first transistor 4 is turned on inversely.
  • the base current of the first transistor 4 is reduced to such an extent that the reverse current I R is reduced via the inverse current gain bstrom of the first transistor 4.
  • the fourth transistor 8 is clamped by the fourth transistor 8 when the first potential 1 is too high, as shown in FIG.
  • the fourth transistor 8 is activated by a monitoring circuit with the comparator 12, which compares the first potential 1 with the reference potential 13 and, in the event of an impermissible increase in the first potential 1, via the fifth transistor 11 in conjunction with the second and third resistors 9, 10 turns on the fourth transistor 8.
  • the first transistor 4 and the fourth transistor 8 are inversely conductive.
  • I R I B8 ⁇ (1 + b4) ⁇ (1 + b8)
  • the base current I B4 of the fourth transistor 4 is equal to the quotient of the voltage across the second resistor 9 and its resistance value. Adding the third transistor 20 in the manner shown results in a base current I B8 for the fourth transistor 8 that is lower by the amount of the collector current of the third transistor 20.
  • the exemplary embodiment shown in FIG. 3 contains an additional stage with a sixth transistor 14, a seventh transistor 15, an eighth transistor 17, and a fourth, fifth and sixth resistor 16, 17, 18, which in normal operation are by means of the emitter and base of the first Sixth transistor 14 located in transistor 4 acts as an active scraper, comparable to the first resistor 6 from FIG. 1. If an excessively high first potential 1 occurs, the sixth transistor 14 is blocked by the comparator 12 and the subsequent circuit part, while the fourth transistor 8, also controlled by the comparator 12, the first transistor 4 clamps. As a result, the first transistor 4 is blocked, which on the one hand increases its dielectric strength and on the other hand allows a higher current gain for normal operation. A higher current gain in turn improves the efficiency of the circuit arrangement.
  • both the first transistor 4 and the fourth transistor 8, the third transistor 5 and the sixth transistor 14 are largely blocked, as a result of which there is only a very low reverse current I R.
  • the advantage of this embodiment of a circuit arrangement according to the invention is that, in addition to a low reverse current in inverse operation, increased dielectric strength is achieved with higher efficiency in normal operation.
  • the base of the first transistor 4 is provided as the base of the third transistor 20 and the collector of the third transistor 20 is provided as the emitter. This has the advantage of low circuitry requirements and less space.
  • monitoring circuit is not limited to only one embodiment with a comparator.
  • circuits with Zener diodes and / or non-linear voltage dividers are also suitable.
EP88121417A 1988-12-21 1988-12-21 Circuit intégré diminuant le courant inverse d'un transistor polarisé inversement Expired - Lifetime EP0374288B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP88121417A EP0374288B1 (fr) 1988-12-21 1988-12-21 Circuit intégré diminuant le courant inverse d'un transistor polarisé inversement
AT88121417T ATE112868T1 (de) 1988-12-21 1988-12-21 Integrierbare schaltungsanordnung zur rückstromverringerung bei einem invers betriebenen transistor.
DE3851839T DE3851839D1 (de) 1988-12-21 1988-12-21 Integrierbare Schaltungsanordnung zur Rückstromverringerung bei einem invers betriebenen Transistor.
US07/455,553 US4945444A (en) 1988-12-21 1989-12-18 Integratable circuit configuration for reverse current reduction in an inversely operated transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP88121417A EP0374288B1 (fr) 1988-12-21 1988-12-21 Circuit intégré diminuant le courant inverse d'un transistor polarisé inversement

Publications (2)

Publication Number Publication Date
EP0374288A1 true EP0374288A1 (fr) 1990-06-27
EP0374288B1 EP0374288B1 (fr) 1994-10-12

Family

ID=8199697

Family Applications (1)

Application Number Title Priority Date Filing Date
EP88121417A Expired - Lifetime EP0374288B1 (fr) 1988-12-21 1988-12-21 Circuit intégré diminuant le courant inverse d'un transistor polarisé inversement

Country Status (4)

Country Link
US (1) US4945444A (fr)
EP (1) EP0374288B1 (fr)
AT (1) ATE112868T1 (fr)
DE (1) DE3851839D1 (fr)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5179492A (en) * 1990-03-30 1993-01-12 Pioneer Electronic Corporation Protection circuit for detachable operating unit used in audio device
FR2700647B1 (fr) * 1993-01-15 1995-03-31 Legrand Sa Commutateur statique à protection intégrée pour le couplage d'une charge à une source électrique, comportant un transistor bipolaire à grille isolée.
JP3272298B2 (ja) * 1998-04-27 2002-04-08 インターナショナル・ビジネス・マシーンズ・コーポレーション 放電回路を備えたスイッチ回路および電子機器
US6675304B1 (en) * 1999-11-29 2004-01-06 Intel Corporation System for transitioning a processor from a higher to a lower activity state by switching in and out of an impedance on the voltage regulator
US6611410B1 (en) 1999-12-17 2003-08-26 Siemens Vdo Automotive Inc. Positive supply lead reverse polarity protection circuit
US6188212B1 (en) * 2000-04-28 2001-02-13 Burr-Brown Corporation Low dropout voltage regulator circuit including gate offset servo circuit powered by charge pump
DE102005011653B4 (de) * 2005-03-14 2007-12-06 Infineon Technologies Ag Schaltungsanordnung mit einem Transistor mit verringertem Rückstrom
TWI330353B (en) * 2006-06-30 2010-09-11 Chimei Innolux Corp Power supplying and discharging circuit for liquid crystal panel
TWI339481B (en) * 2007-01-29 2011-03-21 Chimei Innolux Corp Power supplying and discharging circuit
CN203166467U (zh) * 2013-03-20 2013-08-28 向智勇 一种过压保护电路

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3970869A (en) * 1975-03-03 1976-07-20 The United States Of America As Represented By The Secretary Of The Navy Low power driver
US4420786A (en) * 1981-11-16 1983-12-13 Motorola, Inc. Polarity guard circuit
DE3505986A1 (de) * 1985-02-21 1986-08-21 Deutsche Thomson-Brandt Gmbh, 7730 Villingen-Schwenningen Kurzschlussfestes netzteil, insbesondere fuer einen fernsehempfaenger
NL8601718A (nl) * 1986-07-02 1988-02-01 Philips Nv Transistorschakeling.

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ELECTRONIC ENGINEERING. vol. 44, no. 535, September 1972, LONDON GB Seiten 61 - 63; L.S. CORNISH: "TRANSIENT-TESTING VITAL TO AIRBORNE SYSTEMS RELIABILITY" *
PATENT ABSTRACTS OF JAPAN vol. 9, no. 44 (P-337)(1767) 23 Februar 1985, & JP-A-59 183419 (FUJITSU) 18 Oktober 1984, *

Also Published As

Publication number Publication date
ATE112868T1 (de) 1994-10-15
DE3851839D1 (de) 1994-11-17
EP0374288B1 (fr) 1994-10-12
US4945444A (en) 1990-07-31

Similar Documents

Publication Publication Date Title
DE3342735C2 (fr)
DE102014108576A1 (de) Treiberschaltung mit Miller-Clamping-Funktionalität für Leistungshalbleiterschalter, Leistungshalbleiterschalter und Wechselrichterbrücke
DE3700071A1 (de) Halbleiterschalter
EP0374288B1 (fr) Circuit intégré diminuant le courant inverse d'un transistor polarisé inversement
DE3402222A1 (de) Schaltungsanordnung zum begrenzen von ueberspannungen
DE2814021B2 (de) Schaltungsanordnung für einen steuerbaren Gleichrichter, der über seine Steuerelektrode abschaltbar ist
DE2233260C2 (de) Quasi-komplementäre Schaltung
DE2506196A1 (de) Gleichstrom-schaltvorrichtung
DE2816314B2 (de) MOSFET-Source-Folgerschaltung
DE19838109B4 (de) Ansteuerschaltung für induktive Lasten
DE10317374A1 (de) Steuerschaltung für Leistungsvorrichtung
DE2431487C2 (de) Triggerschaltung
DE2635574C3 (de) Stromspiegelschaltung
DE2813073A1 (de) Diskriminator-schaltung
DE2404850C3 (de) Elektronische Sicherung für einen Gegentakt-Verstarker
DE3931893A1 (de) Schaltung zur strombegrenzung mit foldback-verhalten
DE3536447C2 (de) Kurzschluß- und überlastfeste Transistorausgangsstufe
DE3435324C2 (fr)
DE3029895C2 (de) Schaltungsanordnung zum Speisen einer eine konstante Betriebsspannung liefernden Stromversorgungseinrichtung
DE1805855A1 (de) Gegentaktverstaerker
DE3901560C2 (fr)
EP0552716A2 (fr) Circuit de transistor intégré
EP0758108B1 (fr) Dispositif de miroir de courant
DE3405809C2 (de) Ausgangsstufe
DE69922495T2 (de) Schaltung zur Verbindung zwischen einem Autoradio und einer Kraftfahrzeugbatterie

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE CH DE ES FR GB GR IT LI LU NL SE

RBV Designated contracting states (corrected)

Designated state(s): AT DE FR GB IT NL SE

17P Request for examination filed

Effective date: 19901205

ITF It: translation for a ep patent filed

Owner name: STUDIO ING. E. BONINI S.R.L.

17Q First examination report despatched

Effective date: 19930428

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT DE FR GB IT NL SE

REF Corresponds to:

Ref document number: 112868

Country of ref document: AT

Date of ref document: 19941015

Kind code of ref document: T

REF Corresponds to:

Ref document number: 3851839

Country of ref document: DE

Date of ref document: 19941117

ITF It: translation for a ep patent filed

Owner name: STUDIO JAUMANN

EAL Se: european patent in force in sweden

Ref document number: 88121417.5

GBT Gb: translation of ep patent filed (gb section 77(6)(a)/1977)

Effective date: 19950106

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: AT

Payment date: 19961127

Year of fee payment: 9

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: SE

Payment date: 19961210

Year of fee payment: 9

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: NL

Payment date: 19961217

Year of fee payment: 9

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19971221

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19971222

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19980701

NLV4 Nl: lapsed or anulled due to non-payment of the annual fee

Effective date: 19980701

EUG Se: european patent has lapsed

Ref document number: 88121417.5

REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: IT

Payment date: 20071222

Year of fee payment: 20

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20071218

Year of fee payment: 20

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20080219

Year of fee payment: 20

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20071217

Year of fee payment: 20

REG Reference to a national code

Ref country code: GB

Ref legal event code: PE20

Expiry date: 20081220

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF EXPIRATION OF PROTECTION

Effective date: 20081220