EP0374288A1 - Integrated circuit diminishing the inverse current of an inversely polarized transistor - Google Patents

Integrated circuit diminishing the inverse current of an inversely polarized transistor Download PDF

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Publication number
EP0374288A1
EP0374288A1 EP88121417A EP88121417A EP0374288A1 EP 0374288 A1 EP0374288 A1 EP 0374288A1 EP 88121417 A EP88121417 A EP 88121417A EP 88121417 A EP88121417 A EP 88121417A EP 0374288 A1 EP0374288 A1 EP 0374288A1
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EP
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Prior art keywords
transistor
base
collector
emitter
potential
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Granted
Application number
EP88121417A
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German (de)
French (fr)
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EP0374288B1 (en
Inventor
Frank-Lothar Dipl.-Ing. Schwertlein (Fh)
Michael Ing. Grad. Lenz
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Siemens AG
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Siemens AG
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Priority to AT88121417T priority Critical patent/ATE112868T1/en
Priority to DE3851839T priority patent/DE3851839D1/en
Priority to EP88121417A priority patent/EP0374288B1/en
Priority to US07/455,553 priority patent/US4945444A/en
Publication of EP0374288A1 publication Critical patent/EP0374288A1/en
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/569—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection
    • G05F1/571—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overvoltage detector
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/569—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection

Definitions

  • the present invention relates to a circuit arrangement according to the preamble of patent claim 1.
  • the voltage at the output is much higher than for the supply voltage.
  • the outputs are usually wired with smoothing capacitors, i.e. Voltage regulators are usually operated with a capacitive load. For example, in the event of a short circuit at the input of a low-dropout voltage regulator - caused, for example, by switching off the voltage supply at which other consumers are connected - the voltage at the input of the voltage regulator goes to zero, while at the output the voltage is initially maintained by the smoothing capacitors.
  • inverse operation a current flows in the opposite direction to the original direction, also called reverse current, which can lead to functional impairment or even destruction of the voltage regulator, since the output transistor of the voltage regulator switches through from the output to the input of the voltage regulator in this operating mode, hereinafter referred to as inverse operation .
  • a low-dropout voltage regulator known, for example, from "Sanken New Products Information, Low-Dropout Hybrid Voltage Regulator, Sanken Electric Company"
  • an external diode is connected between the output and input of the voltage regulator as protection during inverse operation in such a way that it blocks in normal operation and in Inverse operation is leading.
  • the return current is thus carried in whole or in part via the diode.
  • the disadvantage of this is that the smoothing capacitor is again discharged quickly, just as when operating without a diode, and therefore the voltage at the output of the voltage regulator drops rapidly. However, this is particularly undesirable in the case of power supplies for microcomputer systems.
  • the object of the invention is to provide a circuit arrangement which at least reduces the reverse current of an inversely operated transistor.
  • the advantage of the invention is that due to the almost complete blocking of the transistor in inverse operation, only a small reverse current flows and the transistor itself is protected against functional impairments or destruction. This is particularly advantageous when used as an output transistor of a low-dropout voltage regulator, since the voltage at the output drops more slowly.
  • the exemplary embodiment according to FIG. 1 shows a conventional output stage of a low-dropout voltage regulator with a first transistor 4 of the PNP type, the emitter of which is acted upon by a first potential 1 and the collector of which is acted upon by a second potential 2.
  • the base of the first transistor 4, the base-emitter path of which is parallel to a resistor 6, is connected to the collector of a second transistor 5 of the NPN type, the emitter of which leads to reference potential 0 and at the base of which a control potential 3 for control in the regular manner Operating case is connected.
  • the base-collector path of the first transistor 4 is connected in parallel with a transistor 7 of the PNP type, which is operated as a diode by interconnecting the base and collector and is conducting in inverse operation.
  • FIG. 2 shows the embodiment according to FIG. 1 to the extent that the collector of a third transistor 20, whose emitter is connected to the collector and whose base is connected to the base of the first transistor 4, with the base of a fourth transistor 8 of the PNP type, which is on the emitter side at the first potential 1 and on the collector side at the base of the first transistor 4, and is connected to a second and third resistor 9, 10, the first resistor 6 and the transistor 7 operated as a diode from FIG. 1 being omitted.
  • the second resistor 9 is connected to the first potential 1 and the third resistor 10 to the collector of a fifth transistor 11 of the NPN type, the emitter of which is at reference potential 0 and the base of which is connected to the output of a comparator 12.
  • the inverting input of the comparator 12 has the first potential 1 applied to it and the non-inverting input has a reference potential 13.
  • the exemplary embodiment according to FIG. 2 is a sixth transistor 14 of the PNP type, a seventh transistor 15 of the PNP type, and an eighth transistor 19 of the NPN type and a fourth, fifth and sixth resistor 16, 17, 18 extended.
  • the base of the seventh transistor 15 is in turn connected to a fourth resistor 16 leading to the first potential 1 and to a fifth resistor 17 connected to the collector of the eighth transistor 19.
  • an additional collector of the third transistor 20 is also connected to the base of the seventh transistor 15.
  • the base of the eighth transistor 19, which is at reference potential 0 on the emitter side, is connected to the output of the comparator 12, as is the base of the fifth transistor 11.
  • the collector acts as an inverse emitter and the emitter as an inverse collector.
  • the first transistor 4 is turned on inversely.
  • the base current of the first transistor 4 is reduced to such an extent that the reverse current I R is reduced via the inverse current gain bstrom of the first transistor 4.
  • the fourth transistor 8 is clamped by the fourth transistor 8 when the first potential 1 is too high, as shown in FIG.
  • the fourth transistor 8 is activated by a monitoring circuit with the comparator 12, which compares the first potential 1 with the reference potential 13 and, in the event of an impermissible increase in the first potential 1, via the fifth transistor 11 in conjunction with the second and third resistors 9, 10 turns on the fourth transistor 8.
  • the first transistor 4 and the fourth transistor 8 are inversely conductive.
  • I R I B8 ⁇ (1 + b4) ⁇ (1 + b8)
  • the base current I B4 of the fourth transistor 4 is equal to the quotient of the voltage across the second resistor 9 and its resistance value. Adding the third transistor 20 in the manner shown results in a base current I B8 for the fourth transistor 8 that is lower by the amount of the collector current of the third transistor 20.
  • the exemplary embodiment shown in FIG. 3 contains an additional stage with a sixth transistor 14, a seventh transistor 15, an eighth transistor 17, and a fourth, fifth and sixth resistor 16, 17, 18, which in normal operation are by means of the emitter and base of the first Sixth transistor 14 located in transistor 4 acts as an active scraper, comparable to the first resistor 6 from FIG. 1. If an excessively high first potential 1 occurs, the sixth transistor 14 is blocked by the comparator 12 and the subsequent circuit part, while the fourth transistor 8, also controlled by the comparator 12, the first transistor 4 clamps. As a result, the first transistor 4 is blocked, which on the one hand increases its dielectric strength and on the other hand allows a higher current gain for normal operation. A higher current gain in turn improves the efficiency of the circuit arrangement.
  • both the first transistor 4 and the fourth transistor 8, the third transistor 5 and the sixth transistor 14 are largely blocked, as a result of which there is only a very low reverse current I R.
  • the advantage of this embodiment of a circuit arrangement according to the invention is that, in addition to a low reverse current in inverse operation, increased dielectric strength is achieved with higher efficiency in normal operation.
  • the base of the first transistor 4 is provided as the base of the third transistor 20 and the collector of the third transistor 20 is provided as the emitter. This has the advantage of low circuitry requirements and less space.
  • monitoring circuit is not limited to only one embodiment with a comparator.
  • circuits with Zener diodes and / or non-linear voltage dividers are also suitable.

Abstract

An integratable circuit configuration includes a first transistor of one conduction type having an emitter being acted upon by a first potential, a collector being acted upon by a second potential, a base, a base-to-collector path and a base-to-emitter path. A resistor is connected in parallel with the base-to-emitter path of the first transistor. A second transistor of the other conduction type is connected to the base of the first transistor for triggering. A diode may be connected in parallel with the base-to-collector path of the first transistor. The diode conducts in inverse operation for reverse current reduction during inverse operation of the first transistor. A third transistor may be connected to the first transistor instead of the diode and fourth and further transistors may also be connected to the first transistor.

Description

Die vorliegende Erfindung betrifft eine Schaltungsanordnung nach dem Oberbegriff des Patentanspruchs 1.The present invention relates to a circuit arrangement according to the preamble of patent claim 1.

Werden beispielsweise Verstärker oder Spannungsregler mit einer kapazitiven Last betrieben und bricht währenddessen die Versorgungsspannung zusammen, so ergibt sich für die Spannung am Ausgang ein wesentlich höherer Wert als für die Versorgungsspannung. Bei Spannungsreglern allgemein werden in der Regel die Ausgänge mit Glättungskondensatoren beschaltet, d.h. Spannungsregler werden üblicherweise mit kapazitiver Last betrieben. Beispielsweise bei einem Kurz­schluß am Eingang eines Low-Dropout Spannungsreglers - her­vorgerufen etwa durch Abschalten der Spannungsversorgung, an der weitere Verbraucher liegen - geht die Spannung am Eingang des Spannungsreglers gegen Null, während an dessen Ausgang die Spannung durch die Glättungskondensatoren zu­nächst noch aufrechterhalten wird. Es fließt dadurch ein der ursprünglichen Richtung entgegengesetzter Strom, auch Rück­strom genannt, welcher zu einer Funktionsbeeinträchtigung bis hin zur Zerstörung des Spannungsreglers führen kann, da der Ausgangstransistor des Spannungsreglers bei dieser Be­triebsform, im folgenden als Inversbetrieb bezeichnet, vom Ausgang auf den Eingang des Spannungsreglers durchschaltet.If, for example, amplifiers or voltage regulators are operated with a capacitive load and the supply voltage breaks down in the meantime, the voltage at the output is much higher than for the supply voltage. With voltage regulators in general, the outputs are usually wired with smoothing capacitors, i.e. Voltage regulators are usually operated with a capacitive load. For example, in the event of a short circuit at the input of a low-dropout voltage regulator - caused, for example, by switching off the voltage supply at which other consumers are connected - the voltage at the input of the voltage regulator goes to zero, while at the output the voltage is initially maintained by the smoothing capacitors. As a result, a current flows in the opposite direction to the original direction, also called reverse current, which can lead to functional impairment or even destruction of the voltage regulator, since the output transistor of the voltage regulator switches through from the output to the input of the voltage regulator in this operating mode, hereinafter referred to as inverse operation .

Bei einem beispielsweise aus "Sanken New Products Informa­tions, Low-Dropout Hybrid Voltage Regulator, Sanken Elec­tric Company" bekannten Low-Dropout Spannungsregler wird als Schutz bei Inversbetrieb eine externe Diode zwischen Aus­gang und Eingang des Spannungsreglers derart geschaltet, daß diese im Normalbetrieb sperrend und im Inversbetrieb leitend ist. Der Rückstrom wird somit ganz oder teilweise über die Diode geführt. Der Nachteil dabei ist jedoch, daß der Glättungskondensator ebenso wie beim Betrieb ohne Diode wiederum rasch entladen wird und deshalb die Spannung am Ausgang des Spannungsreglers schnell abfällt. Dies ist aber insbesondere bei Stromversorgungen von Mikrocomputersystemen unerwünscht.In a low-dropout voltage regulator known, for example, from "Sanken New Products Information, Low-Dropout Hybrid Voltage Regulator, Sanken Electric Company", an external diode is connected between the output and input of the voltage regulator as protection during inverse operation in such a way that it blocks in normal operation and in Inverse operation is leading. The return current is thus carried in whole or in part via the diode. The disadvantage of this, however, is that the smoothing capacitor is again discharged quickly, just as when operating without a diode, and therefore the voltage at the output of the voltage regulator drops rapidly. However, this is particularly undesirable in the case of power supplies for microcomputer systems.

Aufgabe der Erfindung ist es, eine Schaltungsanordnung an­zugeben, welche den Rückstrom eines invers betriebenen Tran­sistors mindestens verringert.The object of the invention is to provide a circuit arrangement which at least reduces the reverse current of an inversely operated transistor.

Die Aufgabe wird bei einer gattungsgemäßen Schaltungsanord­nung durch die kennzeichnenden Merkmale des Patentanspruchs 1 gelöst. Weiterbildungen und Ausgestaltungen des Erfindungs­gedankens sind in Unteransprüchen gekennzeichnet.The object is achieved in a generic circuit arrangement by the characterizing features of claim 1. Further developments and refinements of the inventive concept are characterized in the subclaims.

Vorteil der Erfindung ist es, daß durch das nahezu vollstän­dige Sperren des Transistors im Inversbetrieb nur ein gerin­ger Rückstrom fließt und der Transistor selbst vor Funk­tionsbeeinträchtigungen oder Zerstörung geschützt wird. Dies ist insbesondere bei der Anwendung als Ausgangstran­sistor eines Low-Dropout Spannungsreglers vorteilhaft, da die Spannung am Ausgang langsamer abfällt.The advantage of the invention is that due to the almost complete blocking of the transistor in inverse operation, only a small reverse current flows and the transistor itself is protected against functional impairments or destruction. This is particularly advantageous when used as an output transistor of a low-dropout voltage regulator, since the voltage at the output drops more slowly.

Die Erfindung wird nachfolgend anhand von den in den Figuren der Zeichnung dargestellten Ausführungsbeispielen näher er­läutert, wobei gleiche Elemente mit gleichen Bezugszeichen versehen sind. Es zeigt:

  • FIG 1 eine erste Ausführungsform einer erfindungsgemäßen Schaltungsanordnung;
  • FIG 2 eine zweite, weitergebildete Ausführungsform einer erfindungsgemäßen Schaltungsanordnung mit höherer Spannungsfestigkeit;
  • FIG 3 eine Weiterbildung der Ausführungsform nach FIG 2.
The invention is explained in more detail below on the basis of the exemplary embodiments illustrated in the figures of the drawing, the same elements being provided with the same reference symbols. It shows:
  • 1 shows a first embodiment of a circuit arrangement according to the invention;
  • 2 shows a second, further developed embodiment of a circuit arrangement according to the invention with higher dielectric strength;
  • 3 shows a development of the embodiment according to FIG. 2.

Das Ausführungsbeispiel gemäß FIG 1 zeigt eine übliche Aus­gangsstufe eines Low-Dropout Spannungsreglers mit einem ersten Transistor 4 vom PNP-Typ, dessen Emitter mit einem ersten Potential 1 und dessen Kollektor mit einem zweiten Potential 2 beaufschlagt ist. Die Basis des ersten Tran­sistors 4, dessen Basis-Emitter-Strecke parallel zu einem Widerstand 6 liegt, ist mit dem Kollektor eines zweiten Transistors 5 vom NPN-Typ, dessen Emitter auf Bezugspoten­tial 0 geführt und an dessen Basis ein Steuerpotential 3 zur Ansteuerung im regulären Betriebsfall gelegt ist, ver­bunden. Erfindungsgemäß ist der Basis-Kollektor-Strecke des ersten Transistors 4 ein durch Zusammenschalten von Basis und Kollektor als Diode betriebener und im Inversbetrieb leitender Transistor 7 vom PNP-Typ parallel geschaltet.The exemplary embodiment according to FIG. 1 shows a conventional output stage of a low-dropout voltage regulator with a first transistor 4 of the PNP type, the emitter of which is acted upon by a first potential 1 and the collector of which is acted upon by a second potential 2. The base of the first transistor 4, the base-emitter path of which is parallel to a resistor 6, is connected to the collector of a second transistor 5 of the NPN type, the emitter of which leads to reference potential 0 and at the base of which a control potential 3 for control in the regular manner Operating case is connected. According to the invention, the base-collector path of the first transistor 4 is connected in parallel with a transistor 7 of the PNP type, which is operated as a diode by interconnecting the base and collector and is conducting in inverse operation.

FIG 2 zeigt das Ausführungsbeispiel nach FIG 1 dahingehend weitergebildet, daß der Kollektor eines dritten Transistors 20, dessen Emitter mit dem Kollektor und desen Basis mit der Basis des ersten Transistors 4 verbunden ist, mit der Basis eines vierten Transistors 8 vom PNP-Typ, der emitterseitig an dem ersten Potential 1 und kollektorseitig an der Basis des ersten Transistors 4 liegt, sowie mit einem zweiten und dritten Widerstand 9, 10 verschaltet ist, wobei der erste Widerstand 6 und der als Diode betriebene Transistor 7 aus FIG 1 entfallen. Der zweite Widerstand 9 ist auf das erste Potential 1 und der dritte Widerstand 10 auf den Kollektor eines fünften Transistors 11 vom NPN-Typ geführt, dessen Emitter auf Bezugspotential 0 liegt und dessen Basis mit dem Ausgang eines Komparators 12 verbunden ist. Der inver­tierende Eingang des Komparators 12 ist mit dem ersten Po­tential 1 und der nichtinvertierende Eingang mit einem Referenzpotential 13 beaufschlagt.2 shows the embodiment according to FIG. 1 to the extent that the collector of a third transistor 20, whose emitter is connected to the collector and whose base is connected to the base of the first transistor 4, with the base of a fourth transistor 8 of the PNP type, which is on the emitter side at the first potential 1 and on the collector side at the base of the first transistor 4, and is connected to a second and third resistor 9, 10, the first resistor 6 and the transistor 7 operated as a diode from FIG. 1 being omitted. The second resistor 9 is connected to the first potential 1 and the third resistor 10 to the collector of a fifth transistor 11 of the NPN type, the emitter of which is at reference potential 0 and the base of which is connected to the output of a comparator 12. The inverting input of the comparator 12 has the first potential 1 applied to it and the non-inverting input has a reference potential 13.

In FIG 3 der Zeichnung ist das Ausführungsbeispiel nach FIG 2 um einen sechsten Transistor 14 vom PNP-Typ, einen sieb­ten Transistor 15 vom PNP-Typ, einen achten Transistor 19 vom NPN-Typ sowie um einen vierten, fünften und sechsten Widerstand 16, 17, 18 erweitert. Der sechste Transistor 14, der emitterseitig an dem ersten Potential 1 und kollektor­seitig an der Basis des ersten Transistors 4 liegt, ist über seine Basis zum einen mit einem auf Bezugspotential 0 führenden sechsten Widerstand 18 und zum anderen mit dem Kollektor des emitterseitig an dem ersten Potential 1 an­geschlossenen siebten Transistors 15 verbunden. Die Basis des siebten Transistors 15 ist seinerseits mit einem auf das erste Potential 1 führenden vierten Widerstand 16 und mit einem an den Kollektor des achten Transistors 19 angeschlos­senen fünften Widerstand 17 verschaltet. Darüber hinaus ist ein zusätzlicher Kollektor des dritten Transistors 20 eben­falls mit der Basis des siebten Transistors 15 verbunden.In FIG. 3 of the drawing, the exemplary embodiment according to FIG. 2 is a sixth transistor 14 of the PNP type, a seventh transistor 15 of the PNP type, and an eighth transistor 19 of the NPN type and a fourth, fifth and sixth resistor 16, 17, 18 extended. The sixth transistor 14, which is on the emitter side at the first potential 1 and on the collector side at the base of the first transistor 4, is on the one hand with a sixth resistor 18 leading to reference potential 0 and on the other hand with the collector of the emitter side at the first potential 1 connected seventh transistor 15 connected. The base of the seventh transistor 15 is in turn connected to a fourth resistor 16 leading to the first potential 1 and to a fifth resistor 17 connected to the collector of the eighth transistor 19. In addition, an additional collector of the third transistor 20 is also connected to the base of the seventh transistor 15.

Die Basis des emitterseitig auf Bezugspotential 0 liegenden achten Transistors 19 ist ebenso wie bereits die Basis des fünften Transistors 11 an den Ausgang des Komparators 12 an­geschlossen.The base of the eighth transistor 19, which is at reference potential 0 on the emitter side, is connected to the output of the comparator 12, as is the base of the fifth transistor 11.

Durch die Vorgabe des jeweiligen Leitungstyps bei den Tran­sistoren in den Ausführungsbeispielen ergeben sich für das erste und zweite Potential 1, 2, das Referenzpotential 13, sowie das Ansteuerpotential 3 gegenüber dem Bezugspotential 0 jeweils positive Werte. Im regulären Betriebsfall weist dabei das erste Potential 1 einen höheren Wert auf als das zweite Potential 2.By specifying the respective line type for the transistors in the exemplary embodiments, positive values are obtained for the first and second potentials 1, 2, the reference potential 13 and the drive potential 3 with respect to the reference potential 0. In normal operation, the first potential 1 has a higher value than the second potential 2.

Nachdem zuvor der prinzipielle Aufbau der in den Figuren der Zeichnung dargestellten Ausführungsbeispiele erläutert wor­den ist, sei nunmehr auf deren Wirkungsweise näher einge­gangen.After the basic structure of the exemplary embodiments shown in the figures of the drawing has been explained, their mode of operation will now be discussed in more detail.

Beim Inversbetrieb des ersten Transistors 4, wenn also das zweite Potential 2 größer ist als das erste Potential 1, wirkt der Kollektor als Inversemitter und der Emitter als Inverskollektor. Da aber gemäß FIG 1 die Basis des ersten Transistors 4 über den ersten Widerstand 6 mit dem Invers­kollektor verbunden ist, wird der erste Transistor 4 invers durchgesteuert. Durch den als Diode betriebenen Transistor 7 wird jedoch der Basisstrom des ersten Transistors 4 soweit herabgesetzt, daß sich über die Inversstromverstärkung b₄ des ersten Transistors 4 eine Verringerung des Rückstromes IR ergibt.During the inverse operation of the first transistor 4, that is when the second potential 2 is greater than the first potential 1, the collector acts as an inverse emitter and the emitter as an inverse collector. However, since according to FIG If transistor 4 is connected to the inverse collector via the first resistor 6, the first transistor 4 is turned on inversely. Through the transistor 7 operated as a diode, however, the base current of the first transistor 4 is reduced to such an extent that the reverse current I R is reduced via the inverse current gain bstrom of the first transistor 4.

Zur Erhöhung der Spannungsfestigkeit des ersten Transistors 4 wird dieser, wie in FIG 2 gezeigt, bei einem zu hohen er­sten Potential 1 durch den vierten Transistor 8 geklemmt. Die Ansteuerung des vierten Transistors 8 erfolgt durch eine Überwachungsschaltung mit dem Komparator 12, der das erste Potential 1 mit dem Referenzpotential 13 vergleicht und bei einer unzulässigen Erhöhung des ersten Potentials 1 über den fünften Transistor 11 in Verbindung mit dem zwei­ten und dritten Widerstand 9, 10 den vierten Transistor 8 durchschaltet.To increase the dielectric strength of the first transistor 4, the latter is clamped by the fourth transistor 8 when the first potential 1 is too high, as shown in FIG. The fourth transistor 8 is activated by a monitoring circuit with the comparator 12, which compares the first potential 1 with the reference potential 13 and, in the event of an impermissible increase in the first potential 1, via the fifth transistor 11 in conjunction with the second and third resistors 9, 10 turns on the fourth transistor 8.

Für den Fall, daß das zweite Potential 2 höher ist als das erste Potential 1, sind der erste Transistor 4 und der vier­te Transistor 8 invers leitend. Für den Rückstrom IR ergibt sich in Abhängigkeit vom Basisstrom IB8 des vierten Transi­stors 8 sowie von den Inversstromverstärkungen b₄, b₈ von erstem und viertem Transistor 4, 8 folgender Zusammenhang: IR = IB8·(1 + b₄)·(1 + b₈)
Ohne Berücksichtigung des dritten Transistors 20 ist der Ba­sisstrom IB4 des vierten Transistors 4 gleich dem Quotienten aus der Spannung über dem zweiten Widerstand 9 und dessen Widerstandswert. Durch Hinzufügen des dritten Transistors 20 in der gezeigten Weise ergibt sich ein um den Betrag des Kollektorstromes des dritten Transistors 20 geringerer Ba­sisstrom IB8 für den vierten Transistor 8. Gemäß obiger Gleichung resultiert daraus ein geringerer Rückstrom IR, da der erste Transistor 4 weniger stark ausgesteuert wird. Der Vorteil besteht nun darin, daß zwei sich bisher widerspre­chende Forderungen an einen Ausgangstransistor, nämlich höhere Spannungsfestigkeit im Normalbetrieb und geringerer Rückstrom bei Inversbetrieb, unter Beibehaltung seiner elektrischen Eigenschaften im Normalbetrieb bei einer erfindungsgemäßen Schaltungsanordnung erfüllt werden.In the event that the second potential 2 is higher than the first potential 1, the first transistor 4 and the fourth transistor 8 are inversely conductive. For the reverse current I R , depending on the base current I B8 of the fourth transistor 8 and the inverse current gains b₄, b 4 of the first and fourth transistors 4, 8, the following relationship results: I R = I B8 · (1 + b₄) · (1 + b₈)
Without taking into account the third transistor 20, the base current I B4 of the fourth transistor 4 is equal to the quotient of the voltage across the second resistor 9 and its resistance value. Adding the third transistor 20 in the manner shown results in a base current I B8 for the fourth transistor 8 that is lower by the amount of the collector current of the third transistor 20. According to the above equation, this results in a lower reverse current I R , since the first transistor 4 is driven less. The advantage now lies in the fact that two previously contradicting requirements for an output transistor, namely higher dielectric strength in normal operation and lower reverse current in inverse operation, are met while maintaining its electrical properties in normal operation in a circuit arrangement according to the invention.

Das in FIG 3 dargestellte Ausführungsbeispiel enthält gegen­über FIG 2 eine zusätzliche Stufe mit sechstem Transistor 14, siebtem Transistor 15, achtem Transistor 17, sowie viertem, fünftem und sechstem Widerstand 16, 17, 18, welche im Normal­betrieb mittels des zwischen Emitter und Basis des ersten Transistors 4 liegenden sechsten Transistors 14 als aktiver Ausräumer wirkt, vergleichbar mit dem ersten Widerstand 6 aus FIG 1. Beim Auftreten eines zu hohen ersten Potentials 1 wird der sechste Transistor 14 durch den Komparator 12 und den nachfolgenden Schaltungsteil gesperrt, während der vier­te Transistor 8, ebenfalls durch den Komparator 12 angesteu­ert, den ersten Transistor 4 klemmt. Dadurch wird der erste Transistor 4 gesperrt, was zum einen dessen Spannungsfestig­keit erhöht und zum anderen eine höhere Stromverstärkung für den Normalbetrieb zuläßt. Eine höhere Stromverstärkung wiederum verbessert den Wirkungsgrad der Schaltungsanordnung. Bei Inversbetrieb sind sowohl der erste Transistor 4 als auch der vierte Transistor 8, der dritte Transistor 5 und der sechste Transistor 14 weitgehend gesperrt, wodurch sich nur ein sehr geringer Rückstrom IR ergibt. Der Vorteil die­ser Ausgestaltung einer erfindungsgemäßen Schaltungsanord­nung liegt also darin, daß neben einem geringen Rückstrom im Inversbetrieb eine erhöhte Spannungsfestigkeit bei höhe­rem Wirkungsgrad im Normalbetrieb erzielt wird.Compared to FIG. 2, the exemplary embodiment shown in FIG. 3 contains an additional stage with a sixth transistor 14, a seventh transistor 15, an eighth transistor 17, and a fourth, fifth and sixth resistor 16, 17, 18, which in normal operation are by means of the emitter and base of the first Sixth transistor 14 located in transistor 4 acts as an active scraper, comparable to the first resistor 6 from FIG. 1. If an excessively high first potential 1 occurs, the sixth transistor 14 is blocked by the comparator 12 and the subsequent circuit part, while the fourth transistor 8, also controlled by the comparator 12, the first transistor 4 clamps. As a result, the first transistor 4 is blocked, which on the one hand increases its dielectric strength and on the other hand allows a higher current gain for normal operation. A higher current gain in turn improves the efficiency of the circuit arrangement. In the case of inverse operation, both the first transistor 4 and the fourth transistor 8, the third transistor 5 and the sixth transistor 14 are largely blocked, as a result of which there is only a very low reverse current I R. The advantage of this embodiment of a circuit arrangement according to the invention is that, in addition to a low reverse current in inverse operation, increased dielectric strength is achieved with higher efficiency in normal operation.

Zweckmäßigerweise wird in Ausgestaltung der Erfindung ledig­lich jeweils eine weitere Diffussionsstruktur für den bzw. die Kollektoren des dritten Transistors 20 in die Schal­ tungsanordnung eingebracht. Als Basis des dritten Transi­stors 20 ist die Basis des ersten Transistors 4 und als Emitter der Kollektor des dritten Transistors 20 vorgesehen. Das bringt den Vorteil eines niedrigen Schaltungsaufwandes und eines geringeren Platzbedarfes mit sich.In an embodiment of the invention, it is expedient for only one further diffusion structure for the collector or collectors of the third transistor 20 into the scarf introduced arrangement. The base of the first transistor 4 is provided as the base of the third transistor 20 and the collector of the third transistor 20 is provided as the emitter. This has the advantage of low circuitry requirements and less space.

Abschließend sei bemerkt, daß die Überwachungsschaltung nicht nur auf eine Ausführungsform mit Komparator be­schränkt ist. Beispielsweise eignen sich auch Schaltungen mit Zenerdioden und/oder nichtlinearen Spannungsteilern.Finally, it should be noted that the monitoring circuit is not limited to only one embodiment with a comparator. For example, circuits with Zener diodes and / or non-linear voltage dividers are also suitable.

Claims (4)

1. Integrierbare Schaltungsanordnung mit einem ersten Tran­sistor (4) des einen Leitungstyps, dessen Emitter mit einem ersten Potential (1) und dessen Kollektor mit einem zweiten Potential (2) beaufschlagt ist, dessen Basis-Emitter-Strecke ein erster Widerstand (6) parallel geschaltet ist und dessen Basis zur Ansteuerung durch einen zweiten Transistor (5) des anderen Leitungstyps vorgesehen ist, dadurch ge­kennzeichnet, daß zur Rückstromverringerung für den Fall eines Inversbetriebs des ersten Transistors (4) dessen Basis-Kollektor-Strecke eine Diode (7) derart paral­lel geschaltet ist, daß diese bei Inversbetrieb leitend ist.1. Integrable circuit arrangement with a first transistor (4) of one conduction type, the emitter of which is acted upon by a first potential (1) and the collector of which is acted upon by a second potential (2), the base-emitter path of which has a first resistor (6) in parallel is switched and the base of which is intended to be controlled by a second transistor (5) of the other conduction type, characterized in that, in order to reduce the reverse current in the event of an inverse operation of the first transistor (4), its base-collector path has a diode (7) in parallel in this way is switched that this is conductive in reverse operation. 2. Schaltungsanordnung nach Anspruch 1, dadurch gekennzeichnet, daß ein mit seiner Emitter- ­Kollektor-Strecke der Emitter-Basis-Strecke des ersten Tran­sistors (4) parallel geschalteter vierter Transistor (8) des einen Leitungstyps basisseitig mit einer Überwachungsschal­tung (12, 13) direkt oder über weitere Schaltelemente der­art verbunden ist, daß beim Auftreten eines unzulässig hohen ersten Potentials (1) der vierte Transistor (8) durchgesteu­ert wird und daß der Basis-Kollektor-Strecke des ersten Tran­sistors (4) anstelle der Diode (7) die Basis-Emitter-Strecke eines dritten Transistors (20) des einen Leitungstyps paral­lel geschaltet ist, dessen Kollektor mit der Basis des vier­ten Transistors (8) verbunden ist.2. Circuit arrangement according to claim 1, characterized in that with its emitter-collector path of the emitter-base path of the first transistor (4) connected in parallel fourth transistor (8) of the one line type on the base side with a monitoring circuit (12, 13) is connected directly or via further switching elements such that when an impermissibly high first potential (1) occurs, the fourth transistor (8) is turned on and that the base-collector path of the first transistor (4) instead of the diode (7) is the base -Emitter path of a third transistor (20) of one conduction type is connected in parallel, the collector of which is connected to the base of the fourth transistor (8). 3. Schaltungsanordnung nach Anspruch 2, dadurch gekennzeichnet, daß ein mit seiner Emitter- ­Kollektor-Strecke der Emitter-Basis-Strecke des ersten Tran­sistors (4) parallel geschalteter weiterer Transistor (14) des einen Leitungstyps basisseitig direkt oder über weitere Schaltelemente mit der Überwachunsschaltung (12, 13) derart verbunden ist, daß der ansonsten in einem bestimmten Maße leitende weitere Transistor (14) beim Auftreten eines zu hohen ersten Potentials (1) gesperrt wird und daß ein weite­rer Kollektor des dritten Transistors (20) direkt oder über weitere Schaltelemente mit der Basis des weiteren Transi­stors (14) derart verbunden ist, daß der ansonsten in einem bestimmten Maße leitende weitere Transistor (14) gesperrt wird.3. Circuit arrangement according to claim 2, characterized in that one with its emitter-collector path of the emitter-base path of the first transistor (4) connected in parallel further transistor (14) of the one line type on the base side directly or via further switching elements with the monitoring circuit (12, 13) is connected in such a way that the further transistor (14), which is otherwise conductive to a certain degree, when a occurs high first potential (1) is blocked and that a further collector of the third transistor (20) is connected directly or via further switching elements to the base of the further transistor (14) in such a way that the further transistor (14) which is otherwise conductive to a certain extent is blocked. 4. Schaltungsanordnung nach einem der Ansprüche 1 bis 3, dadurch gekennzeichnet, daß für den dritten Transistor (7) die Basis des ersten Transistors (4) als Basis und der Kolektor des ersten Transistors (4) als Emitter zusammen mit jeweils einer weiteren Diffusionsstruk­tur als Kollektor bzw.Kollektoren vorgesehen sind.4. Circuit arrangement according to one of claims 1 to 3, characterized in that for the third transistor (7), the base of the first transistor (4) as the base and the colector of the first transistor (4) as an emitter together with a further diffusion structure as Collector or collectors are provided.
EP88121417A 1988-12-21 1988-12-21 Integrated circuit diminishing the inverse current of an inversely polarized transistor Expired - Lifetime EP0374288B1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AT88121417T ATE112868T1 (en) 1988-12-21 1988-12-21 INTEGRABLE CIRCUIT ARRANGEMENT FOR REVERSE CURRENT REDUCTION IN AN INVERSE TRANSISTOR.
DE3851839T DE3851839D1 (en) 1988-12-21 1988-12-21 Integrable circuit arrangement for reducing the reverse current in an inversely operated transistor.
EP88121417A EP0374288B1 (en) 1988-12-21 1988-12-21 Integrated circuit diminishing the inverse current of an inversely polarized transistor
US07/455,553 US4945444A (en) 1988-12-21 1989-12-18 Integratable circuit configuration for reverse current reduction in an inversely operated transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP88121417A EP0374288B1 (en) 1988-12-21 1988-12-21 Integrated circuit diminishing the inverse current of an inversely polarized transistor

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EP0374288A1 true EP0374288A1 (en) 1990-06-27
EP0374288B1 EP0374288B1 (en) 1994-10-12

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JP3272298B2 (en) * 1998-04-27 2002-04-08 インターナショナル・ビジネス・マシーンズ・コーポレーション Switch circuit having discharge circuit and electronic device
US6675304B1 (en) * 1999-11-29 2004-01-06 Intel Corporation System for transitioning a processor from a higher to a lower activity state by switching in and out of an impedance on the voltage regulator
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Also Published As

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EP0374288B1 (en) 1994-10-12
DE3851839D1 (en) 1994-11-17
ATE112868T1 (en) 1994-10-15
US4945444A (en) 1990-07-31

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