EP0374288B1 - Integrated circuit diminishing the inverse current of an inversely polarized transistor - Google Patents

Abstract

An integratable circuit configuration includes a first transistor of one conduction type having an emitter being acted upon by a first potential, a collector being acted upon by a second potential, a base, a base-to-collector path and a base-to-emitter path. A resistor is connected in parallel with the base-to-emitter path of the first transistor. A second transistor of the other conduction type is connected to the base of the first transistor for triggering. A diode may be connected in parallel with the base-to-collector path of the first transistor. The diode conducts in inverse operation for reverse current reduction during inverse operation of the first transistor. A third transistor may be connected to the first transistor instead of the diode and fourth and further transistors may also be connected to the first transistor.

Description

The present invention relates to a circuit arrangement according to the preamble of patent claim 1.

If, for example, amplifiers or voltage regulators are operated with a capacitive load and the supply voltage collapses in the meantime, the voltage at the output is much higher than for the supply voltage. With voltage regulators in general, the outputs are usually wired with smoothing capacitors, i.e. Voltage regulators are usually operated with a capacitive load. For example, in the event of a short circuit at the input of a low-dropout voltage regulator - caused, for example, by switching off the voltage supply at which other consumers are connected - the voltage at the input of the voltage regulator goes to zero, while at the output the voltage is initially maintained by the smoothing capacitors. As a result, a current flows in the opposite direction to the original direction, also called reverse current, which can lead to a functional impairment or even destruction of the voltage regulator, since the output transistor of the voltage regulator switches through from the output to the input of the voltage regulator in this operating mode, hereinafter referred to as inverse operation .

From Electronic Engineering, Vol. 44, No. 535, September 1972, London GB, pages 61-63 is a protective measure specified an npn transistor. However, no measures for reducing the reverse current in an inversely operated pnp transistor result from it. Further protective measures are available, for example, from Patent abstract of Japan, Vol. 9, No. 44, (P-337) (1767), February 23, 1985 JP-A-59 183 419.

In a low-dropout voltage regulator known, for example, from "Sanken New Products Information, Low-Dropout Hybrid Voltage Regulator, Sanken Electric Company", an external diode is connected between the output and input of the voltage regulator as protection in the case of inverse operation such that it blocks in normal operation and in Inverse operation is leading. The return current is thus carried in whole or in part via the diode. The disadvantage of this, however, is that the smoothing capacitor is again discharged quickly, just as when operating without a diode, and therefore the voltage at the output of the voltage regulator drops rapidly. However, this is particularly undesirable in the case of power supplies for microcomputer systems.

The object of the invention is to provide a circuit arrangement which at least reduces the reverse current of an inversely operated transistor.

The object is achieved in a generic circuit arrangement by the characterizing features of claim 1. Further developments and refinements of the inventive concept are characterized in the subclaims.

The advantage of the invention is that due to the almost complete blocking of the transistor in inverse operation, only a small reverse current flows and the transistor itself is protected against functional impairments or destruction. This is particularly advantageous when used as an output transistor of a low-dropout voltage regulator, since the voltage at the output drops more slowly.

FIG 1

eine erste Ausführungsform einer erfindungsgemäßen Schaltungsanordnung;

FIG 2

eine zweite, weitergebildete Ausführungsform einer erfindungsgemäßen Schaltungsanordnung mit höherer Spannungsfestigkeit;

FIG 3

eine Weiterbildung der Ausführungsform nach FIG 2.

The invention is explained in more detail below on the basis of the exemplary embodiments illustrated in the figures of the drawing, the same elements being provided with the same reference symbols. It shows:

FIG. 1

a first embodiment of a circuit arrangement according to the invention;

FIG 2

a second, further developed embodiment of a circuit arrangement according to the invention with higher dielectric strength;

FIG 3

a further development of the embodiment according to FIG. 2.

The exemplary embodiment according to FIG. 1 shows a conventional output stage of a low-dropout voltage regulator with a first transistor 4 of the PNP type, the emitter of which is acted upon by a first potential 1 and the collector of which is acted upon by a second potential 2. The base of the first transistor 4, whose base-emitter path is parallel to a resistor 6, is connected to the collector of a second transistor 5 of the NPN type, the emitter of which leads to reference potential 0 and at the base of which a control potential 3 for control in the regular manner Operating case is connected. According to the invention, the base-collector path of the first transistor 4 is connected in parallel with a transistor 7 of the PNP type, which is operated as a diode by interconnecting the base and collector and is conductive in inverse operation.

2 shows the embodiment according to FIG. 1 in such a way that the collector of a third transistor 20, whose emitter is connected to the collector and whose base is connected to the base of the first transistor 4, with the base of a fourth transistor 8 of the PNP type, which is on the emitter side at the first potential 1 and on the collector side at the base of the first transistor 4, and is connected to a second and third resistor 9, 10, the first resistor 6 and the transistor 7 operated as a diode from FIG. 1 being eliminated. The second resistor 9 is connected to the first potential 1 and the third resistor 10 to the collector of a fifth transistor 11 of the NPN type, the emitter of which is at reference potential O and the base of which is connected to the output of a comparator 12. The inverting input of the comparator 12 is supplied with the first potential 1 and the non-inverting input with a reference potential 13.

In FIG. 3 of the drawing, the exemplary embodiment according to FIG. 2 is a sixth transistor 14 of the PNP type, a seventh transistor 15 of the PNP type, and an eighth transistor 19 of the NPN type as well as a fourth, fifth and sixth resistor 16, 17, 18. The sixth transistor 14, which is on the emitter side at the first potential 1 and on the collector side at the base of the first transistor 4, is on the one hand with a sixth resistor 18 leading to reference potential 0 and on the other hand with the collector of the emitter side at the first potential 1 connected seventh transistor 15 connected. The base of the seventh transistor 15 is in turn connected to a fourth resistor 16 leading to the first potential 1 and to a fifth resistor 17 connected to the collector of the eighth transistor 19. In addition, an additional collector of the third transistor 20 is also connected to the base of the seventh transistor 15. The base of the eighth transistor 19 lying on the emitter side at reference potential 0, like the base of the fifth transistor 11, is connected to the output of the comparator 12.

By specifying the respective conduction type for the transistors in the exemplary embodiments, positive values are obtained for the first and second potentials 1, 2, the reference potential 13 and the drive potential 3 with respect to the reference potential 0. In normal operation, the first potential 1 has a higher value than the second potential 2.

After the basic structure of the exemplary embodiments shown in the figures of the drawing has been explained, their mode of operation will now be discussed in more detail.

During the inverse operation of the first transistor 4, that is when the second potential 2 is greater than the first potential 1, the collector acts as an inverse emitter and the emitter as an inverse collector. But since according to FIG 1 the basis of the first If transistor 4 is connected to the inverse collector via the first resistor 6, the first transistor 4 is turned on inversely. Through the transistor 7 operated as a diode, however, the base current of the first transistor 4 is reduced to such an extent that the reverse current I _R is reduced via the inverse current gain b₄ of the first transistor 4.

To increase the dielectric strength of the first transistor 4, the latter is clamped by the fourth transistor 8 when the first potential 1 is too high, as shown in FIG. The fourth transistor 8 is activated by a monitoring circuit with the comparator 12, which compares the first potential 1 with the reference potential 13 and, in the event of an impermissible increase in the first potential 1, via the fifth transistor 11 in conjunction with the second and third resistors 9, 10 turns on the fourth transistor 8.

In the event that the second potential 2 is higher than the first potential 1, the first transistor 4 and the fourth transistor 8 are inversely conductive. Depending on the base current I _{B8 of} the fourth transistor 8 and the inverse current amplifications b₄, b₈ of the first and fourth transistor 4, 8, the following relationship results for the reverse current I _R : $${\text{I.}}_{\text{R}}{\text{= I}}_{\text{B8}}\text{· (1 + b₄) · (1 + b₈)}$$

Without taking into account the third transistor 20, the base current I _{B4 of} the fourth transistor 4 is equal to the quotient of the voltage across the second resistor 9 and its resistance value. Adding the third transistor 20 in the manner shown results in a base current I _B8 for the fourth transistor 8 that is lower by the amount of the collector current of the third transistor 20. According to the above equation, this results in a lower reverse current I _R , since the first transistor 4 is driven less. The advantage now lies in the fact that two previously contradictory requirements for an output transistor, namely higher dielectric strength in normal operation and lower reverse current in inverse operation, are met while maintaining its electrical properties in normal operation in a circuit arrangement according to the invention.

Compared to FIG. 2, the exemplary embodiment shown in FIG. 3 contains an additional stage with a sixth transistor 14, a seventh transistor 15, an eighth transistor 17, and a fourth, fifth and sixth resistor 16, 17, 18, which in normal operation are by means of the emitter and base of the first Sixth transistor 14 located in transistor 4 acts as an active scraper, comparable to the first resistor 6 from FIG. 1. If an excessively high first potential 1 occurs, the sixth transistor 14 is blocked by the comparator 12 and the subsequent circuit part, while the fourth transistor 8, also controlled by the comparator 12, the first transistor 4 clamps. As a result, the first transistor 4 is blocked, which on the one hand increases its dielectric strength and on the other hand allows a higher current gain for normal operation. A higher current gain in turn improves the efficiency of the circuit arrangement. In the case of inverse operation, both the first transistor 4 and the fourth transistor 8, the third transistor 5 and the sixth transistor 14 are largely blocked, as a result of which only a very low reverse current I _R results. The advantage of this embodiment of a circuit arrangement according to the invention is that, in addition to a low reverse current in inverse operation, an increased dielectric strength is achieved with higher efficiency in normal operation.

In an embodiment of the invention, only one further diffusion structure for the collector or collectors of the third transistor 20 is expediently incorporated into the circuit arrangement brought in. The base of the first transistor 4 is provided as the base of the third transistor 20 and the collector of the third transistor 20 is provided as the emitter. This has the advantage of low circuitry and less space.

Finally, it should be noted that the monitoring circuit is not limited to an embodiment with a comparator. For example, circuits with Zener diodes and / or non-linear voltage dividers are also suitable.

Claims (4)

1. Integrable circuit arrangement having a first transistor (4) of the p-conduction type to whose emitter a first potential (1) is applied and to whose collector a second potential (2) is applied, in parallel with whose base/emitter path a first resistor (6) is connected and whose base is provided, for the purpose of drive, with a second transistor (5) of the n-conduction type, characterized in that, to reduce the reverse current in the case of inverse operation of the first transistor (4), a diode (7) is connected in parallel with its base/collector path in such a way that the latter is conducting during inverse operation.
2. Circuit arrangement according to Claim 1, characterized in that the base of a fourth transistor (8) of the one conduction type whose emitter/collector path is connected in parallel with the emitter/base path of the first transistor (4) is connected, directly or via further switching elements, to a monitoring circuit (12, 13) in such a way that, if an unacceptably high first potential (1) occurs, the fourth transistor (8) is turned on, and in that, instead of the diode (7), the base/emitter path of a third transistor (20) of the one conduction type is connected in parallel with the base/collector path of the first transistor (4), the collector of the third transistor (20) being connected to the base of the fourth transistor (8).
3. Circuit arrangement according to Claim 2, characterized in that the base of a further transistor (14) of the one conduction type whose emitter/collector path is connected in parallel with the emitter/base path of the first transistor (4) is connected, directly or via further switching elements, to the monitoring circuit (12, 13) in such a way that, if an unduly high first potential (1) occurs, the further transistor (14), which is otherwise conducting to a certain extent, is turned off, and in that a further collector of the third transistor (20) is connected, directly or via further switching elements, to the base of the further transistor (14) in such a way that the further transistor (14), which is otherwise conducting to a certain extent, is turned off.
4. Circuit arrangement according to one of Claims 1 to 3, characterized in that, for the third transistor (7) the base of the first transistor (4) is provided as base and the collector of the first transistor (4) as emitter, together with a further diffusion structure as collector or collectors in each case.

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