EP0604485B1 - Device for generating intermediate voltages - Google Patents

Abstract

The proposal is for a device for generating intermediate voltages and a preferred use of the device of the invention. The device of the invention makes it possible to emit, with low dissipation losses and good dynamic stability over a wide range of externally applied voltages (Vpos, Vneg), intermediate voltages the values of which lie between those of the externally applied voltages. In a first version, the device of the invention emits an intermediate voltage with a value lying between those of externally applied voltages Vpos, Vneg, and which is generated by means of a current through a Zener block powered by a controllable current source. The current source is controlled dependently upon comparison values obtained from a comparison between a reference voltage and a falling voltage at a component connected in series with the Zener block and the current source. In the preferred use of the device of the invention, the voltages generated are preferably applied to an integrated circuit, or more precisely to individual diffusion regions, thus improving the dielectric strength of the integrated circuit.

Description

The invention relates to a device for generating an intermediate voltage according to the preamble of the main claim and a preferred use according to the preamble of the first use claim.

For certain circuit applications, it is necessary that, in addition to the maximum positive and negative voltages applied from the outside, intermediate voltages with predetermined intermediate values are available. This can be the case, for example, for circuitry reasons.

It is also generally known that semiconductor components are designed for certain reverse voltages due to the manufacturing process used. This means that voltage differences within a component that was produced using such a manufacturing process must not exceed the corresponding reverse voltage values.

This applies, for example, in the case of a bipolar npn transistor which is manufactured using integrated technology, in particular for the differences in voltages which exist between its base region, its insulation / substrate connection and its collector connection, i.e. its epitaxial regions.

The structure of semiconductor components is known and will not be discussed further at this point.

Furthermore, a circuit arrangement of two constant voltages is known from DE-A-2 437 700.

Previously known systems which emit intermediate voltages over a wide range of externally applied voltages, the values of which lie between those of the externally applied voltages, can be implemented, for example, as voltage dividers be. However, they are characterized by a relatively high power loss or by a low dynamic stability, for example by capacitive coupling between epitaxial regions and the substrate.

It is therefore an object of the present invention to implement a circuit which, with low power loss and good dynamic stability, emits intermediate voltages over a wide range of externally applied voltages (Vpos, Vneg), the values of which lie between those of the externally applied voltages.

This object is achieved by the device according to the features of the main claim.

According to the invention, a circuit is presented which can be implemented as part of an integrated circuit and whose power loss is below a predetermined value.

The following is essential in the present invention. If a DC voltage is applied to the device according to the invention, the absolute value of which increases, the intermediate voltage will initially decrease with respect to the positive potential of the DC voltage.

Depending on the absolute value of the DC voltage applied from the outside, a current is controlled by an arrangement of semiconductor components which essentially implement the effect of a Zener diode in such a way that the intermediate voltage does not fall below a predetermined value, i.e. amount does not exceed the specified value.

The intermediate voltage generated according to the invention can be used to implement desired circuit functions.

On the other hand, the device according to the invention also allows the potential of connections of a component, for example of the substrate connection of a bipolar npn transistor, to such a value that the voltage differences between the individual regions of the component do not exceed predetermined values.

It is important to note that all circuit parts that are operated potentially below the intermediate voltage, with their epitaxial areas (collector for an npn transistor, base for a pnp transistor, and epitaxial tub for resistors) are potentially above or at most on the intermediate voltage.

This means that externally applied voltages can be processed by integrated circuit arrangements which have values above the reverse voltage values specified by a manufacturing process used. On the one hand, this has the advantage that a manufacturing process with greater integration density can be used. On the other hand, the operational safety of the integrated circuit arrangement under consideration increases.

If the device according to the invention is realized as part of the integrated circuit which also contains the circuit arrangement to which the intermediate voltage is to be made available, there is the further advantage that additional connection means, such as housing connections or bond connections, can be dispensed with.

If the device according to the invention is interconnected with a step circuit, for example a cascode circuit, the result is a voltage-proof output stage for controlling further stages.

Exemplary embodiments are shown in the drawing and are described in more detail below.

• Figur 1 ein erstes Ausführungsbeispiel der vorliegenden Erfindung,
• Figur 2 Spannungsverläufe bei dem Ausführungsbeispiel gemäß Figur 1,
• Figur 3 ein zweites Ausführungsbeispiel der vorliegenden Erfindung,
• Figur 4 das Ausführungsbeispiel der Figur 3 mit zusätzlichen Schaltungsblöcken,
• Figur 5 ein bevorzugtes Anwendungsbeispiel für die Anordnung nach Figur 4.

Show it

• FIG. 1 shows a first exemplary embodiment of the present invention,
• FIG. 2 voltage curves in the exemplary embodiment according to FIG. 1,
• FIG. 3 shows a second exemplary embodiment of the present invention,
• FIG. 4 the embodiment of FIG. 3 with additional circuit blocks,
• FIG. 5 shows a preferred application example for the arrangement according to FIG. 4.

Before the description of the exemplary embodiments is discussed in more detail, it should be pointed out that the blocks shown individually in the figures serve only for a better understanding of the invention. Usually, one or more of these blocks are combined into units. However, it is also possible that the devices and elements contained in the individual stages can be carried out separately.

The exemplary embodiment according to FIG. 1 has a first connection terminal 20, to which a positive voltage Vpos is applied, and which is connected to a first connection of a voltage source 21 and a first end of a resistor 22. For the sake of completeness, it should be mentioned that Vpos has a potential with the represents the highest value occurring in the circuit arrangement under consideration. In relation to a ground connection or to another potential, such as Vneg, which represents the potential with the lowest value occurring in the circuit arrangement under consideration, the term “voltage” is also to be understood for other potentials.

The second end of the resistor 22 is connected to a first input 23 of a comparison stage 24. A second The input 25 of the comparison stage 24 is connected to a second connection of the voltage source 21. The second end of the resistor 22 and the first input 23 of the comparison stage 24 are connected to the cathode of a Zener diode 26. The anode of this zener diode 26 is connected to a second connection terminal 27 and to a first input of a current source 28. The second connection of this current source 28 is connected to a third connection terminal 29, and a control input of the current source 28 is connected to the output of the comparison stage 24. An intermediate voltage Vzw is available at the second connection terminal 27 and the negative voltage Vneg is applied to the third connection terminal 29.

The function of the device according to the invention is explained with the aid of FIG. 2. There, the value of the voltage difference Vpos - Vneg and the value of the voltage difference Vpos - Vzw are plotted with a solid line as a function of time.

If the positive component of a DC voltage is applied to the first connection terminal 20 and the negative component of this DC voltage is applied to the third connection terminal 29, and the absolute value of this DC voltage continues to increase over time, the resistor 22, the Zener diode 26 and the current source 28 flow in Current to the third terminal 29.

At lower voltage values, the Zener diode 26 initially blocks, so that only a very small current flows through the resistor 22 and thus only a small voltage drops across it. At higher voltage values, that is to say above the breakdown voltage of the zener diode 26, the latter becomes conductive and a substantially larger current flows through it, through the resistor 22 and through the current source 28, the value of which is predetermined by the current source 28. The value of the intermediate voltage Vzw essentially corresponds to the negative voltage Vneg, ie except for the saturation voltage of the current source 28.

This also means that a voltage drops across the resistor 22, the value of which is higher than that of a voltage specified by the voltage source 21. The voltage source 21 can be viewed as a setpoint stage, the voltage it outputs as a setpoint voltage, or generally as a setpoint signal, and its value as a setpoint.

The comparison stage 24 recognizes that the voltage drop across the resistor is higher than the target voltage, and then outputs a control signal to the current source 28 so that it regulates back the current impressed by it. This sets a current value in such a way that the intermediate voltage Vzw essentially corresponds to the zener diode blocking voltage and the voltage dropping across the resistor 22 corresponds to the voltage output by the voltage source 21.

A second embodiment of the invention is shown in Figure 3. Components were grouped together according to their function. Means, components and assemblies that perform the same function as corresponding means of the embodiment of FIG. 1 have been given the same reference numerals and will be dealt with in the following only to the extent that it is important for the understanding of the present invention.

The voltage Vpos present at the first connection terminal 20 is forwarded via the resistor 22 to the first input 23 of the comparison stage 24. The comparison stage 24 contains a first comparison transistor 24a, a second comparison transistor 24b and a comparison resistor 24c connected to the emitter of the first comparison transistor 24a with a first end, the second end of which leads to the first input 23.

The collector of the first comparison transistor 24a is connected to the emitter of the second comparison transistor 24b and its collector forms the output of the comparison stage 24. The base of the second comparison transistor 24b is connected to the second connection terminal 27, to which the intermediate voltage Vzw is applied. The transistors 24a, 24b thus form a cascode stage.

The first input 23 and the first connection terminal 20 are also connected to a first Zener block 26 ', the function of which corresponds to that of the Zener diode 26. This block 26 'contains Zener transistors 26a, ..., 26e, and a Zener resistor 26f.

A capacitor 31 for frequency response compensation is arranged between the second connection terminal 27 and the output of the comparison stage 24.

The current source 28 is formed by a Darlington stage, consisting of a first current source transistor 28a, a second current source transistor 28b and suitable current source resistors 28c, 28d.

entspricht, wobei

Vzt

der Zenerspannung der Zenertransistoren 26a, ... 26d und

V_BE

der Basis-Emitter-Spannung des Transistors 26e entspricht.

The function of the exemplary embodiment according to FIG. 3 essentially corresponds to that of the exemplary embodiment according to FIG. 1. However, it should be noted that the Zener block 26 'realizes a Zener voltage Vz due to the selected circuit arrangement, which value $${\text{Vz = 4 ∗ Vzt + V}}_{\text{BE}}$$

corresponds, whereby

Vzt

the Zener voltage of the Zener transistors 26a, ... 26d and

V _BE

corresponds to the base-emitter voltage of transistor 26e.

If the number of Zener transistors is different, change the factor "4" accordingly.

Furthermore, it should be mentioned that by applying the intermediate voltage Vzw to the base of the second comparison transistor 24b in the two pnp transistors 24a, 24b, which form a cascode stage, the reverse voltage V _{CEO is} not exceeded.

Further possible variants of the exemplary embodiments mentioned can contain at least some of the stages which are indicated in FIG. 4.

In addition to these additional stages, the blocks and components already mentioned are shown in FIG. 4. However, they will only be dealt with in the following to the extent necessary for the understanding of the present invention.

In addition to the stages already mentioned, FIG. 4 connects to the current source 28, the anode of a second Zener block 32, which contains Zener transistors 32a,... 32d, and to the connection terminal 27 of the cathode thereof.

begrenzen. Dabei muß beachtet werden, daß der Strom durch die Schaltungsanordnung vorgegebene Werte nicht überschreitet.This zener block 32 represents a protective circuit in the event that the externally applied voltage (Vpos, Vneg) exceeds predetermined values. In this exemplary embodiment, the circuit arrangement according to the invention would act as a Zener diode and the voltage applied to the connecting terminals 20, 29 would have a value of $${\text{8 ∗ Vzt + 2 ∗ V}}_{\text{BE}}$$

limit. It must be ensured that the current through the circuit arrangement does not exceed predetermined values.

In a further variant, a third Zener block 33 is provided, the anode of which is connected to the third terminal 29 and the cathode of which is connected to a fourth terminal 34 and a current mirror 35. A voltage Vepi is output to the fourth terminal 34, the value of which is 5 ∗ Vz above the voltage Vneg. The third zener block 33 is supplied with a small current by the current mirror 35, which contains two transistors 35a, 35b and resistors 35c, 35d.

The voltage Vepi is of particular interest when the voltages emitted serve to avoid voltage difference values on a component, such as a resistor, which are above permissible values (V _CBO ). Such an application will be discussed further below.

In addition, a bias voltage stage 36 can be provided in the circuit arrangement according to the invention, which outputs a bias voltage Vvs with a predetermined value, for example V _BE + 0.6 volt, based on the intermediate voltage Vzw, to a fourth connection terminal 37.

The output voltages generated by the device according to the invention, such as the intermediate voltage Vzw, the voltage Vepi, the bias voltage Vvs, are preferably used to make a further circuit arrangement more voltage-resistant than the voltages Vpos, Vneg applied from the outside.

A possible downstream circuit arrangement which, on the one hand, brings the full voltage swing (Vpos, Vneg) to its output terminals and, on the other hand, is implemented in an integrated form and whose manufacturing process is designed for reverse voltages which are below the voltage difference Vpos - Vneg is indicated in FIG. 5 .

A cascode stage consisting of a first cascode transistor 41 and a second cascode transistor 42 is shown there. The collector of the first cascode transistor 41 is connected to a first end of a collector resistor 43, the second end of which leads to a first supply connection 44, to which the voltage Vpos is applied. The first Supply terminal 44 is also connected to the emitter of a first driver transistor 45, the base of which leads to a cascode input terminal 46.

The collector of the first driver transistor 45 is connected to the emitter of a second driver transistor 47, the base of the first cascode transistor 41 and the base of a further transistor 48, which is also connected to the collector of the transistor 48. Its emitter is connected on the one hand to a second supply connection 49 and to an input of a current mirror 50. Its output leads to the base of the second driver transistor 47, the collector of which is connected to the base of the second cascode transistor 42 and to a first end of a resistor 51, the second end of which leads to the emitter of the transistor 42. Furthermore, the emitter of transistor 42 is connected to an output terminal 52, at which an output voltage V out dependent on the input voltage V in is provided, and to a first end of an emitter resistor 53, which is formed from a series connection of resistors 53 a and 53 b, and the second end thereof End leads to a third supply terminal 54 to which the negative voltage Vneg is applied.

The resistors 53a, 53b are, as is customary in an integrated circuit, designed in such a way that regions of a basic diffusion which are embedded in an epitaxial tub, also called a "box", determine the electrical values of the respective resistor.

The epitaxial well 55 of the resistor 53b is electrically connected to a fourth supply terminal 56, to which the voltage Vepi is applied.

To the ground of the circuit arrangement according to FIG. 5, which, as is usual with an integrated circuit, with the substrate / insulation connection is identical, the intermediate voltage Vzw is applied via the fifth supply connection 57.

Folgende Gesichtspunkte sind bei der Schaltungsanordnung gemäß Figur 5 besonders wesentlich.The intermediate voltage Vvz preferably has a value that is essentially half of the voltages Vpos and Vneg, ie $$\text{Vvz = 1/2 (Vpos - Vneg).}$$

The following aspects are particularly important in the circuit arrangement according to FIG. 5.

Since the output voltage Vout can also assume values that essentially correspond to Vpos, a voltage difference of approximately Vpos-Vneg is then applied to the emitter resistor 53. As assumed, this voltage difference lies above the permissible reverse voltage values, such as V _{CBO, which are} predetermined by the manufacturing process.

So that the emitter resistor 53 can still process the voltage difference in the manufacturing process used, it is divided into the two resistors 53a and 53b, which have the same resistance values in this exemplary embodiment. This causes a voltage drop across both resistors that corresponds to half the voltage difference value (Vpos-Vneg). In order to ensure that the epitaxial well 55 of the resistor 53b is at a voltage value which is at an allowable distance from both the voltage Vpos and the voltage Vneg, it is set to a potential corresponding to the voltage Vepi. The voltage Vepi is chosen so that on the one hand the difference to the voltages Vpos and Vneg is not too high and on the other hand their value is not below the intermediate voltage Vzw which is applied to the substrate.

It is also essential that the collector connection and thus the epitaxial well of the second cascode transistor 42 a voltage is present which has a value which is above or equal to that of the substrate voltage Vzw. This is achieved by the bias voltage Vvs which is present at the second supply connection 49 and which is led via the base-emitter diodes of the transistors 48, 41 to the collector connection of the transistor 42, where it has a value greater than that of the substrate voltage. As a result, parasitic effects, such as the ignition of a parasitic triac, consisting of the substrate, the epitaxial region of transistor 42, the base of transistor 42 and the emitter of transistor 42, can be avoided.

A variant of the circuit arrangement of FIG. 5 described so far can contain a fourth zener block 58, as shown in broken lines in FIG. This has a similar structure to the Zener blocks already described and consists of four Zener transistors 58a, ..., 58d.

The fourth zener block limits a voltage difference between the collector and the base region of the transistor 42 to a value of 4 * Vzt, where Vzt corresponds to the Zener voltage of the transistors 58a, ..., 58d.

At this point, however, it should be pointed out again that the use of the device according to the invention for generating an intermediate voltage is not limited to increasing the dielectric strength of an integrated circuit, but that this is merely a preferred application.

On the other hand, the intermediate voltages that increase the dielectric strength of a component, such as an integrated circuit, can also be output by other suitable devices.

Overall, a device for generating intermediate voltages and a preferred application of the device according to the invention are thus presented.

In a first version, the device according to the invention emits an intermediate voltage, the value of which lies between the voltages Vpos, Vneg applied from the outside and which is generated by a current through an arrangement of components which perform the function of a Zener diode (Zener diode 26; Zener block 26 ' ), which is impressed by a controllable current source. The current source is controlled in dependence on comparison values which result from a comparison of a nominal voltage (nominal value) with a voltage dropping at a component which is connected in series with the Zener diode (or the Zener block) and the current source.

Further versions of the device according to the invention contain further components and blocks, as a result of which additional voltages are generated, the values of which lie between those of the voltages Vpos, Vneg applied externally.

The device according to the invention is characterized by good dynamic stability with low power loss.

In a preferred use of the device according to the invention, the voltages generated are preferably applied to a circuit arrangement implemented using integrated technology, more precisely to individual diffusion regions, which increases the dielectric strength of the integrated circuit.

To increase the dielectric strength, both individual stages, which are part of the device for generating intermediate voltages, and downstream stages, are implemented accordingly, for example by cascading or series connection of resistors.

Both for the individual stages of the device for generating intermediate voltages and for the downstream stages (components), it should be noted that all circuit parts that are operated potentially below the intermediate voltage Vzw have the corresponding epitaxial regions (collector with npn transistors, base with pnp transistors, and box for resistor) are potentially above or at most on the intermediate voltage Vzw.

Claims (10)

1. Device for producing an intermediate voltage (Vzw) whose voltage value lies between a first applied voltage (Vpos) and a second, lower applied voltage (Vneg), wherein
   means (22, 26; or 26') are provided which incorporate the function of a Zener diode when connected in series and which, on the one hand, emit a signal to a first input (23) of a comparator stage (24) in dependence on the value of the difference between the applied voltages (Vpos, Vneg) and through which, on the other hand, a current flows whose value is dependent on the difference between the applied voltages (Vpos, Vneg) and which is determined by a current source (28) that is controlled by an output signal from the comparator stage (24) upon the second input (25) of which there is a reference signal supplied by a reference value stage (21) and which compares the signal emitted by the means (22, 26; or 26') with the reference signal and the intermediate voltage produced (Vzw) is available from the voltage drop on the means (22, 26; or 26').
2. Device in accordance with Claim 1, characterised in that, it is constructed as part of an integrated circuit.
3. Device in accordance with either of Claims 1 or 2, characterised in that, the means (22, 26; or 26') which emit a signal in dependence on the value of the difference between the applied voltages (Vpos, Vneg) include first means

   - which implement the function of a Zener diode having a predetermined threshold voltage (26; 26') and also further means

   - which (22) with the first means (26; 26') through which a current flows [sic], whereby a voltage is produced whose value provides a measure for the signal emitted by the means (22, 26; or 26') to the first input (23) of the comparator stage (24).
4. Device in accordance with any of the Claims 1 - 3, characterised in that, further means are provided which produce further voltages (Vepi, Vvs) whose values lies between those of the applied voltages (Vpos, Vneg) and which differ by predetermined values from the value of the intermediate voltage (Vzw) or the value of one of the applied voltages (Vpos, Vneg).
5. Device in accordance with any of the Claims 1 - 4, characterised in that, at least some of its stages (24) are constructed as cascode stages and that the potential does not lie below the intermediate voltage (Vzw) in any of its epitaxial regions.
6. Device in accordance with any of the Claims 1 - 5, characterised in that, one of the voltages (Vzw, Vepi, Vvs) that has been produced is applied to the diffusion regions of some of its components (24b) so that the voltage rating of the corresponding stage is increased.
7. The use of the device in accordance with any of the Claims 1 - 6, characterised in that, the intermediate voltage (Vzw) is applied to the diffusion regions of a semiconductor component so that this semiconductor component can handle applied voltages whose difference in value exceeds the blocking voltage values determined by virtue of a manufacturing process.
8. The use of the device in accordance with any of the Claims 1 - 6, in accordance with Claim 7, characterised in that, the intermediate voltage (Vzw) is connected to an isolating-/substrate terminal of an integrated circuit.
9. The use of the device in accordance with any of the Claims 1 - 6, in accordance with either of the Claims 7 or 8, characterised in that, the further voltages (Vepi, Vvs) are connected to further diffusion regions of the semiconductor component so that, on the one hand, the voltage differences between the further diffusion regions are reduced and that, on the other hand, any parasitic effects are avoided.
10. The use of the device in accordance with any of the Claims 1 - 6, in accordance with either of the Claims 8 or 9, characterised in that, at least some of the stages of a subsequently connected circuit are implemented as cascode stages (41, 42) and that in their case, the potential on any of their epitaxial regions does not lie below the intermediate voltage (Vzw).

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