EP0814396B1 - Circuit for generating a voltage reference - Google Patents

Circuit for generating a voltage reference Download PDF

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Publication number
EP0814396B1
EP0814396B1 EP97109351A EP97109351A EP0814396B1 EP 0814396 B1 EP0814396 B1 EP 0814396B1 EP 97109351 A EP97109351 A EP 97109351A EP 97109351 A EP97109351 A EP 97109351A EP 0814396 B1 EP0814396 B1 EP 0814396B1
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EP
European Patent Office
Prior art keywords
transistor
whose
base
collector
emitter
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EP97109351A
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German (de)
French (fr)
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EP0814396A3 (en
EP0814396A2 (en
Inventor
Stephan Weber
Udo Matter
Stefan Heinen
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Infineon Technologies AG
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Siemens AG
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/265—Current mirrors using bipolar transistors only
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/22—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only
    • G05F3/222—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the bipolar type only with compensation for device parameters, e.g. Early effect, gain, manufacturing process, or external variations, e.g. temperature, loading, supply voltage

Definitions

  • the invention relates to a circuit arrangement for generation a reference potential with a first transistor, the Emitter is connected to a reference potential and its Base and collector are interconnected with one another second transistor, the base of which is connected to the base of the first Transistor is connected to a first resistor, the between the collector of the first transistor and an output terminal switched to tap the reference potential is, with a second resistor that is between the collector of the second transistor and the output terminal is, with a third resistor connected between the emitter of the second transistor and the reference potential is, with a third transistor, the base of which is connected to the collector of the second transistor and its emitter with the reference potential is connected to a fourth transistor, its collector with the supply potential, its emitter with the output connector and its base with the collector of the third transistor is connected, between base and collector of the fourth transistor a first current source is switched.
  • Such a bandgap reference voltage source Circuit arrangement is for example from Paul R. Gray, Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, Second Edition 1984, pages 293 to 296 is used in a variety of integrated circuits Supply of other circuit blocks with a temperature independent Reference potential and / or several reference currents used. In the future, it will also become increasingly important that the integrated circuits especially for the Use in battery-operated devices as independently as possible work from the supply voltage. With everyone with constant Base-emitter voltage or constant base current driven, real transistor fluctuates due to the early effect the collector current as a function of the collector-emitter voltage, which in turn often directly with the supply voltage is linked. The early effect is for example with Paul R. Gray, Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, Second Edition 1984, pages 17 to 19 described. This problem is also critical therefore, because fast, modern transistors in terms of Early effects tend to have poor properties.
  • the object of the invention is to provide a circuit arrangement for Specify generation of a reference potential at which the Early effect is largely compensated for.
  • the advantage of the invention is that early compensation with low circuit complexity is achieved.
  • the first Current source a second current source is connected in parallel, which a compensation current to compensate for the current fluctuations generated the first power source.
  • the front second current source generated equalization current the difference of a first multiplied by a factor Early-dependent current and a second less early-dependent one Is current.
  • the first current source can be a fifth transistor are formed, whose emitter has a fifth resistor is connected to the supply potential whose Collector connected to the base of the fourth transistor and is based on a sixth resistance with the Supply potential is coupled. Furthermore, control means provided the one above the sixth resistor voltage dependent on the potential at the connection produce.
  • One embodiment of the invention includes control means a sixth transistor, the base of which is connected to the base of the fifth transistor and its emitter with interposition a seventh resistor with the supply potential is connected and to a seventh transistor whose base to the output terminal, whose emitter has an eighth resistor to the reference potential and its collector to the Collector of the sixth transistor is connected.
  • control means contain an eighth transistor, whose collector-emitter path is the collector-emitter path of the seventh transistor is connected in parallel and the basis of which is on the one hand via a ninth resistance with the Supply potential and secondly via a diode path and a tenth resistor in series with the reference potential is connected, as well as a ninth transistor, whose collector with the supply potential, whose emitter has a third current source with the reference potential and its base is coupled to the collector of the seventh transistor. Finally, there is a tenth transistor in the control means provided its emitter with the base of the fifth Transistor whose collector is connected to the reference potential and whose base is connected to the emitter of the ninth transistor is.
  • the third current source formed by an eleventh transistor, whose emitter over an eleventh resistor with the reference potential whose collector with the emitter of the ninth transistor and its base is connected to the base of the eighth transistor.
  • Partial current sources to form the first early-dependent Current and the second less early dependent current, on the one hand with the supply potential and on the other hand with the input circuit or the output circuit of a current mirror are connected, as well as one with the other two partial current sources coupled third partial current source, that of the first Current source is connected in parallel, can be provided.
  • junction of the current mirror and the output circuit second current source can be connected to the input of a current amplifier stage be connected, the output of which in turn is connected to the base of the ninth transistor is coupled.
  • the current amplifier stage are formed by a second current mirror.
  • the partial current sources can through the output branches Electricity bank, the input branch of which is given by the sixth Resistance is realized.
  • the input branch is given by a twelfth resistance.
  • the twelfth resistance the base-emitter path of a twelfth Transistors and a thirteenth resistor in series connected in parallel.
  • the base of a thirteenth Transistor, whose collector is connected to the supply potential and the collector of a fourteenth transistor, its base with the base of the seventh transistor and its emitter through a fourteenth resistance with the Reference potential is connected to the collector of the twelfth transistor coupled.
  • the base of a fifteenth Transistor whose collector is connected to the reference potential and whose emitter is connected to the base of the twelfth transistor is connected to the emitter of a thirteenth transistor.
  • the base of a sixteenth transistor, the Collector with the base of the fifteenth transistor and its Emitter across a fifteenth resistor with the reference potential is connected to the base of the eighth Transistor coupled.
  • npn transistor T1 provided, whose emitter with the reference potential M is connected and its base and collector together interconnected and via a common resistor R1 an output terminal U coupled to a reference potential are.
  • the base and collector of transistor T1 is the base of an npn transistor T2, whose Emitter via a resistor R3 with the reference potential M and its collector through a resistor R2 with the output termination U is coupled.
  • the emitter is also a npn transistor T4 connected, the collector with a supply potential V is connected.
  • the basis of the Transistor T4 is connected to the collector of an NPN transistor T3 connected, whose emitter to the reference potential M and Base is connected to the collector of transistor T2.
  • the base of transistor T4 is also a Current source circuit connected to the supply potential V.
  • the current source circuit has a pnp transistor T5 whose emitter is connected via a resistor R5 the supply potential V and its collector with the base of transistor T4 or the collector of transistor T3 connected is.
  • the base of transistor T5 is with the base a pnp transistor T6, whose emitter is connected via a Resistor R6 coupled to the supply potential V. is, the emitter via a resistor R6 with the supply potential V is coupled.
  • the collector of the transistor T6 is also with the collector of an NPN transistor T7 connected, the emitter via a resistor R4 to the Reference potential M is connected and its base with the Output terminal U is connected.
  • transistor T7 the collector-emitter path of an npn transistor T8 connected in parallel.
  • the base of the transistor T8 is connected with a resistor R8 connected to the supply potential V.
  • the base of transistor T8 is also connected to the input branch connected to a current mirror.
  • the input branch is through an NPN transistor T11 is formed, the base and collector interconnected as well as with the base of transistor T8 are and their emitters with the interposition of a resistor R10 is connected to the reference potential M.
  • the bases of transistors T7 and T8 are also one Resistor R7 coupled together.
  • the output branch of the current mirror is through an NPN transistor T12 formed, the base of which is connected to the base of the transistor T11 is connected and its emitter with interposition a resistor R9 connected to the reference potential M. is.
  • the collector of transistor T12 is off the base of a pnp transistor T10, the collector of which Reference potential M and its emitter with the bases of the transistors T5 and T6 is connected as well as to the emitter of one npn transistor T9, whose collector with the supply potential V and its base with the collector of the transistor T6 is connected. After all, there is resistance R11 between the bases of transistors T5 and T6 on the one hand and the supply potential V on the other hand switched.
  • the collector With the collector of transistor T6, the collector is one pnp transistor T13 connected whose emitter via a resistor R12 is connected to the supply potential V. its base with the base and collector of a pnp transistor T14, with the collector of a pnp transistor T15 as well coupled to the collector of an NPN transistor T18 is.
  • the emitters of the two transistors T14 and T15 are via a resistor R13 or R14 to the supply potential V connected.
  • the emitter of the transistor T18 is connected to the reference potential M via a resistor R17 connected.
  • the transistor T15 forms like pnp transistors T16 and T17, whose emitters each have a resistor R15 or R16 connected to the supply potential V.
  • the embodiment of Figure 2 changed so that the bases of transistors T15, T16 and T17 do not have the Resistor R11 but via a resistor R17 with the supply potential V are connected.
  • the bases of the transistors T15, T16, T17 are also with the emitter of a pnp transistor T18 and with the base of a pnp transistor T20 interconnected.
  • the collector of transistor T18 is on the reference potential M is connected.
  • the collector of the transistor T20 is based on the one hand with an NPN transistor T19 connected, the collector of the supply potential V is connected, and on the other hand with the collector one Transistor T21 connected, the base of which is connected to terminal U and its emitter with the interposition of a resistor R19 is coupled to the reference potential M.
  • the basis of the Transistor T18 and the emitter of transistor T19 are together connected to the collector of an npn transistor T22, its emitter via a resistor R20 with the reference potential M is connected and its base with the bases of the Transistors T11 and T12 is coupled.
  • a pnp transistor T23 is provided, the base of which is connected to the base of transistor T5 and its Emitter via a resistor R21 to the supply potential V is connected.
  • the collector is with an output connection I interconnected, at which the reference current can be tapped is.
  • the separate optimization of the operating voltage suppression both with regard to the band gap reference potential at the output U and the reference output current at connection I can separately by adjusting the emitter area of the Transistor T14 in relation to the emitter area of the transistor T13 and by adjusting resistors R17 and R18.
  • a smaller resistance value of the two resistors R17 and R18 causes weaker current feedback, so that the early voltage correction is correspondingly stronger. It a drop in the output current, for example be set if it is necessary to set an advance.
  • the output current through the Transistor T5 formed in conjunction with the resistor R5 Current source superimposes a compensation current by the output current which through transistor T17 in conjunction with the Resistor R16 formed current source also in the base of the transistor T4 is fed and the input circuit of the Transistors T15 influenced by transistors T9 to T14 becomes.
  • the output current given by the collector current of transistor T5 on The main reason for this is the early voltage dependency the collector currents of the transistors T5 up to T12. This dependence takes effect via transistor T4 directly to the output connection U.
  • the one superimposed Compensation current is now the difference of a first Early-dependent current of the current source with the transistor T16 in conjunction with resistor R15 and one less Early-dependent current of the current source with the transistor T15 formed in connection with the resistor R14 and with a Multiplied by the current ratio of the Transistors T13 and T14 and the ratio of the resistors R17 and R18 is given.
  • the dimensioning is like this chosen that a linear dependence of the compensation current is achieved and thus overall independence is reached by the supply voltage.

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  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
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  • Electromagnetism (AREA)
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Description

Die Erfindung betrifft eine Schaltungsanordnung zur Erzeugung eines Referenzpotentials mit einem ersten Transistor, dessen Emitter mit einem Bezugspotential verbunden ist und dessen Basis und Kollektor miteinander verschaltet sind, mit einem zweiten Transistor, dessen Basis mit der Basis des ersten Transistors verbunden ist, mit einem ersten Widerstand, der zwischen den Kollektor des ersten Transistors und einen Ausgangsanschluß zum Abgreifen des Referenzpotentials geschaltet ist, mit einem zweiten Widerstand, der zwischen den Kollektor des zweiten Transistors und den Ausgangsanschluß geschaltet ist, mit einem dritten Widerstand, der zwischen den Emitter des zweiten Transistors und das Bezugspotential geschaltet ist, mit einem dritten Transistor, dessen Basis mit dem Kollektor des zweiten Transistors und dessen Emitter mit dem Bezugspotential verbunden ist, mit einem vierten Transistor, dessen Kollektor mit dem Versorgungspotential, dessen Emitter mit dem Ausgangsanschluß und dessen Basis mit dem Kollektor des dritten Transistors verbunden ist, wobei zwischen Basis und Kollektor des vierten Transistors eine erste Stromquelle geschaltet ist.The invention relates to a circuit arrangement for generation a reference potential with a first transistor, the Emitter is connected to a reference potential and its Base and collector are interconnected with one another second transistor, the base of which is connected to the base of the first Transistor is connected to a first resistor, the between the collector of the first transistor and an output terminal switched to tap the reference potential is, with a second resistor that is between the collector of the second transistor and the output terminal is, with a third resistor connected between the emitter of the second transistor and the reference potential is, with a third transistor, the base of which is connected to the collector of the second transistor and its emitter with the reference potential is connected to a fourth transistor, its collector with the supply potential, its emitter with the output connector and its base with the collector of the third transistor is connected, between base and collector of the fourth transistor a first current source is switched.

Eine derartige, auch Bandgap-Referenzspannungsquelle genannte Schaltungsanordnung ist beispielsweise aus Paul R. Gray, Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, Second Edition 1984, Seiten 293 bis 296 bekannt und wird in einer Vielzahl von integrierten Schaltkreisen zur Versorgung anderer Schaltungsblöcke mit einem temperaturunabhängigen Referenzpotential und/oder mehreren Referenzströmen eingesetzt. In Zukunft wird es darüber hinaus zunehmend wichtiger, daß die integrierten Schaltkreise insbesondere für die Anwendung in batteriebetriebenen Geräten möglichst unabhängig von der Versorgungsspannung arbeiten. Bei jedem mit konstanter Basis-Emitter-Spannung oder konstantem Basisstrom angesteuerten, realen Transistor schwankt aufgrund des Early-Effekts der Kollektorstrom in Abhängigkeit von der Kollektor-Emitter-Spannung, die ihrerseits oft direkt mit der Versorgungsspannung verknüpft ist. Der Early-Effekt ist beispielsweise bei Paul R. Gray, Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, Second Edition 1984, Seiten 17 bis 19 beschrieben. Kritisch dieses Problem gerade auch deshalb, da schnelle, moderne Transistoren hinsichtlich des Early-Effekts eher schlechte Eigenschaften aufweisen.Such a bandgap reference voltage source Circuit arrangement is for example from Paul R. Gray, Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, Second Edition 1984, pages 293 to 296 is used in a variety of integrated circuits Supply of other circuit blocks with a temperature independent Reference potential and / or several reference currents used. In the future, it will also become increasingly important that the integrated circuits especially for the Use in battery-operated devices as independently as possible work from the supply voltage. With everyone with constant Base-emitter voltage or constant base current driven, real transistor fluctuates due to the early effect the collector current as a function of the collector-emitter voltage, which in turn often directly with the supply voltage is linked. The early effect is for example with Paul R. Gray, Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, Second Edition 1984, pages 17 to 19 described. This problem is also critical therefore, because fast, modern transistors in terms of Early effects tend to have poor properties.

Aufgabe der Erfindung ist es, eine Schaltungsanordnung zur Erzeugung eines Referenzpotentials anzugeben, bei der der Early-Effekt weitestgehend kompensiert ist.The object of the invention is to provide a circuit arrangement for Specify generation of a reference potential at which the Early effect is largely compensated for.

Die Aufgabe wird durch eine Schaltungsanordnung gemäß Patent anspruch 1 gelöst. Ausgestaltungen und Weiterbildungen des Erfindungsgedankens sind Gegenstand von Unteransprüchen.The object is achieved by a circuit arrangement according to the patent Claim 1 solved. Refinements and developments of the The concept of the invention is the subject of dependent claims.

Vorteil der Erfindung ist es, daß eine Early-Kompensation mit geringem schaltungstechnischen Aufwand erzielt wird.The advantage of the invention is that early compensation with low circuit complexity is achieved.

Dies wird insbesondere dadurch erreicht, daß der ersten Stromquelle eine zweite Stromquelle parallel geschaltet ist, die einen Kompensationsstrom zur Kompensation der Stromschwankungen der ersten Stromquelle erzeugt.This is achieved in particular in that the first Current source a second current source is connected in parallel, which a compensation current to compensate for the current fluctuations generated the first power source.

Bei einer Ausgestaltung kann vorgesehen werden, daß der vorder zweiten Stromquelle erzeugte Kompensationsstrom gleich der mit einem Faktor multiplizierten Differenz eines ersten Early-abhängigen Stroms und eines zweiten weniger Early-abhängigen Stroms ist.In one embodiment it can be provided that the front second current source generated equalization current the difference of a first multiplied by a factor Early-dependent current and a second less early-dependent one Is current.

Dabei kann die erste Stromquelle durch einen fünften Transistor gebildet werden, dessen Emitter über einen fünften Widerstand an dem Versorgungspotential angeschlossen ist, dessen Kollektor mit der Basis des vierten Transistors verbunden ist und dessen Basis über einen sechsten Widerstand mit dem Versorgungspotential gekoppelt ist. Des weiteren sind Ansteuermittel vorgesehen, die über dem sechsten Widerstand eine von dem am Anschluß anliegenden Potential abhängige Spannung erzeugen.The first current source can be a fifth transistor are formed, whose emitter has a fifth resistor is connected to the supply potential whose Collector connected to the base of the fourth transistor and is based on a sixth resistance with the Supply potential is coupled. Furthermore, control means provided the one above the sixth resistor voltage dependent on the potential at the connection produce.

Eine Ausgestaltung der Erfindung enthält Ansteuermittel mit einem sechsten Transistor, dessen Basis mit der Basis des fünften Transistors und dessen Emitter unter Zwischenschaltung eines siebten Widerstands mit dem Versorgungspotential verbunden ist und mit einem siebten Transistor, dessen Basis an den Ausgangsanschluß, dessen Emitter über einen achten Widerstand an das Bezugspotential und dessen Kollektor an den Kollektor des sechsten Transistors angeschlossen ist. Weiterhin enthalten die Ansteuermittel einen achten Transistor, dessen Kollektor-Emitter-Strecke der Kollektor-Emitter-Strecke des siebten Transistors parallel geschaltet ist und dessen Basis zum einen über einen neunten Widerstand mit dem Versorgungspotential und zum anderen über eine Diodenstrecke und einen zehnten Widerstand in Reihe mit dem Bezugspotential verbunden ist, sowie einen neunten Transistor, dessen Kollektor mit dem Versorgungspotential, dessen Emitter über eine dritte Stromquelle mit dem Bezugspotential und dessen Basis mit dem Kollektor des siebten Transistors gekoppelt ist. Schließlich ist bei den Ansteuermitteln ein zehnter Transistor vorgesehen, dessen Emitter mit der Basis des fünften Transistors, dessen Kollektor mit dem Bezugspotential und dessen Basis mit dem Emitter des neunten Transistors verschaltet ist.One embodiment of the invention includes control means a sixth transistor, the base of which is connected to the base of the fifth transistor and its emitter with interposition a seventh resistor with the supply potential is connected and to a seventh transistor whose base to the output terminal, whose emitter has an eighth resistor to the reference potential and its collector to the Collector of the sixth transistor is connected. Farther the control means contain an eighth transistor, whose collector-emitter path is the collector-emitter path of the seventh transistor is connected in parallel and the basis of which is on the one hand via a ninth resistance with the Supply potential and secondly via a diode path and a tenth resistor in series with the reference potential is connected, as well as a ninth transistor, whose collector with the supply potential, whose emitter has a third current source with the reference potential and its base is coupled to the collector of the seventh transistor. Finally, there is a tenth transistor in the control means provided its emitter with the base of the fifth Transistor whose collector is connected to the reference potential and whose base is connected to the emitter of the ninth transistor is.

Bei einer weiteren Ausgestaltung wird die dritte Stromquelle durch einen elften Transistor gebildet, dessen Emitter über einen elften Widerstand mit dem Bezugspotential, dessen Kollektor mit dem Emitter des neunten Transistors und dessen Basis mit der Basis des achten Transistors verbunden ist.In a further embodiment, the third current source formed by an eleventh transistor, whose emitter over an eleventh resistor with the reference potential whose collector with the emitter of the ninth transistor and its base is connected to the base of the eighth transistor.

Bei der zweiten Stromquelle können zwei miteinander gekoppelte Teilstromquellen zur Bildung des ersten Early-abhängigen Stromes und des zweiten weniger Early-abhängigen Stromes, die einerseits mit dem Versorgungspotential und andererseits mit dem Eingangskreis bzw. dem Ausgangskreis eines Stromspiegels verbunden sind, sowie eine mit den anderen beiden Teilstromquellen gekoppelte dritte Teilstromquelle, die der ersten Stromquelle parallel geschaltet ist, vorgesehen werden.With the second power source, two can be coupled together Partial current sources to form the first early-dependent Current and the second less early dependent current, on the one hand with the supply potential and on the other hand with the input circuit or the output circuit of a current mirror are connected, as well as one with the other two partial current sources coupled third partial current source, that of the first Current source is connected in parallel, can be provided.

Der Knotenpunkt des ausganskreises des Stromspiegels und der zweiten Stromquelle kann dabei mit dem Eingang einer Stromverstärkerstufe verbunden sein, deren Ausgang wiederum mit der Basis des neunten Transistor gekoppelt ist.The junction of the current mirror and the output circuit second current source can be connected to the input of a current amplifier stage be connected, the output of which in turn is connected to the base of the ninth transistor is coupled.

Bei einer Ausgestaltung der Erfindung kann die Stromverstärkerstufe durch einen zweiten Stromspiegel gebildet werden.In one embodiment of the invention, the current amplifier stage are formed by a second current mirror.

Die Teilstromquellen können durch die Ausganszweige einer Strombank gegeben sein, deren Eingangszweig durch den sechSten Widerstand realisiert ist.The partial current sources can through the output branches Electricity bank, the input branch of which is given by the sixth Resistance is realized.

Schließlich können die Teilstromquellen durch die Ausgangszweige einer Strombank gebildet werden, deren Eingangszweig durch einen zwölften Widerstand gegeben ist. Dabei ist dem zwölften Widerstand die Basis-Emitter-Strecke eines zwölften Transistors sowie ein in Reihe dazu liegender dreizehnter Widerstand parallel geschaltet. Die Basis eines dreizehnten Transistors, dessen Kollektor an das Versorgungspotential angeschlossen ist, und der Kollektor eines vierzehnten Transistors, dessen Basis mit der Basis des siebten Transistors und dessen Emitter über einen vierzehnten Widerstand mit dem Bezugspotential verbunden ist, sind dabei mit dem Kollektor des zwölften Transistors gekoppelt. Die Basis eines fünfzehnten Transistors, dessen Kollektor mit dem Bezugspotential und dessen Emitter mit der Basis des zwölften Transistors verbunden ist, ist an den Emitter eines dreizehnten Transistors angeschlossen. Die Basis eines sechzehnten Transistors, dessen Kollektor mit der Basis des fünfzehnten Transistors und desse Emitter über einen fünfzehnten Widerstand mit dem Bezugspotential verbunden ist, ist dabei mit der Basis des achten Transistors gekoppelt.Finally, the partial current sources through the output branches a power bank are formed, the input branch is given by a twelfth resistance. Here is the twelfth resistance the base-emitter path of a twelfth Transistors and a thirteenth resistor in series connected in parallel. The base of a thirteenth Transistor, whose collector is connected to the supply potential and the collector of a fourteenth transistor, its base with the base of the seventh transistor and its emitter through a fourteenth resistance with the Reference potential is connected to the collector of the twelfth transistor coupled. The base of a fifteenth Transistor whose collector is connected to the reference potential and whose emitter is connected to the base of the twelfth transistor is connected to the emitter of a thirteenth transistor. The base of a sixteenth transistor, the Collector with the base of the fifteenth transistor and its Emitter across a fifteenth resistor with the reference potential is connected to the base of the eighth Transistor coupled.

Die Erfindung wird nachfolgend anhand der in den beiden Figuren der Zeichnung dargestellten Ausführungsbeispiele näher erläutert, wobei gleiche Elemente mit gleichen Bezugszeichen versehen sind. Es zeigt:

Figur 1
eine erste Ausführungsform und
Figur 2
eine zweite Ausführungsform einer eifindungsgemäßen Schaltungsanordnung.
The invention is explained in more detail below with reference to the exemplary embodiments shown in the two figures of the drawing, the same elements being provided with the same reference symbols. It shows:
Figure 1
a first embodiment and
Figure 2
a second embodiment of a circuit arrangement according to the invention.

Bei dem in Figur 1 gezeigten Ausführungsbeispiel ist ein npn-Transistor T1 vorgesehen, dessen Emitter mit dem Bezugspotential M verbunden ist und dessen Basis und Kollektor miteinander verschaltet und über einen gemeinsamen Widerstand R1 mit einem ein Referenzponential führenden Ausgangsanschluß U gekoppelt sind. An Basis und Kollektor des Transistors T1 ist die Basis eines npn-Transistors T2 angeschlossen, dessen Emitter über einen Widerstand R3 mit dem Bezugspotential M und dessen Kollektor über einen Widerstand R2 mit dem Ausgangsazschluß U gekoppelt ist.In the embodiment shown in Figure 1 is an npn transistor T1 provided, whose emitter with the reference potential M is connected and its base and collector together interconnected and via a common resistor R1 an output terminal U coupled to a reference potential are. At the base and collector of transistor T1 is the base of an npn transistor T2, whose Emitter via a resistor R3 with the reference potential M and its collector through a resistor R2 with the output termination U is coupled.

An dem Ausgangsanschluß U ist darüber hinaus der Emitter eines npn-Transistors T4 angeschlossen, dessen Kollektor mit einem Versorgungspotential V verbunden ist. Die Basis des Transistors T4 ist mit dem Kollektor eines npn-Transistors T3 verbunden, dessen Emitter an das Bezugspotential M und dessen Basis an den Kollektor des Transistors T2 angeschlossen ist.At the output terminal U, the emitter is also a npn transistor T4 connected, the collector with a supply potential V is connected. The basis of the Transistor T4 is connected to the collector of an NPN transistor T3 connected, whose emitter to the reference potential M and Base is connected to the collector of transistor T2.

Die Basis des Transistors T4 ist darüber hinaus über eine Stromquellenschaltung an das Versorgungspotential V angeschlossen. Die Stromquellenschaltung weist einen pnp-Transistor T5 auf, dessen Emitter über einen Widerstand R5 mit dem Versorgungspotential V und dessen Kollektor mit der Basis des Transistors T4 bzw. dem Kollektor des Transistors T3 verbunden ist. Die Basis des Transistors T5 ist mit der Basis eines pnp-Transistors T6 verschaltet, dessen Emitter über einen Widerstand R6 mit dem Versorgungspotential V gekoppelt ist, dessen Emitter über einen Widerstand R6 mit dem Versorgungspotential V gekoppelt ist. Der Kollektor des Transistors T6 ist darüber hinaus mit dem Kollektor eines npn-Transistors T7 verbunden, dessen Emitter über einen Widerstand R4 an das Bezugspotential M angeschlossen ist und dessen Basis mit dem Ausgangsanschluß U verbunden ist. Weiterhin ist der Kollen tor-Emitter-Strecke des Transistors T7 die Kollektor-Emitter-Strecke eines npn-Transistors T8 parallel geschaltet. Die Basis des Transistors T8 ist unter Zwischenschaltung eines Widerstandes R8 an das Versorgungspotential V angeschlossen. Die Basis des Transistors T8 ist zudem mit dem Eingangszweig eines Stromspiegels verbunden. Der Eingangszweig wird durch einen npn-Transistor T11 gebildet, dessen Basis und Kollektor miteinander sowie mit der Basis des Transistors T8 verschaltet sind und dessen Emitter unter Zwischenschaltung eines Widerstandes R10 an das Bezugspotential M angeschlossen ist. Die Basen der Transistoren T7 und T8 sind zudem über einen Widerstand R7 miteinander gekoppelt.The base of transistor T4 is also a Current source circuit connected to the supply potential V. The current source circuit has a pnp transistor T5 whose emitter is connected via a resistor R5 the supply potential V and its collector with the base of transistor T4 or the collector of transistor T3 connected is. The base of transistor T5 is with the base a pnp transistor T6, whose emitter is connected via a Resistor R6 coupled to the supply potential V. is, the emitter via a resistor R6 with the supply potential V is coupled. The collector of the transistor T6 is also with the collector of an NPN transistor T7 connected, the emitter via a resistor R4 to the Reference potential M is connected and its base with the Output terminal U is connected. Furthermore is the kollen Gate-emitter path of transistor T7 the collector-emitter path of an npn transistor T8 connected in parallel. The base of the transistor T8 is connected with a resistor R8 connected to the supply potential V. The base of transistor T8 is also connected to the input branch connected to a current mirror. The input branch is through an NPN transistor T11 is formed, the base and collector interconnected as well as with the base of transistor T8 are and their emitters with the interposition of a resistor R10 is connected to the reference potential M. The bases of transistors T7 and T8 are also one Resistor R7 coupled together.

Der Ausgangszweig des Stromspiegels wird durch einen npn-Transistor T12 gebildet, dessen Basis mit der Basis des Transistors T11 verbunden ist und dessen Emitter unter Zwischenschaltung eines Widerstandes R9 an das Bezugspotential M angeschlossen ist. Der Kollektor des Transistors T12 ist aus die Basis eines pnp-Transistors T10, dessen Kollektor mit dem Bezugspotential M und dessen Emitter mit den Basen der Transistoren T5 und T6 verbunden ist sowie auf den Emitter eines npn-Transistors T9, dessen Kollektor mit dem Versorgungspotential V und dessen Basis mit dem Kollektor des Transistors T6 verschaltet ist, geführt. Schließlich ist ein Widerstand R11 zwischen die Basen der Transistoren T5 und T6 einerseits und das Versorgungspotential V andererseits geschaltet.The output branch of the current mirror is through an NPN transistor T12 formed, the base of which is connected to the base of the transistor T11 is connected and its emitter with interposition a resistor R9 connected to the reference potential M. is. The collector of transistor T12 is off the base of a pnp transistor T10, the collector of which Reference potential M and its emitter with the bases of the transistors T5 and T6 is connected as well as to the emitter of one npn transistor T9, whose collector with the supply potential V and its base with the collector of the transistor T6 is connected. After all, there is resistance R11 between the bases of transistors T5 and T6 on the one hand and the supply potential V on the other hand switched.

Mit dem Kollektor des Transistors T6 ist der Kollektor eines pnp-Transistors T13 verbunden, dessen Emitter über einen Widerstand R12 mit dem Versorgungspotential V verschaltet ist dessen Basis mit Basis und Kollektor eines pnp-Transistors T14, mit dem Kollektor eines pnp-Transistors T15 sowie mit dem Kollektor eines npn-Transistors T18 gekoppelt ist. Die Emitter der beiden Transistoren T14 und T15 sind über jeweils einen Widerstand R13 bzw. R14 an das Versorgungspotential V angeschlossen. Der Emitter des Transistors T18 ist über einen Widerstand R17 mit dem Bezugspotential M verbunden. Der Transistor T15 bildet ebenso wie pnp-Transistoren T16 und T17, deren Emitter über jeweils einen Widerstand R15 bzw. R16 mit dem Versorgungspotential V verbunden sind, Ausgangszweige eines Stromspiegels, dessen Eingangszweig durch den Widerstand R11 gebildet wird. Dazu sind die Basen der Transistoren T15, T16 und T17 mit den Basen der Transistoren T5 und T6 gekoppelt. Der Kollektor des Transistors T16 ist mit Basis und Kollektor eines npn-Transistors T19 sowie mit der Basis des Transistors T18 verschaltet. Der Emitter des Transistors T19 ist über einen Widerstand R18 mit dem Bezugspotential M gekoppelt. Der Kollektor des Transistors T17 schließlich ist mit der Basis des Transistors T4 verbunden.With the collector of transistor T6, the collector is one pnp transistor T13 connected whose emitter via a resistor R12 is connected to the supply potential V. its base with the base and collector of a pnp transistor T14, with the collector of a pnp transistor T15 as well coupled to the collector of an NPN transistor T18 is. The emitters of the two transistors T14 and T15 are via a resistor R13 or R14 to the supply potential V connected. The emitter of the transistor T18 is connected to the reference potential M via a resistor R17 connected. The transistor T15 forms like pnp transistors T16 and T17, whose emitters each have a resistor R15 or R16 connected to the supply potential V. are, output branches of a current mirror, its input branch is formed by the resistor R11. For that are the Bases of transistors T15, T16 and T17 with the bases of the Transistors T5 and T6 coupled. The collector of the transistor T16 is with the base and collector of an NPN transistor T19 and connected to the base of transistor T18. The The emitter of transistor T19 is connected via a resistor R18 the reference potential M coupled. The collector of the transistor Finally, T17 is connected to the base of transistor T4 connected.

Gegenüber dem in Figur 1 gezeigten Ausführungsbeispiel ist die Ausführungsform nach Figur 2 dahingehend geändert, daß die Basen der Transistoren T15, T16 und T17 nicht über den Widerstand R11 sondern über einen Widerstand R17 mit dem Versorgungspotential V verbunden sind. Die Basen der Transistoren T15, T16, T17 sind zudem mit dem Emitter eines pnp-Transistors T18 sowie mit der Basis eines pnp-Transistors T20 verschaltet. Der Kollektor des Transistors T18 ist dabei an das Bezugspotential M angeschlossen. Der Kollektor des Transistors T20 ist zum einen mit der Basis eines npn-Transistors T19 verbunden, dessen Kollektor an das Versorgungspotential V angeschlossen ist, und zum anderen mit dem Kollektor eines Transistors T21 verschaltet, dessen Basis mit dem Anschluß U und dessen Emitter unter Zwischenschaltung eines Widerstandes R19 mit dem Bezugspotential M gekoppelt ist. Die Basis des Transistors T18 und der Emitter des Transistors T19 sind zusammen an dem Kollektor eines npn-Transistors T22 angeschlossen, dessen Emitter über einen Widerstand R20 mit dem Bezugspotential M verbunden ist und dessen Basis mit den Basen der Transistoren T11 und T12 gekoppelt ist.Compared to the embodiment shown in Figure 1 the embodiment of Figure 2 changed so that the bases of transistors T15, T16 and T17 do not have the Resistor R11 but via a resistor R17 with the supply potential V are connected. The bases of the transistors T15, T16, T17 are also with the emitter of a pnp transistor T18 and with the base of a pnp transistor T20 interconnected. The collector of transistor T18 is on the reference potential M is connected. The collector of the transistor T20 is based on the one hand with an NPN transistor T19 connected, the collector of the supply potential V is connected, and on the other hand with the collector one Transistor T21 connected, the base of which is connected to terminal U and its emitter with the interposition of a resistor R19 is coupled to the reference potential M. The basis of the Transistor T18 and the emitter of transistor T19 are together connected to the collector of an npn transistor T22, its emitter via a resistor R20 with the reference potential M is connected and its base with the bases of the Transistors T11 and T12 is coupled.

Um schließlich auch einen Referenzausgangsstrom erzeugen zu können ist ein pnp-Transistor T23 vorgesehen, dessen Basis mit der Basis des Transistors T5 verschaltet ist und dessen Emitter über einen Widerstand R21 an das Versorgungspotential V angeschlossen ist. Der Kollektor ist mit einem Ausgangsanschluß I verschaltet, an dem der Referenzstrom abgreifbar ist.To finally also generate a reference output current a pnp transistor T23 is provided, the base of which is connected to the base of transistor T5 and its Emitter via a resistor R21 to the supply potential V is connected. The collector is with an output connection I interconnected, at which the reference current can be tapped is.

Die getrennte Optimierung der Betriebsspannungsunterdrückung sowohl im Hinblick auf das Bandgap-Referenzpotential am Ausgang U sowie auf den Referenzausgangsstrom am Anschluß I kann getrennt erfolgen durch Einstellen der Emitterfläche des Transistors T14 im Verhältnis zur Emitterfläche des Transistors T13 sowie durch Anpassung der Widerstände R17 und R18. Ein kleinerer Widerstandswert der beiden Widerstände R17 und R18 bewirkt eine schwächere Stromgegenkopplung, so daß die Early-Spannungskorrektur entsprechend stärker ist. Es kann auch ein Absinken beispielsweise des Ausgangsstromes eingestellt werden, wenn es gilt, einen Vorhalt zu realisieren. Zudem können eigene, ggf. abschaltbare Stromausgangsstufen vorgesehen werden, die durch weitere Stromausgänge der aus den Transistoren T13 und T14 in Verbindung mit den Widerständen R12 und R13 gebildeten Strombank zur Early-Kompensation der Ausgangsstufen herangezogen werden.The separate optimization of the operating voltage suppression both with regard to the band gap reference potential at the output U and the reference output current at connection I can separately by adjusting the emitter area of the Transistor T14 in relation to the emitter area of the transistor T13 and by adjusting resistors R17 and R18. A smaller resistance value of the two resistors R17 and R18 causes weaker current feedback, so that the early voltage correction is correspondingly stronger. It a drop in the output current, for example be set if it is necessary to set an advance. In addition, you can switch off your own current output stages be provided by the further current outputs of the from the transistors T13 and T14 in connection with the resistors R12 and R13 formed current bank for early compensation of the output stages are used.

Wie zu ersehen ist, wird dem Ausgangsstrom der durch den Transistor T5 in Verbindung mit dem Widerstand R5 gebildeten Stromquelle ein Kompensationsstrom überlagert, indem der Ausgangsstrom der durch den Transistor T17 in Verbindung mit dem Widerstand R16 gebildeten Stromquelle ebenfalls in die Basis des Transistors T4 eingespeist wird und der Eingangskreis des Transistors T15 über die Transistoren T9 bis T14 beinflußt wird. Mit steigender Versorgungsspannung steigt nämlich auch der durch den Kollektorstrom des Transistors T5 gegebene Ausgangsstrom an. Ursache hierfür ist in erster Linie die Early-Spannungsabhängigkeit der Kollektorströme der Transistoren T5 bis T12. Über den Transistor T4 wirkt sich diese Abhängigkeit direkt auf den Ausgangsanschluß U aus. Der diesen überlagerte Kompensationsstrom wird nun aus der Differenz eines ersten Early-abhängigen Stroms der Stromquelle mit dem Transistor T16 in Verbindung mit dem Widerstand R15 und eines weniger Early-abhängigen Stroms der Stromquelle mit dem Transistor T15 in Verbindung mit dem Widerstand R14 gebildet und mit einem Faktor multipliziert, der durch das Stromverhältnis der Transistoren T13 und T14 sowie das Verhältnis der Widerstände R17 und R18 gegeben ist. Dabei wird die Dimensionierung so gewählt, daß eine lineare Abhängigkeit des Kompensationsstroms erzielt wird und damit insgesamt eine Unabhängigkeit von der Versorgungsspannung erreicht wird.As can be seen, the output current through the Transistor T5 formed in conjunction with the resistor R5 Current source superimposes a compensation current by the output current which through transistor T17 in conjunction with the Resistor R16 formed current source also in the base of the transistor T4 is fed and the input circuit of the Transistors T15 influenced by transistors T9 to T14 becomes. With increasing supply voltage, it also increases the output current given by the collector current of transistor T5 on. The main reason for this is the early voltage dependency the collector currents of the transistors T5 up to T12. This dependence takes effect via transistor T4 directly to the output connection U. The one superimposed Compensation current is now the difference of a first Early-dependent current of the current source with the transistor T16 in conjunction with resistor R15 and one less Early-dependent current of the current source with the transistor T15 formed in connection with the resistor R14 and with a Multiplied by the current ratio of the Transistors T13 and T14 and the ratio of the resistors R17 and R18 is given. The dimensioning is like this chosen that a linear dependence of the compensation current is achieved and thus overall independence is reached by the supply voltage.

Claims (10)

  1. Circuit arrangement for generating a reference potential
    having a first transistor (T1), whose emitter is connected to a reference-earth potential (M) and whose base and collector are connected up to one another,
    having a second transistor (T2), whose base is connected to the base of the first transistor (T1),
    having a first resistor (R1), which is connected between the collector of the first transistor (T1), and an output terminal (U) for tapping off the reference potential,
    having a second resistor (R2), which is connected between the collector of the second transistor (T2) and the output terminal (U)
    having a third resistor (R3), which is connected between the emitter of the second transistor (T2) and the reference-earth potential (M)
    having a third transistor (T3), whose base is connected to the collector of the second transistor (T2) and whose emitter is connected to the reference-earth potential (M),
    having a fourth transistor (T4), whose collector is connected to the supply potential (V), whose emitter is connected to the output terminal (U) and whose base is connected to the collector of the third transistor (T3), a first current source (R5, T5) being connected between the base and the collector of the fourth transistor (T4),
    characterized by a second current source (T17, R16), which is connected in parallel with the first current source (R5, T5) and generates a compensation current for compensating for the current fluctuations of the first current source (R5, T5).
  2. Circuit arrangement according to Claim 1,
    characterized in that the compensation current generated by the second current source (T17, R16) is equal to the difference between a first Early-dependent current and a second, less Early-dependent current, the said difference being multiplied by a factor.
  3. Circuit arrangement according to Claim 1 or 2,
    characterized in that the first current source is formed by a fifth transistor (T5), whose emitter is connected to the supply potential (V) via a fifth resistor (R5), whose collector is connected to the base of the fourth transistor (T4), and whose base is coupled to the supply potential (V) via a sixth resistor (R11), and in that drive means are provided which generate across the sixth resistor (R11) a voltage that is dependent on the potential present at the terminal (U).
  4. Circuit arrangement according to Claim 3,
    characterized by drive means having a sixth transistor (T6), whose base is connected to the base of the fifth transistor (T5) and whose emitter is connected to the supply potential (V) with the interposition of a seventh resistor (R6), having a seventh transistor (T7), whose base is connected to the output terminal (U), whose emitter is connected to the reference-earth potential (M) via an eighth resistor (R4) and whose collector is connected to the collector of the sixth transistor (T6),
    having an eighth transistor (T8), whose collector-emitter path is connected in parallel with the collector-emitter path of the seventh transistor (T7) and whose base is connected on the one hand to the supply potential (V) via a ninth resistor (R8) and on the other hand to the reference-earth potential (M) via a diode path (T11) and a tenth resistor (R10) in series,
    having a ninth transistor (T9), whose collector is coupled to the supply potential (V), whose emitter is coupled to the reference-earth potential (M) via a third current source (T12, R9) and whose base is coupled to the collector of the seventh transistor (T7), and
    having a tenth transistor (T10), whose emitter is connected up to the base of the fifth transistor (T5), whose collector is connected up to the reference-earth potential (M) and whose base is connected up to the emitter of the ninth transistor (T9).
  5. Circuit arrangement according to Claim 4,
    characterized in that the third current source is formed by an eleventh transistor (T12), whose emitter is connected to the reference-earth potential (M) via an eleventh resistor (R9), whose collector is connected to the emitter of the ninth transistor (T9) and whose base is connected to the base of the eighth transistor (T8).
  6. Circuit arrangement according to one of Claims 1 to 4,
    characterized in that in the second current source, provision is made of two partial current sources (R14, R15, T15, T16), which are coupled to one another, for forming the first Early-dependent current and the second, less Early-dependent current, which are connected on the one hand to the supply potential (V) and on the other hand to the input circuit and output circuit, respectively, of a current mirror (T18a, T19a, R17a, R18a), and provision is also made of a third partial current source (T17, R16), which is coupled to the other two partial current sources on the input side and is connected in parallel with the first current source (T5, R5).
  7. Circuit arrangement according to Claim 6,
    characterized in that the node of the output circuit of the current mirror (T18a, T19a, R17a, R18a), and of the second current source (R14, R15, T15, T16) are connected to the input of a current amplifier stage (T13, T14, R12, R13), whose output is coupled to the base of the ninth transistor (T9).
  8. Circuit arrangement according to Claim 6 or 7,
    characterized in that the current amplifier stage is formed by a second current mirror (T13, T14, R12, R13).
  9. Circuit arrangement according to one of Claims 6 to 8,
    characterized in that the partial current sources are formed by the output paths of a current bank whose input path is provided by the sixth resistor (R11).
  10. Circuit arrangement according to one of Claims 6 to 8,
    characterized in that the partial current sources are formed by the output paths of a current bank whose input path is provided by a twelfth resistor (R17), in that the base-emitter junction of a twelfth transistor (T20) in series with a thirteenth resistor (R18) is connected in parallel with the twelfth resistor (R17),
    in that the base of a thirteenth transistor (T19), whose collector is connected to the supply potential (V), and the collector of a fourteenth transistor (T21), whose base is connected to the base of the seventh transistor (T7) and whose emitter is connected to the reference-earth potential (M) via a fourteenth resistor (R19), is coupled to the collector of the twelfth transistor (T20),
    in that the base of a fifteenth transistor (T18), whose collector is connected to the reference-earth potential (M) and whose emitter is connected to the base of the twelfth transistor (T20), is connected to the emitter of the thirteenth transistor (T19), and in that the base of a sixteenth transistor (T22), whose collector is connected to the base of the fifteenth transistor (T18) and whose emitter is connected to the reference-earth potential (M) via a fifteenth resistor (R20), is coupled to the base of the eighth transistor (T8).
EP97109351A 1996-06-20 1997-06-09 Circuit for generating a voltage reference Expired - Lifetime EP0814396B1 (en)

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DE19624676A DE19624676C1 (en) 1996-06-20 1996-06-20 Circuit arrangement for generation of reference voltage
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EP0814396A3 (en) 1998-12-09
DE59702395D1 (en) 2000-11-02
EP0814396A2 (en) 1997-12-29
US5969566A (en) 1999-10-19

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