EP0707741A4 - Montage en surface et technologie de puce a protuberances - Google Patents

Montage en surface et technologie de puce a protuberances

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Publication number
EP0707741A4
EP0707741A4 EP95918863A EP95918863A EP0707741A4 EP 0707741 A4 EP0707741 A4 EP 0707741A4 EP 95918863 A EP95918863 A EP 95918863A EP 95918863 A EP95918863 A EP 95918863A EP 0707741 A4 EP0707741 A4 EP 0707741A4
Authority
EP
European Patent Office
Prior art keywords
substrate
layer
conductive
forming
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP95918863A
Other languages
German (de)
English (en)
Other versions
EP0707741A1 (fr
Inventor
Mike F Chang
King Owyang
Fwu-Iuan Hshieh
Yueh-Se Ho
Jowei Dun
Hans-Juergen Fuesser
Reinhard Zachai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vishay Siliconix Inc
Original Assignee
Siliconix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconix Inc filed Critical Siliconix Inc
Publication of EP0707741A1 publication Critical patent/EP0707741A1/fr
Publication of EP0707741A4 publication Critical patent/EP0707741A4/fr
Withdrawn legal-status Critical Current

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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
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    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
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Definitions

  • This invention relates to integrated circuit electrical isolation, and more specifically to integrated circuit total isolation using both surface mount and flip chip fabrication technologies with a diamond film passivation layer.
  • Dielectric isolation for integrated circuits is well known.
  • a trench or groove is formed in the semiconductor chip substrate and is lined or filled with an insulative material, to electrically isolate various portions of the chip. For instance, a particular portion of the chip such as power (high voltage) transistors is surrounded by an insulated trench, thereby electrically isolating the power transistors from logic type (low voltage) transistors.
  • This prior art trench isolation has the significant disadvantage that the bottom of each trench is an area of substantial mechanical stress in the silicon substrate, thereby being detrimental to chip functionality. Such trenches thus reduce yield (increase cost) .
  • This deficiency is sometimes overcome by using "round hole” techniques to form the bottom of each trench (providing a U-shaped rather than a rectangular cross-section) which however, also tends to increase cost.
  • Another method for achieving isolation uses two wafers, with an oxide layer formed on a surface of one wafer which is then bonded to the second wafer; the oxide layer provides the isolation. After bonding the two wafers, the backside of one of the wafers is polished away down to the oxide layer to isolate a portion of the remaining substrate.
  • this is very expensive because there can be no defects in the bond between the two wafers. Defects are often induced by particles in the bond between the two wafers, causing low production yield and hence high cost. Also, oxidation induced stacking faults (OISF) due to processing temperature cycles are undesirably more pronounced in such a bond than in bulk silicon.
  • OFISF oxidation induced stacking faults
  • trench dielectric isolation is part of a chip fabrication process which allows the packaging for each chip to be formed on the wafer, thereby eliminating the prior art separate step of packaging a semiconductor die after the wafer is scribed into multiple die. Therefore the disclosed process is the equivalent of assembly or packaging the integrated circuit die at "waferscale", since each die is already packaged before the wafer is scribed.
  • transistors or other semiconductor devices are conventionally fabricated on a semiconductor substrate. Some of these devices may be power transistors (operating at high voltage) and others may be lower voltage logic-type transistors formed in another portion of the substrate.
  • the devices are field effect transistors having gate electrodes formed in an insulated layer overlying the principal surface of the semiconductor substrate.
  • the transistors are IGBT's (insulated gate bipolar transistors) , or bipolar transistors, or other semiconductor devices.
  • the fabrication process technology may be a CMOS, NMOS, PMOS, DMOS, BiCMOS, or bipolar technology, for example.
  • an interconnect pattern is conventionally formed overlying and interconnecting the gate electrodes (or other transistor elements) , and for contacting the semiconductor regions (e.g. source and drain) formed in the substrate.
  • a plurality of insulated trenches are then formed penetrating the principal surface of the substrate into the depth thereof, and surrounding (in a top view) various portions of the substrate.
  • the trenches are conventionally insulated by filling or lining them with an insulative material followed by a planarization. This step may be prior to metallization.
  • a portion of the backside of the substrate is removed by conventional machining or chemical processes, exposing the bottom portion of each of the trenches, and thereby achieving full (total) electrical isolation of the various substrate portions surrounded by each trench.
  • the frontside surface Prior to the step of removing the backside portion of the substrate, the frontside surface is bonded to a heat sink cap or plate (made for instance of silicon) using epoxy or similar bonding materials.
  • This heat sink cap also provides the needed mechanical support for the substrate, which is otherwise quite thin following the substrate removal step.
  • vias penetrate from the backside surface of the substrate to its principal (frontside) surface, allowing electrically conductive material formed in the vias to contact an interconnect structure already formed on the substrate frontside surface. Extensions of the vias on the substrate backside define posts for surface mount electrical contacts. Other similar posts formed on the backside surface of the substrate make contact to the bulk substrate.
  • the heat sink cap attached to the frontside substrate surface has a mechanical and heat dissipation function, with no electrical connections provided thereby.
  • the heat sink cap also carries on it an electrical interconnect, making electrical contact to the conventional interconnect on the substrate frontside surface.
  • This heat sink cap may be attached to a conventional flip chip backplate.
  • the electrical contacts formed on the substrate backside surface are the conventional drain or collector contacts for e.g. power integrated circuits.
  • the individual integrated circuits are packaged while still being part of a single wafer, by the application of the heat sink cap which is attached (by epoxy or other adhesive) to the wafer frontside surface.
  • This cap replaces the conventional plastic or ceramic packaging which in the prior art is applied only after the wafer is scribed into individual die.
  • the full trench isolation between the die allows the die to be scribed adjacent to the isolation trenches, together with attached front end mechanical support plate (cap) , so no further packaging is needed.
  • the thickness of the substrate after the substrate removal step is less than about 50 micrometers. This very thin substrate is free of heat induced mechanical stresses, due to its mechanical flexibility.
  • integrated circuit chips in accordance with the invention are inexpensively fabricated using essentially conventional steps which provide a high yield, thus reducing cost.
  • the dielectric isolation trenches may conventionally be lined, for instance with silicon dioxide (formed from the silicon trench walls) , or may be completely filled with silicon dioxide, or may be lined with silicon dioxide and then filled with another material such as CVD (chemical vapor deposition) nitride, polysilicon or oxide. In another embodiment, the trenches are filled with conventional spun on glass. Other insulating materials may be used for the trench dielectric.
  • the heat sink cap is typically silicon, silicon carbide, silicon nitride, aluminum nitride, molybdenum, or other material which provides sufficient heat transfer and is conveniently fabricated.
  • the removal of the backside of the substrate advantageously eliminates mechanical stresses normally present at the bottom of a trench formed in silicon.
  • trench isolation is overcome, resulting in a thin, flexible substrate.
  • the prior art requirement for a semiconductor buried layer in the substrate is eliminated, due to the very thin substrate and formation of a layer of conductive material on selective areas of the substrate backside surface.
  • a backside contact which is a metal plate or metallization layer rather than a buried semiconductor layer.
  • the metallized drain (or collector) contact on the backside surface which is in relatively close proximity to the active transistors (due to the thinness of the substrate) , increases current carrying capability over that of the prior art chips which require either the buried layer or current being transmitted through the relatively thick bulk of the semiconductor substrate.
  • the actual thickness of the final substrate itself is the minimum necessary to support (mechanically and electrically) the active transistor regions.
  • This thickness may be as little as 10 microns, in contrast to prior art integrated circuits typically having a 400 micron die thickness needed for mechanical support for the integrated circuit.
  • the step of removing the backside portion of the substrate after trench formation means that the initial trench depth need not be precisely determined.
  • formation of trenches of precise depth is a significant processing limitation.
  • exact trench depth is not critical.
  • the fabrication process in accordance with the invention advantageously allows for an isolated backside contact structure which is not a single contact but a plurality of individual backside contacts, each contact associated with a particular portion of the die.
  • first backside contact to a power transistor portion of the integrated circuit
  • second backside contact associated with a low voltage transistor portion of the integrated circuit.
  • backside contacts are selectable for a particular portion of the integrated circuit, and various portions of the chip need not share a common collector or common drain.
  • the passivation layer which serves as an isolation layer and an attachment layer to bond the IC wafer (substrate) to the heat sink cap or plate is a CVD (Chemical Vapor Deposition) diamond film.
  • CVD Chemical Vapor Deposition
  • Such material advantageously has high thermal conductivity and high electric resistivity.
  • the diamond film is deposited on top of the substrate after the final front side surface metal patterning.
  • a thermally conductive adhesive (such as silver epoxy) is applied to the exposed surface of the deposited diamond film to attach the substrate to the plate.
  • This use of diamond film is compatible both with the surface mount and flip chip embodiments described above.
  • the diamond layer may be patterned so that particular portions of the metal contact or bonding pads are connected to and through the support plate to external leads from the front side of the wafer, in the flip chip embodiment.
  • Figs. 1 to 12 illustrate exemplary fabrication steps of the surface mount embodiment of the invention.
  • Figs. 13 to 17 illustrate exemplary fabrication steps of the flip chip type embodiment of the invention.
  • Figs. 1 to 12 illustrate steps to fabricate a surface mount integrated circuit chip in accordance with the invention. It is understood that these are conventionally drawn cross sections of an integrated circuit showing only a small portion of the circuit, i.e. a small portion of a wafer. No topside views are provided, since the top side geometry of the integrated circuit is conventional, as will be understood by one of ordinary skill in the art from the following description. Also, this is only an illustration of the surface mount approach, which is not limited to semiconductor devices of the type shown.
  • Fig. 1 shows initial steps in fabrication of this embodiment.
  • Fig. 1 is conventional both in structure and fabrication as typically used for integrated circuits which include both power transistors and low voltage transistors on one chip. See U.S. Patent Application No. 07/948,276, filed 9/21/92, Hamza Yilmaz et al., entitled "BiCDMOS Process Technology and
  • Fig. 1 Shown in Fig. 1 is silicon (or other material) substrate 10 which is conventionally N+ doped, having formed on an upper portion thereof in one embodiment an epitaxial
  • (silicon) layer 20 which is conventionally N- doped.
  • the epitaxial layer is an option but is not a necessary part of the invention; the active portions of the transistors may be formed in the substrate. (It is to be understood that materials, dimensions, transistor structure, conductivity types, and other elements disclosed herein are illustrative only and not limiting. )
  • Substrate 10 is approximately 500 micrometers thick, and silicon layer 20 is 1 to 50 micrometers thick.
  • Conventionally formed (in this illustrative embodiment) in silicon layer 20 are two "deep body” conventionally doped P+ regions 22 and 24.
  • Formed respectively in body regions 22 and 24 are N+ source regions 26, 28, 30 and 32 each of which is conventionally doped. It is to be appreciated that in this embodiment P+ body regions 22 and 24 and the associated other doped regions are a part of a power portion of the integrated circuit, i.e. power transistors.
  • Formed adjacent to regions 22 and 24 is P tub 38 which is conventionally doped.
  • Formed in P tub 38 are N+ doped regions 40 and 42.
  • silicon layer 20 Also formed in silicon layer 20 are P+ regions 46 and 48 which are similar in their doping level and structure to region 44, and N+ region 50 which is similar to regions 40 and 42.
  • a conventional gate oxide layer 60 Formed immediately overlying the upper surface of silicon layer 20 is a conventional gate oxide layer 60 of e.g. silicon dioxide.
  • a doped polysilicon gate electrode layer 54 including (as a result of a masking step) portions 54a, 54b, 54c and 54d and 54e which in this embodiment form the gate electrodes of various transistors.
  • Overlying gate electrode layer 54 is a second overlying (upper) insulative layer 62 formed of silicon dioxide and also covering the respective side edges of the gate electrodes 54a, ..., 54e.
  • BPSG layer 64 borophosphorsilicate glass formed to a thickness of 0.5 to 1.5 micrometers and then conventionally reflowed to completely cover gate electrodes 54a, ..., 54e.
  • Fig. 2 shows subsequent processing with a conventional masking layer 70 formed overlying BPSG layer 64.
  • Masking layer 70 is conventionally patterned and the underlying structure etched, with the etchant penetrating through silicon layer 20 and into substrate 10 to define trenches 72a, 72b, 72c, 72d, and 72e. These trenches are 0.5 to 5 micrometers in width and 5 to 50 micrometers in depth. (The depth is relatively arbitrary for reasons discussed later and the width dimension is also not critical.)
  • the trench etch is a conventional anisotropic process. It is to be understood that trenches 72a, ..., 72e as shown here in cross-section, would in a topside view interconnect so as to surround various portions of the integrated circuit, i.e. so as to surround the power transistor portion 22, 24 thereby separating this portion from the portion including P tub 38.
  • a glass layer 76 is formed conventionally such as by being spun on in each of trenches 72a, ... , 72e thereby filling each of these trenches, and also overlying the upper surface of BPSG layer 64, to a thickness of 1 to 2 micrometers.
  • SOG chemical vapor deposition
  • Alternatives to SOG for layer 76 are CVD formed materials or plasma enhanced CVD formed materials. After formation of spun on glass layer 76, this material is cured. Spun on glass 76 here is the trench dielectric insulating material. In other embodiments, the trenches e.g.
  • etch back (planarization) step using for instance CMP of the spun on glass layer 76 effectively removes those parts of layer 76 overlying the gate electrodes 54a, ..., 54e.
  • CMP is to apply a layer of photoresist then etch back using a dry etch.
  • an LTO (low temperature oxide) layer 80 is deposited over the upper surface of the structure to a thickness of 0.5 to 2.0 micrometers.
  • an electrical contact mask layer (not shown) is applied overlying LTO layer 80. The contact mask layer is then conventionally patterned and the underlying layers etched, with the etch extending through LTO layer 80, through the remaining portions of spun on glass layer 76, and down to the principal surface of the silicon layer 20, thus exposing portions of the principal surface of the silicon layer 20 and defining contact openings 84a, ... , 84g.
  • a layer of conductive material 90 (such as aluminum) is conventionally deposited over the surface of the substrate, filling the various contact openings 84a, ..., 84g and making contact with the underlying semiconductor regions formed in silicon layer 20. Then conductive layer 90 is conventionally masked, the masking layer is patterned, and layer 90 is etched to define electrical contacts 90a, ... , 90g.
  • a conventional passivation layer of e.g. plasma nitride material is formed overlying electrical contacts 90a, ... , 90g.
  • Passivation layer 96 is 0.5 to 2.5 micrometers thick.
  • an epoxy material layer 98 is conventionally deposited 25 to 250 micrometers thick.
  • This epoxy material 98 is e.g. a high performance epoxy resin composition that is thermally conductive (such as silver epoxy) .
  • a "cap" (plate) 100 is affixed to epoxy layer 98 which is then cured, bonding cap 100 to passivation layer 96.
  • Cap 100 is about 500 micrometers thick and is e.g. undoped silicon.
  • a single cap 100 covers the entire wafer which includes substrate 10 and silicon layer 20. Other bonding materials and processes other than epoxy may be used to affix cap 100. Cap 100 achieves thermal conductivity through epoxy layer 98 and also provides sufficient mechanical support for the substrate 10, silicon layer 20, and the active transistor regions and interconnect formed thereon.
  • the backside surface of substrate 10 is partially removed by grinding, etching, or CMP (chemical-mechanical polishing) so that the total thickness of substrate 10 and/or silicon layer 20 is in the range of 5 to 100 microns. This is in contrast to the original total thickness of structures 10 and 20 of about 500 microns. (Again, these dimensions are illustrative and not limiting.)
  • the goal is to reduce the thickness of substrate 10 and silicon layer 20 to a minimum necessary for electrical functioning of the transistors formed therein.
  • the removing step reduces the thickness of substrate 10 so that the bottom portion of each of trenches 72a, ..., 72e is exposed, and thereby the insulative material formed in each of these trenches is exposed at the backside surface of substrate 10.
  • heat sink cap 100 is done prior to the removing step to ensure that the substrate, after the removing step, remains in one integrated piece.
  • Conventional masking, implantation, and annealing steps may be added to this process, as desired to form N+ or P+ contacts on the backside surface of substrate 10 for subsequent metal layer 104.
  • the backside surface of substrate 10 is metallized by a conventional sputtering or evaporative process to form a metal layer 104 (aluminum) thereon having a thickness of e.g. 0.15 to 1.5 micrometers.
  • metal layer 104 is conventionally covered with a mask layer, the mask layer is patterned, and metal layer 104 then etched to define backside contact pads 104a, 104b on the backside surface of substrate 10.
  • Each of contact pads 104a, 104b is associated with a selected portion of the integrated circuit die as defined by the trenches 72a, ..., 72e.
  • each portion of the die need not have a contact pad; contact pads 104a, 104b are only provided to those portions of the die which require same. (It is to be understood that conventionally some types of transistors do not require backside contacts.)
  • a protective/passivation layer 110 is deposited on the backside surface of substrate 10 overlying contact pads 104a and 104b.
  • layer 110 is conventionally patterned to define openings 112a and 112b.
  • Each opening 112a and 112b is associated with a particular electrical contact 90a, 90g on the upper side surface of silicon layer 20, as shown.
  • a deep silicon etch is undertaken through openings 112a and 112b to define vias 116a, 116b extending through substrate 10 and/or silicon layer 20 to expose the underside portions of electrical contacts 90a, 90g.
  • This deep silicon etching step uses a wet or wet/dry or dry etching technique.
  • Vias 116a, 116b need only be wide enough to establish good electrical paths to contacts 90a, 90g and otherwise their dimensions in terms of width are not critical; neither is their cross-sectional shape critical. Then as shown in Fig. 10 the remaining portions of layer 110 may be conventionally stripped off or kept as a passivation layer.
  • a plating step electrodeposi- tion
  • vias 116a and 116b are filled with a solderable metal (e.g. nickel, gold, copper) to define posts 124, 130 extending therefrom.
  • metal posts 126, 128 are deposited on metal contacts 104a, 104b.
  • posts 126, 128 are formed by screen printing the desired type of metal on respectively the backside 104, 104b interconnection leads to establish the desired thickness for the surface mount posts.
  • the diameter of the surface mount posts may vary, depending on the particular application.
  • an (optional) passivation layer 136 is deposited over all exposed surfaces of the surface mount posts 124, 126, 128 and 130 to a thickness of 0.8 to 1.2 micrometers.
  • Passivation layer 136 is e.g. polyamide or low temperature oxide.
  • passivation layer 136 is removed (by masking and etching or other means, for instance CMP) from the bottom surfaces of each surface mount post 124, 126, 128, 130, so as to leave the post bottom surfaces exposed for soldering, such as to a printed circuit board.
  • the height of the surface mount posts extending from the lower backside surface of substrate 10 is conventionally 10 to 300 micrometers, or any other height as needed depending on the mounting application.
  • Fig. 12 all of the electrical interconnections to outside of the chip are provided on the backside surface of substrate 10 by the surface mount posts 124, 126, 128 and 130. Subsequently (not shown) the wafer is scribed into individual integrated circuit die along predescribed scribe lines which are for instance adjacent to dielectrically filled trenches. Thus as a result of the scribing step, the various integrated circuit die are already packaged by the top side cap 100 and the bottom side passivation layer 136; hence no further packaging is needed.
  • the initial processing steps are identical to those shown in Figs. 1 to 5 for the surface mount embodiment, resulting in the structure of Fig. 13.
  • the flip chip embodiment is not limited to semiconductor devices of the type shown.
  • the structure of Fig. 13 is identical to that of Fig. 5, except that in Fig. 13 the next step is that passivation layer 160 (which is similar in material and thickness to passivation layer 96 in Fig. 6) is masked using a mask layer (not shown) which is patterned, with subsequent etching to define contact openings 164a, 164b, therethrough.
  • Contact openings 164a, 164b expose a portion of the underlying electrical contacts 90a, 90g.
  • the goal in this embodiment is to define both substrate frontside and backside electrical contacts; openings 164a, 164b define the frontside contact openings.
  • silicon (or other suitable material) heat sink cap 172 is provided, having formed thereon (prior to assembly to the substrate 10) metal (aluminum or a solderable material) interconnect structures 176a, 176b.
  • Interconnect structures 176a, 176b include interconnect lines on the surface of cap 172 which faces contacts 90a, 90b; these interconnect lines have a thickness of e.g. 10 to 50 micrometers.
  • Cap 172 is electrically insulated on all surfaces by e.g. oxide dielectric layer 175. Interconnect structures 176a, 176b are then conventionally soldered or sintered to underlying contacts 90a, 90g. This electrical contact can be provided by any other conventional method.
  • Cap 172 is attached to the underlying structure by a high performance thermally conductive (and electrically insulative) epoxy resin layer 168 (or other high performance adhesive) formed on passivation layer 160 to a thickness of 25 to 250 micrometers. Adhesive layer 168 is prevented from fouling the electrical interconnections (between elements 176a,
  • 176b and 90a, 90b) by masking and etching the adhesive layer 168 or by polishing it away from the interconnections.
  • adhesive layer 168 is initially formed in a thick layer covering structures 176a, 176b, then etched back to expose the ends of structures 176a, 176b using a wet or dry etch.
  • cap 172 serves as a heat sink and supports contact structures 176a, 176b which connect through vias extending through cap 172 to form interconnect contacts 174a, 174b on the opposite surface of cap 172.
  • These interconnect contacts 174a, 174b are suitable for attachment to an underlying supporting conventional flip chip-type back plate (not shown) providing mechanical support and electrical bonds thereto.
  • backside surface of substrate 10 is polished or etched away to expose the lower portions of dielectrically insulated trenches 72a, ..., 72e. Again, the total thickness of substrate 10 and silicon layer 20 is minimized by this removing step to that needed for proper electrical functioning.
  • backside contacts 178a, 178b are formed, similar to contacts 104a, 104b in Fig. 8.
  • backside passivation layer 186 is deposited to a thickness of e.g.
  • oxide or nitride or an oxide-nitride "sandwich" material over the backside surface of substrate 10 and initially over contact areas 178a and 178b, but is then removed from the exposed surfaces by use of a mask which is then patterned, and etching away of the unneeded portions of passivation layer 186.
  • Fig. 17 provides both frontside substrate electrical contacts 174a, 174b through cap 172 and also backside contacts 178a, 178b.
  • the frontside leads are beam or tunnel lead structures or types to the transistors.
  • the above-described flip chip type and surface mount embodiments use conventional silicon dioxide or nitride as the dielectric insulation and passivation layer between the semiconductor wafer itself and the heat sink plate. These materials are known to provide relatively poor heat conduction, due to for instance the very low thermal conductivity of silicon dioxide of approximately 2 W/mK. In contrast, diamond film (which is also a good dielectric insulating material) provides thermal conductivities of about 2,000 W/mK. Also diamond is well known to be chemically inert, and due to its having the densest crystal lattice of any known material, the diffusion of other elements into diamond is very low. Thus diamond is not only a good dielectric insulator with excellent thermal conductivity but it is also a material which serves effectively as a passivation layer, providing good corrosion protection.
  • diamond film has the best combination of thermal conductivity and electrical resistivity of available materials.
  • Other materials such as aluminum nitride, aluminum oxide, or silicon carbide also provide high dielectric insulation but much less thermal conductivity than diamond.
  • the only materials providing thermal conductivity similar to that of diamond film are electrically conductive metals such as copper and silver, which are not useful for passivation.
  • CVD chemical vapor deposition
  • methane or acetylene is used as the carbon source with significant partial pressure of atomic hydrogen.
  • Excitation sources used include microwave and radio frequency plasmas, hot filament and thermal plasmas and combustion flames.
  • Methods for depositing diamond film in accordance with the present invention include low temperature microwave plasma assisted CVD.
  • An alternative is an arc jet CVD process. It is known to pattern diamond films using conventional oxygen-based RIE (reactive ion etching) processes, as are well known in semi-conductor fabrication.
  • RIE reactive ion etching
  • a diamond film formed by one of the above described processes is substituted for passivation layer 96.
  • the diamond film is formed to be a layer e.g. approximately 0.5 to 10 micrometers thick (but this is not limiting) .
  • a thermally conductive adhesive such as commercially available silver epoxy is used to bond the plate 100 to the diamond film. All other processing steps are as described above for this embodiment.
  • passivation layer 160 is a CVD (or other type) diamond film approximately 0.5 to 10 micrometers thick (again this dimension is not limiting) .
  • This diamond film is, as described above for the non-diamond film flip chip type embodiment, masked using a mask layer to pattern it to define the contact openings 164A, 164B therethrough.
  • the remaining of the processing is as described above, using a thermally conductive (but electrically insulative) high performance adhesive to bond the heat sink cap 172 to the diamond film passivation layer 160.
  • the process steps in terms of structure are similar to those described above for the non-diamond film flip chip type embodiment, except for the presence of the diamond film passivation layer material.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Puce à circuit intégré dans laquelle chaque partie présente une isolation diélectrique des sillons tout entiers. Un couvercle de puits thermique (100) est attaché à une couche de passivation diamantée (96) sur la surface avant du substrat. Cette couche de passivation est un film diamanté déposé chimiquement en phase vapeur qui assure à la fois l'isolation électrique et la conductivité thermique. Dans une version de puce à protubérances, des contacts électriques avant (174a, 174b) s'étendent à travers la couche de passivation avant jusqu'au couvercle de puits thermique. Dans une version de montage en surface, des voies sont pratiquées dans le substrat par attaque chimique, des supports (90a, 90b) de montage en surface étant formés sur les voies pour se trouver en contact avec les contacts électriques avant et assurer tous les contacts électriques sur la surface arrière du substrat. La tranche est ensuite découpée en dé dans les deux versions sans nécessiter d'autre conditionnement.
EP95918863A 1994-05-05 1995-05-04 Montage en surface et technologie de puce a protuberances Withdrawn EP0707741A4 (fr)

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Application Number Priority Date Filing Date Title
US23855294A 1994-05-05 1994-05-05
US238552 1994-05-05
US32193794A 1994-10-12 1994-10-12
US321937 1994-10-12
PCT/US1995/005217 WO1995031006A1 (fr) 1994-05-05 1995-05-04 Montage en surface et technologie de puce a protuberances

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EP0707741A1 EP0707741A1 (fr) 1996-04-24
EP0707741A4 true EP0707741A4 (fr) 1997-07-02

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JP (1) JP4308904B2 (fr)
KR (1) KR100232410B1 (fr)
AU (1) AU2462595A (fr)
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WO (1) WO1995031006A1 (fr)

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US9238207B2 (en) 1997-04-04 2016-01-19 Chien-Min Sung Brazed diamond tools and methods for making the same
US9463552B2 (en) 1997-04-04 2016-10-11 Chien-Min Sung Superbrasvie tools containing uniformly leveled superabrasive particles and associated methods
US9409280B2 (en) 1997-04-04 2016-08-09 Chien-Min Sung Brazed diamond tools and methods for making the same
US9221154B2 (en) 1997-04-04 2015-12-29 Chien-Min Sung Diamond tools and methods for making the same
US9199357B2 (en) 1997-04-04 2015-12-01 Chien-Min Sung Brazed diamond tools and methods for making the same
US9868100B2 (en) 1997-04-04 2018-01-16 Chien-Min Sung Brazed diamond tools and methods for making the same
DE19718618C2 (de) 1997-05-02 1999-12-02 Daimler Chrysler Ag Komposit-Struktur mit einem mehrere mikroelektronische Bauteile und eine Diamantschicht aufweisenden Wachstums-Substrat sowie Verfahren zur Herstellung der Komposit-Struktur
FR2793953B1 (fr) * 1999-05-21 2002-08-09 Thomson Csf Capacite thermique pour composant electronique fonctionnant en impulsions longues
JP4761644B2 (ja) * 2001-04-18 2011-08-31 三菱電機株式会社 半導体装置
WO2002101829A1 (fr) * 2001-06-13 2002-12-19 Advanpack Solutions Pte Ltd Procede de formation d'un boitier a puce au niveau de la plaquette et boitier obtenu
EP2560199B1 (fr) 2002-04-05 2016-08-03 STMicroelectronics S.r.l. Procédé de fabrication d'une interconnexion isolée traversant un corps de matériau semi-conducteur
JP2004104074A (ja) * 2002-07-17 2004-04-02 Sumitomo Electric Ind Ltd 半導体装置用部材
US7301223B2 (en) * 2003-11-18 2007-11-27 Halliburton Energy Services, Inc. High temperature electronic devices
FR2874127B1 (fr) * 2004-08-03 2006-12-08 United Monolithic Semiconduct Boitier miniature hyperfrequence pour montage en surface et procede de fabrication du boitier
US9724802B2 (en) 2005-05-16 2017-08-08 Chien-Min Sung CMP pad dressers having leveled tips and associated methods
US9138862B2 (en) 2011-05-23 2015-09-22 Chien-Min Sung CMP pad dresser having leveled tips and associated methods
US8678878B2 (en) 2009-09-29 2014-03-25 Chien-Min Sung System for evaluating and/or improving performance of a CMP pad dresser
US8393934B2 (en) 2006-11-16 2013-03-12 Chien-Min Sung CMP pad dressers with hybridized abrasive surface and related methods
US8324103B2 (en) 2006-02-01 2012-12-04 Silex Microsystems Ab Vias and method of making
FR2923080A1 (fr) * 2007-10-26 2009-05-01 St Microelectronics Rousset Procede de fabrication d'un via dans une plaquette de semi-conducteur
FR2955202B1 (fr) * 2009-12-10 2012-08-03 St Microelectronics Crolles 2 Dispositif microelectronique integre avec liaisons traversantes.
WO2012162430A2 (fr) 2011-05-23 2012-11-29 Chien-Min Sung Tampon de polissage mécano-chimique (cmp) à pointes nivelées et procédés associés
JP7232137B2 (ja) * 2019-06-25 2023-03-02 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
DE102019122888A1 (de) * 2019-08-27 2021-03-04 Infineon Technologies Ag Leistungshalbleitervorrichtung und Verfahren

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DE707741T1 (de) 1996-11-28
JP4308904B2 (ja) 2009-08-05
WO1995031006A1 (fr) 1995-11-16
EP0707741A1 (fr) 1996-04-24
KR100232410B1 (ko) 1999-12-01
JPH09500240A (ja) 1997-01-07
AU2462595A (en) 1995-11-29

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