EP0624290B1 - Verfahren zur kaskadierung von sigma-delta modulatoren und ein sigma-delta modulatorsystem - Google Patents

Verfahren zur kaskadierung von sigma-delta modulatoren und ein sigma-delta modulatorsystem Download PDF

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EP0624290B1
EP0624290B1 EP93914539A EP93914539A EP0624290B1 EP 0624290 B1 EP0624290 B1 EP 0624290B1 EP 93914539 A EP93914539 A EP 93914539A EP 93914539 A EP93914539 A EP 93914539A EP 0624290 B1 EP0624290 B1 EP 0624290B1
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modulator
signal
error
quantized
scaling
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French (fr)
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EP0624290A1 (de
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Tapani Ritoniemi
Teppo Karema
Hannu Tenhunen
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/414—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type
    • H03M3/418—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type all these quantisers being single bit quantisers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/02—Delta modulation, i.e. one-bit differential modulation

Definitions

  • the invention relates to a method for cascading at least two sigma-delta modulators, wherein an error of one modulator in the cascade is quantized by the next modulator in the cascade; the quantized error is differentiated; and the differentiated error is subtracted from the quantized output signal of said one modulator.
  • sigma-delta modulators also known as delta-sigma modulators
  • the signal is quantized by using only a small number of quantization levels (2 - 256, which corresponds to an A/D converter with a resolution of 1 to 8 bits) at a high rate, usually 32 - 512 times the signal frequency.
  • the ratio between the Nyquist sampling frequency (two times the useful signal band) and the used high sampling frequency is also called oversampling ratio (M).
  • M oversampling ratio
  • a quantizer is a combination of an A/D and a D/A converter, in which an analog signal is converted by the A/D converter to a discrete digital value which is then immediately converted back to an analog voltage (value) by the D/A converter.
  • a quantizing error (e k ) is the difference voltage (value) between the analog input voltage and the analog output voltage, and the quantizing noise is the spectrum (Q e ) of the quantizing error; in the case of the sigma-delta modulator, the quantizing noise can be regarded as white noise.
  • the effective value (E) of the white noise in a one-bit quantizer is (q/2) 2 with a one-bit, where q is the spacing between the quantization levels.
  • a sigma-delta modulator configuration is such that the quantizer error transfer function (NTF) to the output of the modulator is different from the signal transfer function (STF) from the input to the output of the modulator.
  • the object is to provide a quantizing error transfer function NTF with the highest possible attenuation within a desired passband while the signal transfer function STF is as uniform as possible over the whole passband.
  • the STF and NTF are interdependent in a manner determined by the used modulator structure.
  • the order of the modulator is the order of the NTF function, or the number of integrators in the modulator. By increasing the order of the modulator the amount of quantizing noise in the passband can be decreased.
  • Another way of decreasing the amount of quantizing noise in the passband is to increase the oversampling ratio; however, an increase in the oversampling ratio increases the sampling frequency which in turn is limited by the components used in the implementation.
  • the only way to improve the ratio (S/N q ) between the signal (S) and the quantizing noise (N q ) in the passband is to increase the order of the modulator or to improve the NTF so that the attenuation in the passband is increased while the order of the modulator and the oversampling ratio remain unchanged.
  • a conventional sigma-delta modulator with directly series-connected integrators is, however, difficult to implement due to the oscillation caused by the feedback loop. Therefore higher-order sigma-delta modulators have been formed by cascading two or more stable lower-order sigma-delta modulators.
  • the quantizing error of the first modulator in the cascade connection (the difference between the input and output signals of the quantizer) is applied to the second modulator in the cascade, and the amount of quantizing noise over the signal band can be decreased by suitably interconnecting the outputs of the blocks.
  • a 16-bit Oversampling A-to-D Conversion Using Triple-Integration Noise Shaping, IEEE Journal of Solid State Circuits, Vol. SC-22, No. 6, December 1987, p. 921 to 929 describes the cascading of first-order sigma-delta modulators by the so-called MASH technique.
  • FI Patent 80548 describes the cascade connections of second-order multiple-feedback modulators.
  • the object of the present invention is to cascade two sigma-delta modulator blocks to achieve a better SNRQ than what was possible in the prior art modulator system of the same order and with the same oversampling ratio.
  • At least two nth-order sigma-delta modulator blocks realized by a 1-bit quantizer are cascaded so that each subsequent modulator block quantizes the signal estimate error voltage formed in the preceding modulator block, scaled by a scalar 1/C to the operating range of the subsequent modulator.
  • the 1-bit data of the subsequent modulator block is filtered by a digital filter having a transfer function which is the inverse of the transfer function of the integrators of the first modulator block, and scaled by a scalar C, and then subtracted from the 1-bit data of the first block, which data has been delayed in an amount corresponding to the delay caused by the subsequent modulator block.
  • the signal estimate error of the first block, quantized by the subsequent modulator block can be subtracted from the output of the first block, and the accuracy of the signal estimate is improved and the amount of quantizing noise on the signal band is reduced.
  • the obtained digital output is the output of a 2*nth-order sigma-delta modulator.
  • the prior art re-quantization of the quantizing error and the substraction of the error from the output of the first block linearizes the attenuation across the quantizer to a constant value (1), so that the signal transfer function is determined by the STF of the first modulator block.
  • the modulator blocks used in the invention are of the FF-type. According to the invention the blocks are at least of the second order. The STF of the two blocks must be equal.
  • the signal estimate error is the voltage difference between the feedbacked quantized signal (voltage) and the analog input voltage. However, the signal estimate error is integrated n times (n is the number of the integration stages) before it is applied to the subsequent (next) modulator. In addition, it is possible to subtract an appropriately weighted signal estimate (a 1-bit quantized voltage) from the signal estimate error.
  • the cascade connection can improve the signal-to-noise ratio (S/N+N q ) in practical applications, because the required voltage scaling in the input of the first modulator block is smaller than in the prior art cascaded modulators.
  • the sensitivity of the modulator to the noise (N) of the circuit elements is at highest in the input stage, and so the performance of nearly all modulators (with an accuracy higher than 16 bits) is limited by the noise of the circuit elements of the first integrator. With less voltage scaling the physical noise (N) of the circuit elements is relatively smaller.
  • the invention also relates to a sigma-delta modulator system comprising a first sigma-delta modulator having at least two integration stages and a quantizing means for quantizing a primary signal; a means for providing an error signal representing the quantizing noise of the first modulator; a second sigma-delta modulator means having at least two integration stages and a quantizing means, for quantizing said error signal; a differentiation means having a transfer function substantially equal to the inverse function of the common transfer function of the integration stages of the first modulator means, for differentiating the output signal of the second modulator means; a means for delaying a quantized primary signal in an amount corresponding to the delay of the second modulator means; and a means for subtracting the differentiated error signal from the delayed quantized primary signal.
  • Oversampling generally means that the sampling frequency Fs is substantially higher than the lowest sampling frequency determined by the Nyquist criterion, which is two times the highest frequency of the signal.
  • the sampling frequency usually applied in oversampling is an integer multiple of the Nyquist frequency, e.g. 32 or 64 (oversampling ratio).
  • the invention is applicable in any applications utilizing a higher-order sigma-delta modulator.
  • Figure 1 illustrates generally the cascading of two nth-order modulators SD1 and SD 2 according to the invention, but it is equally possible in the invention to cascade several modulators in the same way.
  • An input signal Din to be quantized is applied to a first modulator block SD1, which produces a quantized 1-bit output signal D', which is delayed in a delay block 5 by a delay z -k , and the delayed quantized signal D" is applied to one input in a subtractor means 6.
  • An integrated signal estimate error e of the modulator block SD1 is first scaled by a coefficient 1/C and then applied to the second modulator block SD2, which produces a quantized error signal e'.
  • the signal e' is differentiated by a digital filter block 3 forming a differentiator, the transfer function (1-z- -1 ) n of the filter block 3 being substantially equal to the inverse function of the common transfer function of the integration stages of the modulator block SD1.
  • the differentiated and quantized error signal e" is scaled by a coefficient C (the reciprocal of 1/C), and the scaled error signal e q is applied to another input in the subtractor means 6.
  • the quantized error signal e q is subtracted from the delayed quantized primary signal D", so that only the 2*nth-order quantizing noise of the modulator block SD2, differentiated n times, is retained in the output signal D' of the system.
  • the modulator blocks SD1 and SD2 are of the same order and have the same coefficient values. If the modulator blocks SD1 and SD2 are not of the same order or have not the same number of delays, the digital filter block 3 is difficult to implement as not only the FIR differentiator but also the IIR part has to be realized by it. Therefore the cascading of modulator blocks SD1 and SD2 of unequal order is a less interesting application. Accordingly, in the preferred embodiments of the invention, the order n of the differentiator realized by the block 3 is equal to the order of the modulator blocks SD1 and SD2, and it eliminates the effect of the common transfer function of the integrations of the modulator block SD1 on the quantized error signal e'.
  • the delay k of the delay block 5 has to be equal to the delay of the modulator block SD2, that is, the combined delay of its integrators.
  • the error signal is scaled by a coefficient 1/C, and so the voltage of the error signal will fall within the linear operating range of the block SD2. Thereafter the digital output of the block SD2 is scaled by the coefficient C so that the original signal level will be restored.
  • the minimum value of the coefficient C is the ratio between the modulator coefficients b n /b 1 .
  • the system is operative even at higher scaling coefficients C, although the SNRQ deteriorates with the increasing coefficient.
  • Nth-order feedforward modulator structures will be described below as illustrating embodiments, which can be used as the blocks SD1 and SD2 in the modulator system according to the invention.
  • FIG. 2 shows a feedforward modulator structure suitable for use as SD1, comprising a series connection of a subtractor 26 and n integration stages 21-1 ... 21-n in this order.
  • the output voltage D 1 -D nN of each integration stage 21-1 ... 21-n is connected through a respective scaling means 24-1 ... 24-n (each voltage being scaled by a respective coupling coefficient bl-bn) to a summing means 25, which combines the scaled voltages D 1 -D n and applies the sum voltage Ds to a quantizer 23.
  • the quantizer 23 is a combination of an A/D and a D/A converter, in which the analog voltage Ds is converted by the A/D converter 23A to a discrete digital value D', which is the output signal of the modulator SD1 and which is immediately thereafter converted back to an analog voltage Df (value) by the D/A converter 23B so as to establish a negative feedback from the output of the quantizer 23 to the input of the modulator SD1.
  • the quantized output signal D' that is, the signal estimate
  • the difference voltage DO between the voltages Din and Df is the signal estimate error.
  • the output voltage of the last integration stage 21-n that is, the integrated signal estimate error Dn may be the error voltage e applied to the next modulator stage SD2 when scaled by the coefficient 1/C in a scaling means 28.
  • the modulator does not comprise a subtractor 27 and a scaling means 29.
  • a subtractor 27 to one input of which the output voltage of the integration stage 21-n is applied.
  • the output signal D' of the quantizer 23 is weighted (after having been converted into an analog voltage by the A/D converter 23B) by a scaling coefficient x (where O ⁇ x ⁇ 4*b1/b2) in the scaling means 29 and further applied to another input in the subtractor 27 (as shown by the broken lines) so as to be subtracted from the voltage Dn, that is, from the integrated signal estimate error to obtain their difference voltage e, which is preferably scaled in a scaling means 28 by a scaling coefficient 1/C smaller than one (at least b n /b 1 ) to decrease the signal level to the operating range of the next modulator block SD2.
  • Figure 3 shows a feedforward-type sigma-delta modulator structure suitable for use as the modulator block SD2.
  • the modulator comprises a series connection of a subtractor 36 and n integration stages 31-1 ... 31-n in this order.
  • the output voltage e 1 -e n of each integration stage 31-1 ... 31-n is connected through a respective scaling means 34-1 ... 34-n (each voltage being scaled by a respective coupling coefficient b1-bn) to a summing means 35.
  • the output voltage of the last integration stage 31-n is connected to the summing means 35 through a delay block 37 connected in series with the scaling means 34-n.
  • the summing means 35 combines the scaled voltages e 1 -e n and applies the sum voltage es to a quantizer 33.
  • the quantizer 33 is a combination of an A/D and a D/A converter, in which the analog voltage es is converted by the A/D converter 33A into a discrete digital value e', which is the output signal of the modulator SD2 and which is immediately thereafter converted back to an analog voltage ef (value) by the D/A converter 33B so as to establish a negative feedback from the output of the quantizer 33 to the input of the modulator SD2.
  • the quantized output signal e' that is, the signal estimate is converted into an analog voltage ef by the D/A converter 33B and applied to one input in the subtractor 36 to be subtracted from the input voltage e of the integration stage 31-1.
  • the output of the quantizer 33 gives a quantized error signal e' which is applied to the differentiator block 3 shown in Figure 1.
  • the output voltage e n of the integration stage 31-n is feedbacked through a scaling means 39 having a feedback coefficient "a" to a subtractor 38 in the input of the preceding integration stage 31-(n-1) to be subtracted from the input voltage of the integration stage.
  • the subtractor 38 is, of course, omitted if the feedback is not provided.
  • the transfer of the transmission zeros from the zero frequency imposes a few additional requirements on the blocks SD1 and SD2.
  • the integrators of the modulator blocks SD1 and SD2 have to be delayed (generally a delay of at least two clock periods in the outermost modulator feedback loop of the quantized value, including the integrator delays; and a delay of one or two clock periods for the feedback "a", including the integrator delays) in order that the block SD2 could produce a transmission zero in the noise function. If the feedback loop "a" comprises one delay, the transmission zero will be positioned accurately on the unit circle of the z domain, and infinite attenuation will be obtained at this point.
  • the transmission zero will be positioned on a line which is tangent to the unit circle at a point (1, 0) so that an absolutely accurate transmission zero is obtained at this point only; the zeros, however, are positioned so close to the circumference of the unit circle at oversampling ratios greater than 64 that there is no significant difference in the amount of quantizing noise on the signal band as compared with the accurate zero. If the order n of the modulator blocks SD1 and SD2 is higher than or equal to 3, the modulator block SD2 has to comprise at least two delayed integration stages to achieve the transmission zero.

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Claims (9)

  1. Verfahren zum Kaskadieren mindestens zweier Sigma-Delta-Modulatoren vom Vorwärtskopplungstyp, wobei
    ein Fehler eines Modulators in der Kaskade durch den nächsten Modulator in der Kaskade quantisiert wird,
    der quantisierte Fehler differenziert wird
    und der differenzierte Fehler vom quantisierten Ausgangssignal des einen Modulators subtrahiert wird,
       dadurch gekennzeichnet, daß der Fehler der Fehler bei der integrierten Signalabschätzung des einen Modulators ist.
  2. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß das Fehlersignal die Ausgangsspannung der letzten Integrationsstufe des einen Modulators ist.
  3. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß das Fehlersignal erhalten wird, indem das quantisierte Ausgangssignal des einen Modulators um einen vorbestimmten Skalierkoeffizienten skaliert und das skalierte quantisierte Ausgangssignal von der Ausgangsspannung der letzten Integrationsstufe des einen Modulators subtrahiert wird.
  4. Sigma-Delta-Modulator-System, das folgendes umfaßt:
    einen ersten Sigma-Delta-Modulator (SD1) mit mindestens zwei Integrationsstufen (21) und einem Quantisiermittel (23) zum Quantisieren eines Hauptsignals (Din);
    ein Mittel zum Bereitstellen eines Fehlersignals (e), das das Quantisierrauschen des ersten Modulators (SD1) darstellt;
    ein zweites Sigma-Delta-Modulator-Mittel (SD2) mit mindestens zwei Integrationsstufen (31) und einem Quantisiermittel (33) zum Quantisieren des Fehlersignals (e);
    ein Differenzierungsmittel (3) mit einer der Umkehrfunktion der gemeinsamen Übertragungsfunktion der Integrationsstufen des ersten Modulatormittels im wesentlichen gleichen Übertragungsfunktion zum Differenzieren des Ausgangssignals (e') des zweiten Modulatormittels;
    ein Mittel (5) zum Verzögern eines quantisierten Hauptsignals (D') in einem Umfang, der der Verzögerung des zweiten Modulatormittels (SD2) entspricht; und
    ein Mittel (6) zum Subtrahieren des differenzierten Fehlersignals (e", eq) von dem verzögerten Hauptsignal (D"), dadurch gekennzeichnet, daß das Fehlersignal (e) der integrierte Fehler der Signalabschätzung des ersten Modulators (SD1) ist.
  5. System nach Anspruch 4, dadurch gekennzeichnet, daß der erste Modulator (SD1) ein Summiermittel (25) zum Summieren der skalierten Ausgangsspannungen (D1-Dn) der Integrationsstufen (21) und zum Anlegen der Summenspannung (D) an das Quantisiermittel (23) und ein Rückkopplungsmittel (26) zum Bewirken einer negativen Rückkopplung vom Ausgang des Quantisierers (23) zum Eingang der ersten Integrationsstufe (21-1) umfaßt.
  6. System nach Anspruch 4 oder 5, dadurch gekennzeichnet, daß das Fehlersignal (e) die Ausgangsspannung (Dn) der letzten Integrationsstufe (21-n) des ersten Modulators (SD1) ist.
  7. System nach Anspruch 4, 5 oder 6, dadurch gekennzeichnet, daß der erste Modulator (SD1) zum Liefern des Fehlersignals (e) ein zweites Skaliermittel (29) zum Skalieren des Ausgangssignals (D') des Quantisierers (23) und ein Subtrahiermittel (27) zum Subtrahieren des Ausgangssignals des zweiten Skaliermittels (29) von der Ausgangsspannung (Dn) der letzten Integrationsstufe (21-n) des ersten Modulatormittels umfaßt.
  8. System nach einem der Ansprüche 4 bis 7, dadurch gekennzeichnet, daß der zweite Modulator (SD2) eine negative Rückkopplung vom Ausgang mindestens einer Integrationsstufe (31-n) zum Eingang der vorhergehenden Integrationsstufe umfaßt und daß mindestens die rückgekoppelte Integrationsstufe oder die dieser vorausgehende Integrationsstufe verzögert ist.
  9. System nach einem der Ansprüche 4 bis 8, dadurch gekennzeichnet, daß sie ein drittes Skaliermittel (28, 38) zum Skalieren des Fehlersignals (e) um einen ersten Skalierkoeffizienten kleiner als einer vor dem zweiten Modulatormittel (SD2) und ein viertes Skaliermittel (4) zum Skalieren des quantisierten Fehlersignals (e', e") um einen zweiten, dem Kehrwert des ersten Koeffizienten im wesentlichen gleichen Skalierkoeffizienten vor der Subtraktion des Fehlersignals von dem quantisierten Hauptsignal (D") umfaßt.
EP93914539A 1992-01-28 1993-01-28 Verfahren zur kaskadierung von sigma-delta modulatoren und ein sigma-delta modulatorsystem Expired - Lifetime EP0624290B1 (de)

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FI920378 1992-01-28
FI920378A FI90296C (fi) 1992-01-28 1992-01-28 Menetelmä sigma-delta-modulaattorien kytkemiseksi kaskadiin ja sigma-delta-modulaattorijärjestelmä
PCT/FI1993/000027 WO1993015557A1 (en) 1992-01-28 1993-01-28 Method for cascading sigma-delta modulators and a sigma-delta modulator system

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EP0624290A1 EP0624290A1 (de) 1994-11-17
EP0624290B1 true EP0624290B1 (de) 1997-10-29

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US (1) US5629701A (de)
EP (1) EP0624290B1 (de)
JP (1) JP3113277B2 (de)
KR (1) KR100343757B1 (de)
AT (1) ATE159840T1 (de)
DE (1) DE69314939T2 (de)
FI (1) FI90296C (de)
WO (1) WO1993015557A1 (de)

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US6348888B1 (en) * 1999-03-22 2002-02-19 Texas Instruments Incorporated Pipelined ADC with noise-shaped interstage gain error
EP1177634B1 (de) 1999-05-05 2004-09-29 Infineon Technologies AG Sigma-delta-analog/digital-wandleranordnung
US6408031B1 (en) * 1999-10-27 2002-06-18 Agere Systems Guardian Corp. Single bit Sigma Delta filter with input gain
EP1161044B1 (de) * 2000-05-30 2006-11-15 Matsushita Electric Industrial Co., Ltd. Quadraturmodulator
JP3795338B2 (ja) * 2001-02-27 2006-07-12 旭化成マイクロシステム株式会社 全差動型サンプリング回路及びデルタシグマ型変調器
JP2002353815A (ja) * 2001-05-23 2002-12-06 Pioneer Electronic Corp デルタシグマ型ａｄ変換器
DE10205680B4 (de) * 2002-02-12 2010-06-02 Infineon Technologies Ag Ein-Punkt-Modulator mit PLL-Schaltung
US6788232B1 (en) * 2003-01-14 2004-09-07 Berkana Wireless, Inc. Sigma delta modulator
JP4141865B2 (ja) * 2003-03-11 2008-08-27 株式会社ルネサステクノロジ モジュレータ
JP3830924B2 (ja) * 2003-07-04 2006-10-11 松下電器産業株式会社 縦続型デルタシグマ変調器
US7034728B2 (en) * 2004-08-11 2006-04-25 Raytheon Company Bandpass delta-sigma modulator with distributed feedforward paths
TWI517596B (zh) * 2013-07-18 2016-01-11 瑞昱半導體股份有限公司 前饋式三角積分調變器
US10128875B1 (en) 2018-03-30 2018-11-13 Mitsubishi Electric Research Laboratories, Inc. Methods and system of a digital transmitter with reduced quantization noise

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JPH01204528A (ja) * 1988-02-10 1989-08-17 Fujitsu Ltd Ａ／ｄ変換器
US4862169A (en) * 1988-03-25 1989-08-29 Motorola, Inc. Oversampled A/D converter using filtered, cascaded noise shaping modulators
US5055846A (en) * 1988-10-13 1991-10-08 Crystal Semiconductor Corporation Method for tone avoidance in delta-sigma converters
FI80548C (fi) * 1988-11-09 1990-06-11 Nokia Oy Ab Foerfarande foer kaskadkoppling av tvao eller flera sigma-deltamodulatorer samt ett sigma-delta-modulatorsystem.
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US5442354A (en) * 1993-08-26 1995-08-15 Advanced Micro Devices, Inc. Fourth-order cascaded sigma-delta modulator

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JPH07503346A (ja) 1995-04-06
KR950700640A (ko) 1995-01-16
FI920378A (fi) 1993-07-29
FI90296B (fi) 1993-09-30
ATE159840T1 (de) 1997-11-15
EP0624290A1 (de) 1994-11-17
JP3113277B2 (ja) 2000-11-27
DE69314939D1 (de) 1997-12-04
DE69314939T2 (de) 1998-03-05
WO1993015557A1 (en) 1993-08-05
US5629701A (en) 1997-05-13
KR100343757B1 (ko) 2002-11-23
FI920378A0 (fi) 1992-01-28
FI90296C (fi) 1994-01-10

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