EP0603226B1 - Verfahren und vorrichtung zur ansteuerung von matrixdisplays - Google Patents

Verfahren und vorrichtung zur ansteuerung von matrixdisplays Download PDF

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Publication number
EP0603226B1
EP0603226B1 EP92918425A EP92918425A EP0603226B1 EP 0603226 B1 EP0603226 B1 EP 0603226B1 EP 92918425 A EP92918425 A EP 92918425A EP 92918425 A EP92918425 A EP 92918425A EP 0603226 B1 EP0603226 B1 EP 0603226B1
Authority
EP
European Patent Office
Prior art keywords
lines
image
matrix display
line
displayed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP92918425A
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German (de)
English (en)
French (fr)
Other versions
EP0603226A1 (de
Inventor
Gangolf Hirtz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Deutsche Thomson Brandt GmbH
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Deutsche Thomson Brandt GmbH
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Application filed by Deutsche Thomson Brandt GmbH filed Critical Deutsche Thomson Brandt GmbH
Publication of EP0603226A1 publication Critical patent/EP0603226A1/de
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers

Definitions

  • the present invention relates to a method for controlling a matrix display according to the preamble of the main claim and a device suitable for carrying out the method according to the preamble of the first subject claim.
  • matrix displays also called matrix displays
  • LCD display liquid crystal display
  • plasma display plasma display
  • Matrix displays consist of an arrangement of M * N pixels, so-called pixels. M is the number of these pixels per line and N is the number of lines.
  • the control of the pixels is usually done line by line, i.e.
  • An analog video signal which contains the information of a picture line, is first scanned M times. It is also conceivable that the M samples from previous signal processing are already available.
  • the sample values are converted in series / in parallel, so that all M sample values are simultaneously available for driving a display line.
  • the corresponding display line is addressed, which means that the sample values available in parallel can be transferred to the corresponding display line.
  • T Za is the time duration of the video signal to be displayed within one line.
  • the aforementioned document GB-A-2 179 185 presents an interface in which a period of time for carrying out signal processing algorithms for driving a matrix display is extended into periods in which a video signal transmitted by a transmitter or a storage medium does not contain any image information.
  • the image data of a transmitted video signal are written into a memory with a first high clock frequency and the image data for controlling the matrix display are read out with a second clock frequency that is lower than the first clock frequency.
  • the known interface does not allow the number of lines to be added to be increased compared to the number of lines transmitted.
  • the invention is based on the following knowledge.
  • the electron beam To drive cathode ray tubes, such as are used in conventional image display devices, such as television sets, monitors and the like, the electron beam must be returned to the beginning of the next image line after writing each image line. This return takes a certain amount of time. A horizontal blanking period is therefore provided within each line in which there is no active video signal from which the image to be displayed is derived.
  • the electron beam when driving a cathode ray tube after writing the last line of each image, the electron beam must be returned to the beginning of the first line.
  • the duration required for this is referred to as the vertical blanking period and is taken into account in the video signal to be processed by invisible return lines.
  • the invention has the advantage that the increase in the number of controlled lines leads to a reduction in the visible line structure.
  • the image to be displayed can be expanded to 560 lines.
  • FIG. 1 symbolically shows the course of a video image line 10 known per se, which is composed of an active part 11 and a non-active part 12.
  • the total duration of line 10 is Tz, of which the active part 11 takes the duration Tza.
  • FIG. 2 shows the temporal structure of a video picture or field when using interlaced signals. This consists of a total number Z of rows, of which Za are active, i.e. Image information included.
  • Each of these lines has a course as symbolically shown in Fig. 1.
  • the time duration of each of the lines mentioned is Tz. If only those lines that receive image information are considered, their number is Za and the duration for the transmission of the active lines is Tba.
  • the lines indicated in FIG. 2 can also have a course other than that shown in FIG. 1. It is only essential that, in addition to an active part, a non-active part is provided which, depending on the respective television standard, can contain synchronization pulses such as "sync", "burst”, etc.
  • FIG. 3 A device according to a first embodiment is shown in FIG. 3.
  • An image source 13 which processes a signal transmitted by a recording medium or a transmitter and has, for example, a receiver, a color decoder and an analog / digital converter, outputs a video signal line by line to the data input of a line memory 14. This has a first control input 15 and a second control input 16.
  • a first line control signal S1 is present at the first control input 15, by means of which the storage (writing) of video line data is controlled.
  • a second line control signal S2 is present at the second control input 16, by means of which the reading out of video line data is controlled.
  • the signal read out from the line memory 14 is output to a signal processing device 17.
  • the signal processed by the signal processing device 17 reaches a line-serial / parallel converter 18, the output signal of which drives a matrix display 19 line by line.
  • the time periods shown in hatched lines in FIG. 2 can additionally be used for the control of a matrix display for the execution of signal processing algorithms and for the control of the Matrix displays 19.
  • the time that is additionally available for image processing algorithms can be increased by a factor k1 less than or equal to 1.23 be expanded.
  • the number M 'of pixels to be displayed per line in this exemplary embodiment is identical to the number M of pixels per line determined by the geometry of the matrix display.
  • ft ′ ft / k1.
  • ie Tza * Tza * k1
  • the clock frequency required for the stages 17, 18 for driving the matrix display 19 thus becomes lower given the same number Za of lines to be displayed.
  • FIG. 4 The device of a second embodiment is shown in FIG. 4. Means that perform the same function As in the first exemplary embodiment in FIG. 3, the same characteristic numbers are used as there and they are only dealt with to the extent necessary for understanding.
  • the image source 13 outputs its output signal to an image memory 20 which has a first control input 21 and a second control input 22.
  • first control input 21 At the first control input 21 is a first image control signal S1 ', which controls the storage (writing) of video image data.
  • second control input 22 At the second control input 22 there is a second image control signal S2 'which controls the reading out of video image data.
  • the versions of the control signals S1 ', S2' can be used to implement different versions.
  • the time available for signal processing is increased by up to 33%, which is a factor k2 less than or equal to 1.33 corresponds.
  • the reading of the image data takes place, controlled by the second image control signal S2 ', now extended into the vertical blanking period.
  • the time available for displaying Za lines is designated Tba '.
  • the total available line duration is Tza + Tza ′ ⁇ Tz ′ - Ti
  • the reduced clock frequency ft ' is an integer multiple of the reduced line frequency fz'.
  • FIG. 5 An image structure according to the second exemplary embodiment is shown in FIG. 5.
  • time Tb (corresponds to the total framed area of hatched and non-hatched area) is the same in FIGS. 2 and 5.
  • the first image control signal S1 'with the clock frequency ft and the second image control signal S2' is modulated with the reduced clock frequency ft+.
  • FIG. 6 symbolically shows storage and reading processes for the image memory 20 of FIG. 4.
  • the storage takes place at a higher frequency than the reading.
  • image information is only present within an active image duration and is stored in this duration.
  • the active image duration is to be understood as the time corresponding to the non-hatched area in FIG. 2.
  • the reading out takes place during a period of time that can essentially correspond to almost the entire image duration Tb, particularly taking into account the initialization time Ti.
  • the required size of the image memory depends on the area in which the image is enlarged in the vertical direction. That is the area Tb - Tba.
  • Another exemplary embodiment provides that the clock frequency ft is not reduced to the extent that was described in the previous exemplary embodiments. Instead, however, the video information stored in the image memory 20 is to be displayed over a larger number of lines compared to the number Za of lines which contain image information, which corresponds to a vertical upward interpolation of the number of lines Za.
  • an active video image that contains image information can be read into and read out of the memory 20 at the same clock frequency.
  • the periods for beam return are additionally available for processing by stages 23, 24 and for display by the matrix display 19. These time periods can now be used to control more lines of the matrix display than is provided by the relevant television standard, which leads to a reduction in the visible line structure.
  • the image to be displayed can be stretched, for example, in its horizontal dimensions. Parts that thereby go beyond the horizontal dimensions of the matrix display 19 can be trimmed.
  • the image to be displayed can be expanded to 560 lines.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Transforming Electric Information Into Light Information (AREA)
  • Liquid Crystal (AREA)
EP92918425A 1991-09-05 1992-08-26 Verfahren und vorrichtung zur ansteuerung von matrixdisplays Expired - Lifetime EP0603226B1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE4129459A DE4129459A1 (de) 1991-09-05 1991-09-05 Verfahren und vorrichtung zur ansteuerung von matrixdisplays
DE4129459 1991-09-05
PCT/EP1992/001954 WO1993005497A1 (de) 1991-09-05 1992-08-26 Verfahren und vorrichtung zur ansteuerung von matrixdisplays

Publications (2)

Publication Number Publication Date
EP0603226A1 EP0603226A1 (de) 1994-06-29
EP0603226B1 true EP0603226B1 (de) 1995-11-29

Family

ID=6439869

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Application Number Title Priority Date Filing Date
EP92918425A Expired - Lifetime EP0603226B1 (de) 1991-09-05 1992-08-26 Verfahren und vorrichtung zur ansteuerung von matrixdisplays

Country Status (10)

Country Link
US (1) US6121941A (xx)
EP (1) EP0603226B1 (xx)
JP (4) JPH07501626A (xx)
KR (1) KR100256841B1 (xx)
CN (1) CN1030806C (xx)
DE (2) DE4129459A1 (xx)
ES (1) ES2082497T3 (xx)
HK (1) HK113296A (xx)
MY (1) MY111957A (xx)
WO (1) WO1993005497A1 (xx)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4093380B2 (ja) * 1996-04-17 2008-06-04 三星電子株式会社 表示モードの変換機能を有する液晶表示装置
KR100205009B1 (ko) 1996-04-17 1999-06-15 윤종용 비디오신호 변환장치 및 그 장치를 구비한 표시장치
AU2003267775A1 (en) * 2002-11-08 2004-06-07 Koninklijke Philips Electronics N.V. Circuit for driving a display panel
JP4152934B2 (ja) * 2003-11-25 2008-09-17 シャープ株式会社 表示装置及びその駆動方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60227296A (ja) * 1984-04-25 1985-11-12 シャープ株式会社 表示制御方式
JPS60257497A (ja) * 1984-06-01 1985-12-19 シャープ株式会社 液晶表示装置の駆動方法
JPS60257683A (ja) * 1984-06-01 1985-12-19 Sharp Corp 液晶表示装置の駆動回路
JPH084340B2 (ja) * 1985-08-07 1996-01-17 セイコーエプソン株式会社 インタ−フエイス装置
JPS62218943A (ja) * 1986-03-19 1987-09-26 Sharp Corp 液晶表示装置
JPH0782306B2 (ja) * 1986-05-30 1995-09-06 株式会社日立製作所 ビデオインターフェース方法及び装置
GB8728434D0 (en) * 1987-12-04 1988-01-13 Emi Plc Thorn Display device
JP2508673B2 (ja) * 1986-12-17 1996-06-19 ソニー株式会社 表示装置
DE3720353A1 (de) * 1987-06-19 1989-01-05 Online Tech Datenuebertragungs Verfahren und schaltungsanordnung zur ansteuerung einer bildwiedergabeeinrichtung
EP0295690B1 (en) * 1987-06-19 1994-11-30 Kabushiki Kaisha Toshiba Display area control system for plasma display apparatus
JP2892010B2 (ja) * 1988-05-28 1999-05-17 株式会社東芝 表示制御方式
DE69027136T2 (de) * 1989-02-10 1996-10-24 Sharp Kk Flüssigkristallanzeigeeinheit und Steuerverfahren dafür
JP2531534B2 (ja) * 1989-05-26 1996-09-04 三菱電機株式会社 表示装置
JP2578984B2 (ja) * 1989-07-06 1997-02-05 松下電器産業株式会社 映像信号変換回路
JP2906462B2 (ja) * 1989-07-18 1999-06-21 ソニー株式会社 テレビジョン受信機
JPH0362090A (ja) * 1989-07-31 1991-03-18 Toshiba Corp フラットパネル表示制御回路
CA2041819C (en) * 1990-05-07 1995-06-27 Hiroki Zenda Color lcd display control system
GB9015986D0 (en) * 1990-07-20 1990-09-05 Philips Electronic Associated Image display
DE69212076T2 (de) * 1991-07-19 1997-01-30 Philips Electronics Nv Mehrnormwiedergabeanordnung

Also Published As

Publication number Publication date
JP3853819B2 (ja) 2006-12-06
JPH07501626A (ja) 1995-02-16
ES2082497T3 (es) 1996-03-16
MY111957A (en) 2001-03-31
DE4129459A1 (de) 1993-03-11
CN1030806C (zh) 1996-01-24
HK113296A (en) 1996-07-05
EP0603226A1 (de) 1994-06-29
JP2005165346A (ja) 2005-06-23
WO1993005497A1 (de) 1993-03-18
DE59204522D1 (de) 1996-01-11
CN1070276A (zh) 1993-03-24
JP3727631B2 (ja) 2005-12-14
JP2004046176A (ja) 2004-02-12
JP2006301667A (ja) 2006-11-02
KR100256841B1 (ko) 2000-05-15
US6121941A (en) 2000-09-19

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