EP0424254B1 - Résistance électrique sous forme de puce à montage de surface et son procédé de fabrication - Google Patents

Résistance électrique sous forme de puce à montage de surface et son procédé de fabrication Download PDF

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Publication number
EP0424254B1
EP0424254B1 EP90402915A EP90402915A EP0424254B1 EP 0424254 B1 EP0424254 B1 EP 0424254B1 EP 90402915 A EP90402915 A EP 90402915A EP 90402915 A EP90402915 A EP 90402915A EP 0424254 B1 EP0424254 B1 EP 0424254B1
Authority
EP
European Patent Office
Prior art keywords
layer
substrate
resistive
foil
alloy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP90402915A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP0424254A1 (fr
Inventor
Claude Flassayer
Franklin Collins
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SFERNICE FRANCAISE DE L'ELECTRO-RESISTANCE Ste
Original Assignee
SFERNICE FRANCAISE DE L'ELECTRO-RESISTANCE Ste
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SFERNICE FRANCAISE DE L'ELECTRO-RESISTANCE Ste filed Critical SFERNICE FRANCAISE DE L'ELECTRO-RESISTANCE Ste
Priority to AT90402915T priority Critical patent/ATE99828T1/de
Publication of EP0424254A1 publication Critical patent/EP0424254A1/fr
Application granted granted Critical
Publication of EP0424254B1 publication Critical patent/EP0424254B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/06—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material including means to minimise changes in resistance with changes in temperature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
    • H01C17/28—Apparatus or processes specially adapted for manufacturing resistors adapted for applying terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C1/00—Details
    • H01C1/14—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors
    • H01C1/142—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors the terminals or tapping points being coated on the resistive element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
    • H01C17/006—Apparatus or processes specially adapted for manufacturing resistors adapted for manufacturing resistor chips

Definitions

  • the invention relates to an electrical resistance in the form of a wireless chip, adapted so as to be able to be soldered in particular on a printed circuit board or on a hybrid circuit substrate.
  • a resistance is part of the family of new components for electronics, generally known by the specific term of surface mount components.
  • the invention also relates to the method for the manufacture of this electrical resistance.
  • resistors in the form of a chip so as to form a resistive element or resistive layer deposited on an electrically insulating substrate in the form of a square or rectangle, of a few mm 2 of surface.
  • This resistive element is deposited by screen printing using resistive pastes or inks deposited directly on said substrate.
  • the thickness of the deposited layer is of the order of several micrometers, and its electrical resistance varies between a few ohms and several megohms. This technique is known to those skilled in the art under the specific term of deposition in thick layers.
  • the same type of component by depositing, by vacuum deposition techniques, resistive materials, in particular of the Nickel-Chromium or Constantan type, directly onto said substrate.
  • resistive materials in particular of the Nickel-Chromium or Constantan type
  • the ohmic value of the component thus produced can vary between a few ohms and a few tens of kilo-ohms, the thickness of the deposit typically varying between 10 and a few thousand nanometers.
  • This technique is known by the specific term of vacuum deposition.
  • the end electrodes of these known resistors are produced according to deposition techniques in thick layers, in particular by depositing Ag-Pd alloys on the substrate, produced so as to form an electrical continuity with the resistive material and then recharging by electrolytic deposition techniques said Ag-Pd alloy by thick layers of Nickel, Sn and Pb-Sn.
  • Each of the bar-shaped sections is then cut into units of a few mm2 and to complete an electrolyte deposit of Ni and Pb-Sn or equivalent is applied to each of said chips. A resistance is thus obtained in the form of a surface mount chip.
  • the resistors manufactured by these known methods have the disadvantage, however, because of their nature of being imprecise and of having temperature variation and frequency response characteristics detrimental to the performance demanded by current electronic circuits.
  • the ohmic value tolerances of these resistors are hardly less than a few percent of the nominal value of the resistance.
  • their temperature coefficient represented by the variation in nominal resistance as a function of temperature, is never less than 100 to 200 parts per million / ° C (ppm / ° C).
  • variations in the nominal resistance as a function of time can be comprised in a few thousand and several thousand parts per million (ppm).
  • the object of the present invention is to overcome these drawbacks by providing a surface-mount chip resistor whose tolerance of the ohmic value relative to the nominal value is at least of the order of 0.1% to 0.05 %.
  • Another object of the present invention is to provide a chip resistor whose temperature coefficient is less than 5 ppm / ° C.
  • Another object of the present invention is to provide a chip resistor whose variation in nominal resistance over time is confined in the range of 50 to 200 ppm for a period of between 2,000 h and 10,000 h at 155 ° C. .
  • Another object of the present invention is to provide a chip resistance enjoying the advantages described above while retaining the solderability and reliability properties generally associated with so-called very high precision components.
  • Another object of the present invention is to provide a method which makes it possible to manufacture a chip resistor which has the characteristics defined above.
  • the invention thus relates to an electrical resistance in the form of a chip, intended to be soldered in particular on a printed circuit board or on a hybrid circuit substrate, comprising an electrically insulating substrate of the ceramic type, on which is bonded by an adhesive layer of organic resin a sheet of metal or resistive alloy, this sheet being cut by etching so as to form filaments connected together to form a sinuous resistive circuit, this cut resistive sheet being covered by another layer of organic resin.
  • this resistance is characterized in that said other layer of resin leaves free, in the vicinity of two opposite edges of the substrate, two end parts of the cut resistive sheet, in that these two parts of the resistive sheet are each covered by a thin layer of a metal or alloy adhering to the resistive sheet, this layer being covered by a second thicker layer of metal or conductive alloy, and this second layer being covered by a third layer also thicker of a weldable alloy, these three superimposed layers also extending on the two opposite lateral faces of the substrate corresponding to said opposite edges and partially on the face of the substrate opposite to the cut resistive sheet.
  • the invention thus makes it possible to produce a chip-shaped resistor with surface mounting, comprising as a resistive element an etched metal sheet instead of a resistive layer obtained according to the technique of thick or thin layers.
  • said end parts of the cut resistive sheet do not extend to the two opposite lateral faces of the substrate but leave free two opposite zones of the substrate adjacent to said lateral faces of the latter, so that said three metal layers successively cover on each side of the resistor, a part of the cut resistive sheet, then an area of the substrate not covered by said resistive sheet and devoid of resin, then successively the lateral face of the substrate and a part of the surface of the substrate opposite to that carrying the resistive sheet.
  • a resin 2 for example of the epoxy or polyimide type, or any other type of glue capable of withstanding thermal and mechanical stresses
  • a sheet 3 d alloy of nickel and chromium of thickness between 2 and 10 micrometers on an insulating substrate 1 (for example of ceramic of the aluminum oxide, beryllium oxide or aluminum nitride type or any other ceramic having good dielectric properties at any temperature as well as excellent hardness and mechanical rupture properties), of thickness between 0.2 and 0.6 mm and of surface on the order of 0.5 to a few square millimeters.
  • a photoresist mask is applied to the sheet 3 comprising openings drawing a resistance pattern similar to those described in the cited patents upper.
  • the assembly is subjected to chemical, electrochemical or ionic machining, as described for example in American patents 3,517,436 and 3,405,381 (ZANDMAN) in French patents 2,344,940 and 2,354,617 of the Applicant, to engrave the areas of the resistive sheet 3 not protected by the photoresist.
  • chemical, electrochemical or ionic machining as described for example in American patents 3,517,436 and 3,405,381 (ZANDMAN) in French patents 2,344,940 and 2,354,617 of the Applicant, to engrave the areas of the resistive sheet 3 not protected by the photoresist.
  • the substrate 1 sheet 2 assembly is in the form shown in FIG. 2, in which the reference 4 schematically represents the resistance in the form of an engraved filament folded in Greek form at the ends of which are formed in the same step of photogravure of the output pads 5, intended to connect the resistor to the outside, the assembly adhering tightly to the substrate 1 by the resin layer 2.
  • the etching mask has been studied so that the lateral dimension d of the resistive element 3, 4, 5, is substantially smaller than the width D of the substrate 1 and is between 0.8 D and 0.6 D. Thus, there remains on each side of the end portions 5 of the engraved sheet 3 of the free zones.
  • the lateral dimension of this protective surface is substantially smaller than d, so as to leave free most of the contact pads 5.
  • This resin layer 6 is applied by screen printing or other process.
  • parts 6 and 5 are protected by a thick layer of photoresist with a thickness of the order of 5 to 10 micrometers, so as to leave exposed the lateral parts 7 of the resistor, covered by layer 2 bonding resin.
  • the portion of the resin layer 2 not protected by the photoresist is then removed by etching.
  • One of the preferred means of the invention is to subject the entire resistance to a plasma consisting of a mixture of oxygen and fluorinated gaseous compounds of the carbon fluoride type.
  • the plasma etching speed being substantially equal for the photoresist and the resin 2, the result of this operation, represented by FIG. 4, is to leave bare and perfectly free from any trace of resin, the parts adjacent to the two opposite edges of substrate 1.
  • the sixth step of the method consists in depositing by vacuum deposition a thin contact layer 8 on the output pads 5 of the resistive sheet 3 and on the lateral surfaces 7 of the substrate 1.
  • One of the preferred means of the invention is to deposit, by sputtering, on said areas and surfaces 5 and 7, first a layer of chromium 8, of thickness between 10 and 50 nanometers, followed by a deposit 9 of nickel alloy -Chrome, with a concentration between 20% and 50% in chromium atom, and with a thickness between 500 and 1500 nanometers.
  • the purpose of the deposition 8 is to produce, between the sheet 3 and the layer 9, an interface capable of achieving excellent ohmic contact combined with suitable adhesion forces between the sheet 3 and the layer 9.
  • a third layer of nickel or 'Or 14 is then deposited.
  • One of the preferred means of the invention is to use to make said deposit the appropriate electrolytic techniques for depositing metals and alloys.
  • Another preferred means of the invention is to deposit in place of the layer of Chromium 8, an alloy of the Titanium-Tungsten type, which allows better mechanical attachment to the sheet 3 than pure Chromium.
  • This layer also covers the parts 7 while ensuring as smooth a transition as possible between the output pads 5 and said parts 7. This makes it possible to reduce as much as possible the stresses of mechanical origin as well as the stresses of thermal origin which may develop at the level of said areas 5 due to the differences in expansion coefficient between 1.2 and 3 respectively. This optimization ensures that the value of the chip resistance will be practically constant over time and under temperature variations during its operation. This phenomenon is further accentuated by the use of sputtering means, which have the property of increasing the adhesion forces of the thin films deposited on the output pads 5 and the substrate 1.
  • metal masks 10 and 11 Prior to the deposition operations, metal masks 10 and 11 were placed, by appropriate mechanical means, on the faces 12 and 13 of the resistor in order to protect them from all traces of Chromium, Nickel-Chromium and Nickel or from Au.
  • the deposition is carried out so as to cover a uniform thickness all the surfaces of the sheet 2 and substrate 1 assembly, protected or not protected by the metal masks 10 and 11.
  • the masks metal 10 and 11 are removed. This operation mechanically removes the thin layers that have settled on these masks. The result of this operation is shown in FIG. 6.
  • the deposition layers 8, 9 and 14 therefore produce an ohmic contact in the form of an elongated C electrically binding the sheet resistance 3, via the output pads 5, to the lower surface 13 of the substrate 1.
  • the material constituting the layer 14 is produced by electroytic deposition of gold.
  • the layer 14 is produced by electrolytic deposition of nickel. This is then covered, by appropriate means of soaking in a tin-lead bath, with a layer of tin-lead with a thickness of between 5 and 20 micrometers.
  • the parts 5a of the etched resistive sheet 3 extend practically to the opposite lateral edges of the substrate 1.
  • the parts 5a of the etched resistive sheet 3 are covered by three metallic layers 8, 9, 14 identical to those represented in FIG. 6, which extend on the lateral faces of the substrate and on a part of the face 13 of the latter opposite to the face carrying the etched resistive sheet 3.
  • these three metallic layers form a conductive coating of C-shaped section extending over the entire length of component on its two opposite sides.
  • the chip resistance thus obtained also has superior performance to that of the resistors produced using the thick or thin layer techniques, thanks to the high precision with which the resistive element 3 can be obtained in the form of a cut or engraved sheet.
  • the superiority of the resistance shown in FIG. 6 is essentially explained by the presence of free zones 7 comprised between the edges of the parts 5 of the resistive sheet 3 and the adjacent edges of the substrate 1 which, as explained above, make it possible to reduce the thermal and mechanical stresses generated on the parts 5 of the etched resistive sheet 3 due to the differences in expansion coefficient between the substrate 1, the resin layer 2 and the resistive sheet 3.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Non-Adjustable Resistors (AREA)
  • Thermistors And Varistors (AREA)
  • Inorganic Insulating Materials (AREA)
  • Glass Compositions (AREA)
  • Details Of Resistors (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
EP90402915A 1989-10-20 1990-10-17 Résistance électrique sous forme de puce à montage de surface et son procédé de fabrication Expired - Lifetime EP0424254B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT90402915T ATE99828T1 (de) 1989-10-20 1990-10-17 Elektrischer widerstand in chip-bauweise fuer oberflaechenbestueckung und verfahren zu seiner herstellung.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8913759A FR2653588B1 (fr) 1989-10-20 1989-10-20 Resistance electrique sous forme de puce a montage de surface et son procede de fabrication.
FR8913759 1989-10-20

Publications (2)

Publication Number Publication Date
EP0424254A1 EP0424254A1 (fr) 1991-04-24
EP0424254B1 true EP0424254B1 (fr) 1994-01-05

Family

ID=9386613

Family Applications (1)

Application Number Title Priority Date Filing Date
EP90402915A Expired - Lifetime EP0424254B1 (fr) 1989-10-20 1990-10-17 Résistance électrique sous forme de puce à montage de surface et son procédé de fabrication

Country Status (10)

Country Link
US (1) US5111179A (pt)
EP (1) EP0424254B1 (pt)
JP (1) JPH03165501A (pt)
KR (1) KR910008749A (pt)
AT (1) ATE99828T1 (pt)
BR (1) BR9005297A (pt)
CA (1) CA2028043C (pt)
DE (1) DE69005785T2 (pt)
FR (1) FR2653588B1 (pt)
MC (1) MC2169A1 (pt)

Families Citing this family (30)

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US5179366A (en) * 1991-06-24 1993-01-12 Motorola, Inc. End terminated high power chip resistor assembly
US5189387A (en) * 1991-07-11 1993-02-23 Electromer Corporation Surface mount device with foldback switching overvoltage protection feature
US5170146A (en) * 1991-08-01 1992-12-08 Motorola, Inc. Leadless resistor
US5287083A (en) * 1992-03-30 1994-02-15 Dale Electronics, Inc. Bulk metal chip resistor
US5323138A (en) * 1992-09-04 1994-06-21 Trw Inc. Reliable thin film resistors for integrated circuit applications
US5464966A (en) * 1992-10-26 1995-11-07 The United States Of America As Represented By The Secretary Of Commerce Micro-hotplate devices and methods for their fabrication
DE4339551C1 (de) * 1993-11-19 1994-10-13 Heusler Isabellenhuette Widerstand in SMD-Bauweise und Verfahren zu seiner Herstellung sowie Leiterplatte mit solchem Widerstand
JPH10508430A (ja) * 1994-06-09 1998-08-18 チップスケール・インコーポレーテッド 抵抗器の製造
US5566011A (en) * 1994-12-08 1996-10-15 Luncent Technologies Inc. Antiflector black matrix having successively a chromium oxide layer, a molybdenum layer and a second chromium oxide layer
EP0810614B1 (en) * 1996-05-29 2002-09-04 Matsushita Electric Industrial Co., Ltd. A surface mountable resistor
TW405129B (en) * 1997-12-19 2000-09-11 Koninkl Philips Electronics Nv Thin-film component
JP3826749B2 (ja) * 2001-08-22 2006-09-27 株式会社日立製作所 シャント抵抗を備えた電力変換装置
AU2002324848A1 (en) * 2002-09-03 2004-03-29 Vishay Intertechnology, Inc. Flip chip resistor and its manufacturing method
US20040201447A1 (en) * 2003-04-14 2004-10-14 Wong Marvin Glenn Thin-film resistor device
EP1950771A1 (en) * 2005-10-13 2008-07-30 Rohm Co., Ltd. Chip resistor and its manufacturing method
US8208266B2 (en) * 2007-05-29 2012-06-26 Avx Corporation Shaped integrated passives
TWI503849B (zh) * 2009-09-08 2015-10-11 Cyntec Co Ltd 微電阻元件
WO2012157435A1 (ja) 2011-05-17 2012-11-22 ローム株式会社 チップ抵抗器、チップ抵抗器の製造方法、およびチップ抵抗器の実装構造
JP6107062B2 (ja) * 2012-11-06 2017-04-05 Tdk株式会社 チップサーミスタ
JP2014165194A (ja) * 2013-02-21 2014-09-08 Rohm Co Ltd チップ抵抗器、およびチップ抵抗器の製造方法
JP6227877B2 (ja) * 2013-02-26 2017-11-08 ローム株式会社 チップ抵抗器、およびチップ抵抗器の製造方法
CN105655072A (zh) * 2014-11-11 2016-06-08 南京化工职业技术学院 一种光控热敏电阻器
TWI616903B (zh) * 2015-07-17 2018-03-01 乾坤科技股份有限公司 微電阻器
US10083781B2 (en) 2015-10-30 2018-09-25 Vishay Dale Electronics, Llc Surface mount resistors and methods of manufacturing same
US10839989B2 (en) * 2016-09-27 2020-11-17 Panasonic Intellectual Property Management Co., Ltd. Chip resistor
JP2017163165A (ja) * 2017-06-21 2017-09-14 ローム株式会社 チップ抵抗器、およびチップ抵抗器の製造方法
US10438729B2 (en) 2017-11-10 2019-10-08 Vishay Dale Electronics, Llc Resistor with upper surface heat dissipation
DE202018004354U1 (de) * 2018-09-19 2018-10-15 Heraeus Sensor Technology Gmbh Widerstandsbauelement zur Oberflächenmontage auf einer Leiterplatte und Leiterplatte mit zumindest einem darauf angeordneten Widerstandsbauelement
JP6732996B2 (ja) * 2019-04-15 2020-07-29 ローム株式会社 チップ抵抗器
KR102300015B1 (ko) * 2019-12-12 2021-09-09 삼성전기주식회사 저항 부품

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US3517436A (en) * 1965-05-04 1970-06-30 Vishay Intertechnology Inc Precision resistor of great stability
US3496513A (en) * 1967-11-17 1970-02-17 Sprague Electric Co Film resistor with securely soldered leads
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JP2668375B2 (ja) * 1988-01-25 1997-10-27 ティーディーケイ株式会社 回路部品の電極製造方法
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NL8800853A (nl) * 1988-04-05 1989-11-01 Philips Nv Chipweerstand en werkwijze voor het vervaardigen van een chipweerstand.

Also Published As

Publication number Publication date
BR9005297A (pt) 1991-09-17
MC2169A1 (fr) 1992-04-09
KR910008749A (ko) 1991-05-31
JPH03165501A (ja) 1991-07-17
FR2653588A1 (fr) 1991-04-26
US5111179A (en) 1992-05-05
EP0424254A1 (fr) 1991-04-24
FR2653588B1 (fr) 1992-02-07
ATE99828T1 (de) 1994-01-15
DE69005785T2 (de) 1994-05-05
DE69005785D1 (de) 1994-02-17
CA2028043C (en) 1999-03-16
CA2028043A1 (en) 1991-04-21

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