EP0368572B1 - Steuereinrichtung und -verfahren für eine Flüssigkristallanzeigetafel - Google Patents

Steuereinrichtung und -verfahren für eine Flüssigkristallanzeigetafel Download PDF

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Publication number
EP0368572B1
EP0368572B1 EP89311397A EP89311397A EP0368572B1 EP 0368572 B1 EP0368572 B1 EP 0368572B1 EP 89311397 A EP89311397 A EP 89311397A EP 89311397 A EP89311397 A EP 89311397A EP 0368572 B1 EP0368572 B1 EP 0368572B1
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EP
European Patent Office
Prior art keywords
data
color
source lines
reading
memory
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Expired - Lifetime
Application number
EP89311397A
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English (en)
French (fr)
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EP0368572A3 (de
EP0368572A2 (de
Inventor
Tokutarou Kusada
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Sharp Corp
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Sharp Corp
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Priority claimed from JP63280029A external-priority patent/JPH02126285A/ja
Priority claimed from JP63326472A external-priority patent/JPH02170784A/ja
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of EP0368572A2 publication Critical patent/EP0368572A2/de
Publication of EP0368572A3 publication Critical patent/EP0368572A3/de
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Publication of EP0368572B1 publication Critical patent/EP0368572B1/de
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0224—Details of interlacing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0281—Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general

Definitions

  • the present invention relates generally to devices and methods for driving liquid crystal panels, and particularly to a device and a method for driving an active matrix display type color liquid crystal display panel by using a low speed clock signal. More particularly, the present invention relates to a structure of a liquid crystal panel drive line memory circuit and a drive method thereof for applying a color signal to a series of signal electrodes included in the liquid crystal panel according to a high speed line sequential system.
  • Display devices using liquid crystal can be driven with low voltage and consequently they are utilized for applications which require low consumption of power.
  • liquid crystal panels having a matrix arrangement of liquid crystal pixels and to be driven by successively applying a video signal to each liquid crystal pixel to display an image.
  • Figs. 1A to 1C show schematically a structure of a conventional active matrix display type color liquid crystal panel.
  • pixels P11, P12, ..., P 1(N-1) , P 1N , ..., P M(N-1) , P MN are arranged in a matrix of M rows and N columns on a panel (i.e., an active matrix display type color liquid crystal panel) 1 to form a display screen (hereinafter referred to as a screen) 2.
  • a thin film transistor, not shown, (hereinafter referred to as TFT) is provided in each pixel P in a one-to-one correspondence.
  • each pixel P comprises a TFT ⁇ Tr, a capacitor CA and a liquid crystal element LE.
  • the TFT ⁇ Tr has its gate connected to a scanning line (i.e., a gate line) lx and its source connected to a source line ly.
  • the capacitor CA accumulates signals transmitted from the source line ly through the TFT ⁇ Tr.
  • the liquid crystal element LE transmits or interrupts light in response to a signal potential from the source line ly or the capacitor CA.
  • a color filter is disposed on the liquid crystal element LE and a desired color display is obtained through the color filter dependent on the transmission/interruption state of the liquid crystal element LE.
  • the gates of the TFTs of the respective rows are connected to the corresponding scanning lines (gate lines) lx1, lx2, lx3, ... lxM.
  • a scanning driver 4 activates the scanning lines lx1 to lxM successively. Thus, the screen 2 is scanned in the vertical direction.
  • the sources of the TFTs of the respective columns are connected to the corresponding source lines ly1, ly2, ..., lyN.
  • a color signal is transmitted from a source driver 3 (shown in Fig. 1C) to each of the source lines ly1 to lyN.
  • a plurality of pixels P connected in common to one source line ly constitute a pixel row b1, r2, g3, b4, ..., r (N-1), gN (a pixel row being generically denoted by a reference character Y) in which an order of colors is preset from the left to the right of the screen 2.
  • the characters b, r, g represent pixels of colors corresponding to color video signals B (blue), R (red), G (green), and the numerals attached to those characters, 1, 2, 3 etc. represent the order of arrangement.
  • a scanning line is generally indicated by the reference characters lx and a source line is generally indicated by the reference characters ly.
  • the source driving circuit (hereinafter referred to as the source driver) 3 comprises: a shift register 3a including output terminals Q1 to Q N corresponding to the number N of source lines ly; an analog switch 3b including switching elements S1 to S N provided corresponding to the output terminals Q1 to Q N with a one-to-one relation; and an analog sample-and-hold circuit 3c.
  • the shift register 3a shifts the output in the direction from the output terminal Q1 to the output terminal Q N to turn on the switching elements S1 to S N successively one by one in the direction shown by the arrow y, whereby the color video signals B, R, G connected to the switching elements S1 to S N are applied successively to the analog sample-and-hold circuit 3c.
  • the analog sample-and-hold circuit 3c holds the color video signals B, R, G accepted in one horizontal period of the screen 2 and outputs those signals individually to the corresponding pixel rows Y through the source lines ly in the subsequent horizontal period and, at the same time, it accepts in parallel the color signals B, R, G for the subsequent horizontal period.
  • Fig. 2 is a block diagram showing an electric construction of a conventional liquid crystal drive circuit.
  • the liquid crystal drive circuit 21 comprises a plurality of source drivers 5 to 8 arranged in peripheral portions of the screen 2, and a plurality of line memory circuits 9 to 14 which supply color video signals R, G, B to the respective source drivers 5 to 8.
  • Each of the line memory circuits 9 to 14 includes an A/D converter, a memory, a multiplexer, a latch circuit, a D/A converter and the like, as described later.
  • the screen 2 is constructed according to a multiplex matrix system. More specifically, the source lines ly are connected alternately to the upper and lower source drivers 5, 7; 6, 8, and each pixel row Y is divided into two portions, in the horizontal direction, i.e., the first half portion (driven by the source drivers 5, 6) and the second half portion (driven by the source drivers 7, 8). As a result, the screen 2 is formed by four portions, i.e., the respective portions corresponding to the pixel rows Y1 to Y4.
  • the plurality of source drivers 5 to 8 are arranged around the screen corresponding to the divided pixel rows Y1 to Y4.
  • the color video signals R, G, B applied through the lines 11, 12, 13, respectively, are processed in six line memory circuits 9 to 14 by sequential operation such as analog-to-digital (A/D) conversion, writing, reading, latching and digital-to-analog (D/A) conversion. After that, the processed signals are supplied according to alternate signal strobe operation of the source drivers 5 to 8.
  • the circuit for each line memory is required to comprise, as shown in the block diagram in Fig. 3, an amplifying circuit 9a for the inputted color signal (e.g., B), an A/D converter 9b for digitally converting the inputted color signal, a buffer circuit 9c, a memory 9d for storing the digital data from the buffer circuit 9c, a write address generating circuit 9e and a read address generating circuit 9f for generating write/read addresses for the memory 9d, a multiplexer 9h for switching write/read operations of the memory 9d with prescribed timing and supplying the write address or the read address to the memory 9d, a latch circuit 9i for latching the data read from the memory 9d, a D/A converter 9j for converting the latched digital data to an analog signal, and a buffer 9k provided between the source driver and the D/A converter 9
  • the switching of the write/read operations of the memory 9d is carried out under the control of a line memory control circuit 9g through the address multiplexer.
  • the operation control (such as control of address generation timing) of the write address generating circuit 9e and the read address generating circuit 9f is carried out by the line memory control circuit 9g.
  • each of the source drivers 5 to 8 has the same structure as shown in Fig. 1C and successively receives and holds a color signal of one color in response to the clock signal CK.
  • each of the line memories 9 to 14 transmits signals to the two source drivers.
  • the signal from one line memory to the source driver (5 or 6) of the first half portion and that to the source driver (7 or 8) of the second half portion are alternately read and, on this occasion, the order of acceptance of the signals provided from the respective line memories 9 to 14 by the source drivers 5 to 8 need to be consistent with the color order of the pixel rows Y.
  • a delay circuit or the like is required for the output portion of each of the line memories 9 to 14. Accordingly, each of the source drivers 5 to 8 drives only 1/4 of the columns (160 columns in the figure) of the screen 2.
  • each of the line memories 9 to 14 can drive the liquid crystal panel at an operation speed equal to 1/2 of that in the case of one memory for each color and each of the source drivers 5 to 8 can drive the panel at an operation speed equal to 1/4 of that in the case of one memory for each color.
  • the construction of the device is large-sized and complicated.
  • the present invention seeks to provide a liquid crystal drive device having a simplified circuit construction and an excellent linearity.
  • the present invention also seeks to provide a circuit for driving a liquid crystal panel of a multiplex matrix system, which does not require application of a high speed clock signal.
  • the present invention also seeks to provide a circuit for driving a liquid crystal panel of a high speed line sequential system having color filters of a delta arrangement in response to a low speed clock signal with low consumption of power.
  • the present invention also seeks to provide a method of driving a liquid crystal panel of a multiplex matrix system in response to a low speed clock signal with low consumption of power.
  • the present invention also seeks to provide a method of driving a liquid crystal panel of a multiplex matrix system having color filters of a delta arrangement using a low speed clock signal.
  • a circuit for driving a color liquid crystal display panel includes: a plurality of drive means for driving source lines, and a plurality of first storing means for accepting color video signals R, G, B to be displayed and providing the color video signals R, G, B in an order required by the drive means.
  • Each of the first storing means includes: a plurality of analog-to-digital (A/D) converters for A/D conversion for each color of the video signals in one horizontal period; switching means for providing the digital-converted data according to an order of writing; at least a pair of second storing means for storing the digital-converted data and providing the same; data reading means for dividing the data in one horizontal period into two portions, i.e., the first half portion and the second half portion, and reading alternately the divided data of the first half portion and the second half portion from the second storing means; a plurality of latch circuits for latching the data read from the data reading means; and digital-to-analog (D/A) converters for D/A conversion of the data provided from the latch circuits.
  • A/D analog-to-digital
  • a line memory circuit for driving a liquid crystal panel includes: means for providing two types of video signals from a video signal of one horizontal period simultaneously for a first gate line (a scanning line) and for a second gate line forming a pair with the first gate line (the scanning line); and means for storing the two types of video signals thus provided by dividing those signals into at least eight groups corresponding to the first gate line, the second gate line, odd-numbered source lines and even-numbered source lines for the first and second gate lines, the source lines of the first half portion, and the source lines of the second half portion.
  • This line memory circuit further includes: means for reading alternately pixel data to be transmitted from the storing means to the source lines of the first half portion for the first gate line and pixel data to be transmitted to the source lines of the second half portion and reading the pixel data for the second gate line in the same order as for the first gate line after the reading for the first line is terminated; means for transmitting the pixel data supplied from the reading means to the source drivers provided corresponding to at least two groups of the first half portion and the second half portion of the source lines; and signal lines arranged not to intersect with each other, for transmitting the outputs of the source drivers to the source lines of the liquid crystal panel.
  • color video signals R, G, B for one horizontal period in the first storing means are converted to digital data by the A/D converters.
  • the converted digital data are outputted to the second storing means of the pair according to the writing order by the switching means and those data are stored together in the second storing means.
  • the contents stored in the second storing means for the previous horizontal period is divided into the first half and the second half of one horizontal period and those divided portions are read alternately by the data reading means.
  • the read data are converted to the color video signals R, G, B as analog signals by the D/A converters and inputted to the corresponding drive means.
  • the plurality of drive means accept suitably the data of the first half and that of the second half outputted alternately and drive the liquid crystal elements.
  • a line memory circuit In a line memory circuit according to another embodiment of the invention, two types of signals are provided simultaneously for the first line and the second line of the gate lines (the scanning lines) from the video signals for one horizontal period, and the data of the two types of video signals thus provided are written in the storing means. Then, the video signal data corresponding to one gate line is read from the storing means for a 1/2 horizontal period and applied to the source drivers as the pixel drive means. Thus, the liquid crystal panel can be driven according to the high speed line sequential system.
  • the video signal data corresponding to one gate line is divided into a first half and a second half of the source lines and the divided data are read alternately, whereby the video signals can be supplied alternately to the source drivers driving the first half and the second half of the source lines.
  • Fig. 1 is a block diagram showing a structure of a conventional liquid crystal panel.
  • Fig. 2 is a block diagram showing an electric construction of a conventional liquid crystal driving circuit.
  • Fig. 3 is a block diagram showing an electric construction of a line memory circuit for one color in the conventional circuit.
  • Fig. 4 is a block diagram showing an electric construction of a liquid crystal driving circuit of an embodiment of the present invention.
  • Fig. 5 is a block diagram showing an electric construction of a line memory circuit used in the embodiment.
  • Fig. 6 is a timing chart explaining the read operation of the embodiment.
  • Fig. 7 is a timing chart explaining the write operation of the embodiment.
  • Fig. 8 is an illustration showing a scanning order and inversions of polarities of gate lines in a double speed line sequential system.
  • Fig. 9 shows a scanning order and inversions of polarities of gate lines in an interlace system.
  • Fig. 10 shows a scanning order and inversions of polarities of gate lines in a high speed line sequential system.
  • Fig. 11 shows a schematic structure of a liquid crystal panel.
  • Fig. 12 shows an arrangement of color filters of the liquid crystal panel in Fig. 11.
  • Fig. 13 is a diagram showing an example of structure of source drivers for driving the liquid crystal panel shown in Fig. 12.
  • Fig. 14 shows a specified structure of a line memory circuit which provides video signals for the high speed line sequential system according to another embodiment of the invention.
  • Fig. 15 is a block diagram showing a construction for providing two sets of video signal data for odd-numbered gate lines and for even-numbered gate lines from video signals for one horizontal period in the line memory circuit shown in Fig. 14.
  • Fig. 16 is a timing chart showing operation of the A/D converters and the 3-state buffers shown in Fig. 15.
  • Fig. 17 is a block diagram showing an example of specified construction of a data train converting circuit of the line memory circuit shown in Fig. 14.
  • Fig. 18 is a timing chart showing operation of the data train converting circuit shown in Fig. 17.
  • Fig. 19A is a timing chart showing operation of writing trains of data obtained by the data train converting circuit into memories.
  • Fig. 19B is a schematic diagram showing operation of writing of data into each memory and showing write areas in each memory.
  • Fig. 20A is a timing chart showing operation of reading of data from the memories shown in Fig. 14.
  • Fig. 20B is a schematic diagram showing the operation of the timing chart of Fig. 20A in the areas of the memories.
  • Fig. 21 shows an example of construction of the polarity changing circuit included in the line memory circuit shown in Fig. 14.
  • Fig. 22 is a timing chart showing operation of the polarity changing circuit shown in Fig. 21.
  • Fig. 23 is a block diagram showing an example of construction for converting one train of data contained in the line memory circuit shown in Fig. 14 to video signals corresponding to three colors R, G, B.
  • Fig. 24 is a timing chart showing operation of the latch circuits and the D/A converters shown in Fig. 23 and also showing operation for sampling the outputs of the D/A converters by means of the source drivers shown in Fig. 14.
  • Fig. 4 shows schematically an electric construction of a liquid crystal driving circuit according to an embodiment of the present invention.
  • the liquid crystal driving circuit 31 comprises: source drivers 33, 34, 35, 36 for driving a display panel 32 divided into four areas for example; and a pair of line memory circuits 37, 38 for supplying color video signals R, G, B to the source drivers 33 to 36.
  • the source drivers 33 to 36 are arranged in left upper, right upper, left lower and right lower portions in the figure in the periphery of the display panel 32.
  • the line memory circuit 37 supplies the color video signals R, G, B to the source drivers 33, 35, while the line memory circuit 38 supplies the color video signals R, G, B to the source drivers 34, 36.
  • the liquid crystal driving circuit 31 is constituted by using only two line memory circuits 37, 38.
  • Fig. 4 shows as an example a case in which the number of pixel columns (source lines) in the horizontal direction of the screen (the horizontal direction in the figure) of the display panel (herein after referred to simply as the panel) 32 is 640.
  • the 640 pixel columns are driven by the pair of line memory circuits 37, 38 and accordingly the number of pixel columns for one line memory circuit is 320.
  • the panel 32 is constituted according to a multiplex matrix system as in the case of Fig. 2.
  • the left upper first source driver 33 and the right upper third source driver 35 are connected in common to lines l1b, l1r, l1g as output lines of the first line memory circuit 37.
  • the left lower second source driver 34 and the right lower fourth source driver 36 are connected in common to lines l2b, l2r, l2g as output lines of the second line memory circuit 38.
  • Those four source drivers 33 to 36 are supplied with clock signals.
  • the left upper first source driver 33 is supplied with a clock signal of a phase of 0°;
  • the left lower second source driver 34 is supplied with that of a phase of 90°;
  • the right upper third source driver 35 is supplied with that of a phase of 180°;
  • the right lower fourth source driver 36 is supplied with that of a phase of 270°.
  • the above mentioned source drivers 33 to 36 are activated in a circulating manner in the order of the left upper driver, the left lower driver, the right upper driver and the right lower driver, so that the video signals B, R, G are accepted from the corresponding line memory circuits 37, 38.
  • the panel 32 has an order of colors preset as B-G-R-B etc. from the left of the screen for example by color filters not shown. Accordingly, an arrangement of colors is set for each pixel row Y as b1, g2, r3, b4, ... g638, r639, b640 from the left of the screen.
  • Those 640 pixel columns b1 to b640 are divided into two halves at the center of the screen, and the pixel columns b1, g2, r3, ..., b319, g320 included in the first half of one horizontal scanning period of the screen are driven alternately by the first and second source drivers 33 and 34 on the left of the screen, while the pixel columns r321, b322, g323, ... r639, b640 included in the second half are driven alternately by the third and fourth source drivers 35 and 36 on the right of the screen.
  • the pair of line memory circuits 37, 38 which supply the color video signals R, G, B to the first to fourth source drivers 33 to 36 are only different in the order of color signals connected to the corresponding source drivers and in the clock phases for activation, and they operate in the same manner.
  • the acceptance of each of the three colors of the color video signals R, B, G in the first to fourth source drivers 33 to 36 is carried out with a delay of one clock and it circulates for three clocks. Operation of this embodiment will be typically described with respect to the first line memory circuit 37 arranged in the upper portion of the screen and the drive circuit 31a shown by the chain lines in Fig. 4 formed by the first and third source drivers 33 and 35.
  • the order of supply of the respective color signals (R, B, G), that is, the order of reading of the signals from the first line memory circuit 37 with respect to the first and third source drivers 33 and 35 on the upper side of the screen included in the driver circuit 31a needs to be consistent with the order of the color arrangement of the pixel row Y defined by the color filters as described above. Accordingly, as shown, the color signals are supplied to the left first source driver 33 in the order of B-R-G-B etc. and the color signals are supplied to the right third source driver 35 in the order of R-G-B-R etc.
  • the order of acceptance of the color video signals (R, G, B) by the first line memory 37 is the same as that for the first source driver 33, that is, the order of B-R-G etc, and this order is used as the order of writing of the color signals in the first line memory circuit 37 as described later.
  • Fig. 5 is a block diagram showing an electric construction of the line memory circuit 37 of this embodiment.
  • the first and second line memory circuits 37 and 38 shown in Fig. 4 have the same construction. In the following, only the first line memory circuit 37 will be described typically.
  • the characters b, r, g attached to the reference numerals correspond to the color signals B, R, G and in the case of general indications, only the reference numerals are used without the characters b, r, g.
  • the first line memory circuit 37 comprises: A/D converters 39b, 39r, 39g for A/D conversion of the respective color video signals B, R, G applied through line amplifiers not shown; and 3-state buffers 40b, 40r, 40g for on/off control of the digital data of the respective colors provided from the A/D converter 39 according to the order of writing in the memories described later.
  • the line memory circuit 37 further comprises: 3-state buffers 41, 42 for supplying write data provided from the above mentioned 3-state buffer 40 to a pair of memories 43, 44 at the time of writing; and a data multiplexer 45 for providing color signals Bd, Rd, Gd in the memory on the reading side out of the pair of memories 43, 44 capable of writing/reading, to a subsequent data latch circuit 46.
  • the line memory circuit 37 further comprises: data latch circuits 46b, 46r, 46g for latching data of the color signals provided from the data multiplexer 45 according to the reading order; D/A converters 47b, 47r, 47g for converting the data latched by the data latch circuit 46 to analog signals; amplifiers (not shown) for amplifying the levels of the analog-converted color signals B, R, G and providing the outputs to the source drivers (as shown in Fig. 4); and an address multiplexer 49 for selectively instructing write/read operation and addresses for the memories 43, 44 with the prescribed timing.
  • the line memory circuit 37 further comprises: a write address generating circuit 50 for generating a write address in writing of data (in a write cycle), a read address generating circuit 51 for generating an address of the memory to be read in reading of data (in a read cycle), and a line memory control circuit 52 for controlling the operation of those circuit blocks.
  • the number of horizontal pixels related with the line memory circuit 37 is assumed to be N.
  • Digital data corresponding to one row of pixels is written in one memory 43 or 44.
  • the line memory circuit 37 supplies color video signals to both of the source driver 33 of the first half and the source driver 35 of the second half.
  • the memory area of one memory 43 or 44 corresponds to one row of pixels, it is necessary to divide the memory area into a first half and a second half.
  • a boundary address between the first and second halves is obtained as follows. 2 x ⁇ N/2 that is, X ⁇ log2 (N/2)
  • This value x is provisionally called a switching bit.
  • the write address generating circuit 50 generates a write address A1 for writing the digital data of the first half period (H/2) of one horizontal period (H) in the order of 0, 1, ..., j (j ⁇ 2 x ) according to the switching bit, and it generates a write address A2 for writing the digital data of the second half period (H/2) in the order of 2 x + 0, 2 x + 1, ..., 2 x + j.
  • the data to be transmitted to the source driver 33 of the first half is written in the area H of the address 0 to j > 2 x of the memory 43 or 44, while the data to be supplied to the source driver 35 of the second half is written in the memory area A2 of the address of 2 x or more.
  • the address is (x + 1) bits, switching between the areas A1 and A2 can be easily effected if "0" is set in the address area A1 of the first half and "1" is set in the address area A2 of the second half.
  • N 320.
  • the data of the first and second halves are read alternately in one horizontal period H X from the memory (for example, the memory 43) having the data written in the previous horizontal period H X-1 while the address changes as 0, 28, 1, 28 + 1, 2, etc., and in the next horizontal period H X+1 writing/reading of the two memories 43 and 44 are switched, so that the data of the first and second halves are read alternately from the other memory 44 while the address changes as 0, 28, 1, 28 + 1, etc.
  • the writing of the data is carried out in the same manner.
  • the reading/writing operations of the memories 43, 44 are switched for each horizontal period H and while data are being read from one memory, data are written in the other memory. Further, one horizontal period H is divided into the first and second halves and writing/reading operations are carried out alternately in those first and second halves. This construction simplifies the electric construction of the liquid crystal drive circuit 31 and realizes high speed operation.
  • the first line memory circuit 37 comprises the 3-state write buffers 41, 42 on the write ⁇ input side of the pair of memories 43, 44, and the data multiplexer 45 on the read output side, so that writing/reading of data are controlled by the line memory control circuit 52.
  • the second write buffer 42 connected to the second data line l2 is turned on and the digital data of the color video signals B, R, G obtained by A/D conversion are provided to the data line l2 and written in the memory 43.
  • the second input terminal a2 of the data multiplexer 45 attains high impedance with respect to the data line l2, so that input of the above mentioned digital data is inhibited.
  • the first write buffer 41 connected to the first data line l1 attains high impedance and the first input terminal al of the data multiplexer 45 turns on.
  • the digital data from the A/D converter 39 is not provided to the data line l1.
  • the data read from the memory 44 is provided to the first data line l1 and applied to the data latch circuits 46b, 46r, 46g of the next stage through the data multiplexer 45.
  • the read/write cycles of the memories 43, 44 are reversed, so that reading is effected in the memory 43 and writing is effected in the memory 44.
  • the output of the first write buffer 41 and the second input terminal a2 of the data multiplexer 45 are turned on, and the output of the second write buffer 42 and the first input terminal al of the data multiplexer 45 attains high impedance.
  • the digital data from the A/D converter 39 is provided through the first data line l2 and written in the memory 44.
  • data is read from the memory 43 and inputted to the data latch circuits 46b, 46r, 46g of the next stage from the second data line l2 through the data multiplexer 45.
  • writing/reading of the digital data of the color video signals B, R, G are carried out alternately.
  • the A/D converters 39b, 39r, 39g and the D/A converters 46b, 46r, 46g used in the line memory circuit 37 convert data in response to the clock signal ⁇ c applied to the line memory control circuit 52.
  • the A/D converters 39b, 39r, 39g convert the analog color video signals B, R, G to digital data and output the same.
  • the D/A converters 47b, 47r, 47g convert the digital data of the color video signals B, R, G provided from the latch circuits 46b, 46r, 46g to analog signals and supply the same to the lines l1b, l1r, l1g.
  • the 3-state buffers 40b, 40r, 40g of the next stage are enabled successively one by one according to the writing order so that the digital data for one color is outputted successively and written in the memory 43 or 44.
  • the digital data read from the memory 43 or 44 and passing through the data multiplexer 45 are inputted in parallel to the data latch circuits 46b, 46r, 46g and they are classified into three colors in response to the latch pulses applied with timing according to the reading order.
  • the sampling clock frequency band can be caused to be outside the video signal frequency band, making it easy to design filters for removal of sampling clock interference provided in video signal amplifiers, not shown, connected in the preceding stage of each A/D converter 39 (39b, 39r, 39g) and in the succeeding stage of each D/A converter 47 (47b, 47r, 47g).
  • the left first source driver 33 has the order of B-R-G and the right second source driver 35 has the order of R-G-B.
  • the order of acceptance of the color video signals R, G, B by the line memory circuit 37 is the same as the acceptance order of B-R-G of the first source driver 33 as described later and this order is the order of writing in the memory 43 or 44.
  • the order of the output of the accepted color video signals to the pixel row Y is the order of b1-r321-r3-g323-g5-b325-b7 etc. if the output of the data to the first source driver 33 of the first half and that to the second source driver 35 of the second half are provided alternately, as shown in Fig. 4. In this case, it is necessary to output the color video signals of the same color of the second half and the first half successively from the line memory circuit 37 and accordingly there is not sufficient time for switching of the color video signals.
  • the reading order data are read alternately in the order of the second source driver 35 and the first source driver 33, which means the reversed order of the first and second halves in data reading.
  • the order of reading of data is r312-b1-g323-r3-b325-g5 etc. and the respective source drivers 33, 35 can accept the video signals of the same color at equal intervals, which allows sufficient time for switching of the color video signals B, R, G in the line memory circuit 37.
  • the first line memory circuit 37 accepts the color video signals in the order of B-R-G in the first and second memories 43 and 44 and reads the data from the first and second memories 43, 44 in the order of R(second half)-B(first half)-G(second half)-R(first half)-B(second half)-G(first half) etc. so as to provide the color video signals B, R, G in the order required by the first and second source drivers 33 and 35.
  • Figs. 6 and 7 are timing charts showing operation of the line memory circuit according to this embodiment.
  • the screen 2 is divided into the upper and lower portions which are controlled by the first and second line memory circuits 37 and 38, respectively.
  • Those two line memory circuits 37 and 38 operate in the same manner and those circuits are different only in the phases of the supplied operation clock signals and the orders of acceptance of the source drivers for the respective colors. Therefore, Figs. 6 and 7 show the timing of the reading operation and that of the writing operation of only the first memory circuit 37.
  • Fig. 6(a) represents timing of a clock signal ⁇ C applied to the first line memory circuit 37
  • Fig. 6(b) represents timing of a source driver clock signal applied to the first and third source drivers 33 and 35.
  • Fig. 6(c) represents a waveform of a read address signal provided from the read address generating circuit 51 shown in Fig. 5.
  • the data of the color video signals R, G, B for one horizontal period is divided into first and second halves and the data of the second half is stored in the memory 43 or 44 from an address of 28, namely, the address 256, while the data of the first half is stored therein from the address 0.
  • the read address generating circuit 51 provides alternately the addresses where the data of the first and second halves are stored.
  • the data latch signals ⁇ R , ⁇ G , ⁇ B corresponding to the respective colors of the color video signals R, G, B are supplied for each pulse of the clock signals ⁇ C from the line memory control circuit 52 to the data latch circuits 46b, 46r, 46g separately.
  • the data read in accordance with the read address signal shown in Fig. 6(c) is latched by the corresponding data latch circuit 46.
  • the data latch signals ⁇ B , ⁇ R , ⁇ G are provided in the order of B data latch ⁇ B - R data latch ⁇ R - G data latch ⁇ G .
  • Figs. 6(d), (f), (h) represent the timings of the data latch signals thus provided corresponding to the respective colors.
  • Fig. 6(e) represents timing that the data of the color video signal B is sequentially latched in response to the B data latch signal ⁇ B
  • Fig. 6(g) represents timing that the data of the color video signal R is sequentially latched
  • Fig. 6(h) represents timing that the data of the color video signal G is sequentially latched.
  • the latch signals ⁇ B , ⁇ R , ⁇ G for latching the data of the respective colors have a rotation in three clocks of the clock signal ⁇ C shown in Fig. 6(a) and the data is latched once for three clocks in the latch circuit 46b, 46r, 46g.
  • the latched data are supplied to the D/A converters 47b, 47r and 47g of the succeeding stage, where they are converted to analog signals. Then, those analog signals are accepted successively by the first and second source drivers 33 and 35 with timing of the source driver clock ⁇ S , and sampled and held therein. After that, the respective color signals from the source drivers 33, 35 to the source lines are transmitted with prescribed timing (e.g., with timing of the horizontal synchronizing signal), and the pixel p connected to the activated scanning line (gate line) l x illuminates.
  • prescribed timing e.g., with timing of the horizontal synchronizing signal
  • Fig. 7(a) represents timing of the clock signal ⁇ C applied to the first line memory circuit 37, similarly to Fig. 6(a).
  • the respective A/D converters 39b, 39r, 39g convert the color video signals R, G, B to digital data in the same order as the arrangement order of pixels (the color order).
  • Figs. 7(b), (c), (d) represent timings of output of the digital-converted data of the respective colors.
  • the time t0 defines timing of start of one horizontal period.
  • Fig. 7(e) represents timing of a write address signal outputted from the write address generating circuit 50.
  • the address multiplexer 49 provides write signals ⁇ B , ⁇ R , ⁇ G of the respective colors in synchronization with the clock signal ⁇ C as shown in Figs. 7(f), (h), (j).
  • the 3-state buffer 40b outputs the data of the color video signal B digital-converted by the A/D converter 39b as shown in Fig. 7(g).
  • the 3-state buffer 40r outputs the data of the color video signal R digital-converted by the A/D converter 39r as shown in Fig.
  • the respective source drivers 33 to 36 are able to operate in response to the low speed clock signal ⁇ S .
  • only one pair of line memory circuits 37, 38 are provided and the data of the respective color signals are latched and outputted at a speed equal to 1/3 of that of the line memory clock ⁇ C in the respective line memory circuits 37, 38, which makes it possible to drive the liquid crystal panel at high speed by using the source drivers operating at low speed.
  • only one pair of line memory circuits are provided and each line memory circuit can process the three colors, it is possible to obtain a small-sized and inexpensive liquid crystal drive circuit having a simple structure.
  • the same arrangement of colors is applied to the respective scanning lines (gate lines) and that the color filters (pixels) are arranged in a matrix of rows and columns.
  • the scanning order of the scanning lines (gate lines) it was not specifically stated whether an interlace system or a non-interlace system is adopted. Since the scanning order is defined by the scanning driver 4 (as shown in Fig. 1A) in the above described structure, either system is applicable to the structure of the line memory circuits 37, 38.
  • the polarity of the signal applied to the liquid crystal is inverted every prescribed cycles. More specifically, if a liquid crystal panel is to be driven, gate lines (i.e., signal lines for selecting a row to which a row of liquid crystal elements in the liquid crystal panel are connected; scanning lines) are scanned sequentially so that all the gate lines can be scanned in one field. In this case, the polarity of the video signal is inverted for one horizontal period according to the scanning of the gate lines. If the gate lines are so many that they cannot be scanned in the period of one field, two systems called the double line sequential system and the interlace system are conventionally utilized to scan all the gate lines in the prescribed one-frame period.
  • the double line sequential system and the interlace system are conventionally utilized to scan all the gate lines in the prescribed one-frame period.
  • pairs of two gate lines are scanned and those pairs of gate lines are alternately selected for each field, as shown in Fig. 8.
  • the gate lines g1, g2 forming a pair are scanned simultaneously and the gate lines g3, g4 forming a pair are also scanned simultaneously.
  • the pair of gate lines g5, g6 are scanned and the pair of gate lines g7, g8 are scanned.
  • a positive signal is applied to each liquid crystal pixel in the gate lines g1, g2; a negative signal is applied to each liquid crystal pixel in the gate lines g3, g4; and a positive signal is applied to each liquid crystal pixel in the gate lines g5, g6.
  • the gate lines g2, g3 forming a pair are scanned and the gate lines g4, g5 forming a pair are scanned.
  • a negative signal is applied to each liquid crystal pixel of the gate lines g2, g3 and a positive signal is applied to each liquid crystal pixel of the gate lines g4, g5.
  • the pairs of gate lines are selected and scanned sequentially. In this double speed line sequential system, the polarity of the signal for the liquid crystal pixels connected to one gate line is changed for two fields (i.e., one frame).
  • One horizontal period (1H) is a period in which all the liquid crystal pixels connected to one gate line are driven, and this period corresponds to one horizontal scanning period of a display device of an ordinary raster scanning system.
  • One field corresponds to a frequency of 60Hz.
  • This double speed line sequential system has an excellent responsitivity for moving pictures since all the gate lines can be scanned in the period of one field.
  • the respective pairs of two gate lines namely, the odd-numbered gate lines and the even-numbered gate lines are scanned simultaneously and, accordingly, if the color filters of a color display liquid crystal panel have a delta arrangement, correction for the delta arrangement cannot be effected, resulting in deterioration of a horizontal resolution.
  • the delta arrangement mentioned above is a color arrangement of the color filters in which different colors, namely, color filters of R, G, B are arranged at respective apexes of an arbitrary regular triangle composed of pixels of the liquid crystal panel.
  • the gate lines are scanned alternately in each field and all the gate lines are scanned in two fields. More specifically, according to this interlace system, the odd-numbered gate lines g1, g3, g5, g7 are scanned in the field A and the even-numbered gate lines g2, g4, g6, g8 are scanned in the next field B. If the color filters of the liquid crystal panel have a delta arrangement and the signal electrodes for applying a signal potential to the pixels are arranged in a zigzag form, the odd-numbered gate lines and the even-numbered gate lines are staggered by 1.5 pixel. Consequently, the odd-numbered gate lines and the even-numbered gate lines cannot be driven with the same timing.
  • the cycle of inversion of the polarities of the signals required for AC drive of the liquid crystal panel corresponds to two frames, namely, 15Hz as shown in Figs. 8 and 9 and accordingly flickering is liable to occur.
  • the above described disadvantages of the double speed line sequential system and the interlace system concerning the correction of the delta arrangement, the responsitivity for moving pictures and the occurrence of flickering can be overcome by the high speed line sequential system.
  • this high speed line sequential system two gate lines are scanned in one horizontal period.
  • the two gate lines are not scanned simultaneously but one of the gate lines is scanned in a half period of one horizontal period and the other gate line is scanned in the remaining half period, whereby the two gate lines are scanned in one horizontal period.
  • this high speed line sequential system is different from the double speed line sequential system in this point.
  • the gate lines g1 and g2 forming a pair are selected and the gate line g1 is scanned in the first half period of one horizontal period and the gate line g2 is scanned in the remaining half period. Since the gate lines are scanned one by one in this high speed line sequential system, the delta arrangement can be corrected and since two gate lines are scanned in one horizontal period, all the gate lines can be scanned in a one-field period, enhancing the responsitivity for moving pictures. In addition, since the gate lines are scanned individually one by one, it is possible to invert the polarity of the video signal when scanning in the 1/2 horizontal period, namely, scanning of one gate line is completed.
  • the cycle of inversion of the polarities of the signal required for AC drive of the liquid crystal panel can be made to correspond to one frame, namely, 30Hz to attain high-speed operation, making it possible to suppress flickering in the liquid crystal panel.
  • the polarity of the signal of the gate lines can be inverted for each of the frames A, B, C, D, E and the polarity inversion cycle of the signal corresponds to one frame.
  • the timing of application of a video signal to the odd-numbered gate lines and that to the even-numbered gate lines need to differ by 1.5 pixel period and, accordingly, even if video signals for two gate lines are produced from a video signal for one gate line, those two types of video signals cannot be directly supplied to the source drivers and some signal processing is required.
  • one gate line is scanned in a half horizontal period and a signal potential for this gate line needs to be transmitted to each liquid crystal pixel, it is necessary to operate the source drivers which transmit the signal potential to each pixel, with a clock frequency twice larger than that in the conventional line sequential system or interline system, causing deterioration in the linear characteristic or increase of consumption of power.
  • a line memory circuit for driving a liquid crystal panel has the below described construction.
  • the respective color signals R (red), G (green) and B (blue) of the video signals are divided for two gate lines, i.e., an odd-numbered line and an even-numbered line, and A/D conversion is effected for the respective two lines in parallel for one horizontal period with the above mentioned difference in timing corresponding to 1.5 clock.
  • the 3-state buffers are provided in the succeeding stage of the A/D converters provided corresponding to the respective colors R, G, B of the video signals.
  • the operation timings of those 3-state buffers are controlled, whereby the data output timings of the respective colors R, G, B provided from the A/D converters are controlled to output the video data of the respective colors R, G, B in the same arrangement order as that of the color filters of the liquid crystal panel.
  • video data for one horizontal period with respect to the odd-numbered gate lines and that with respect to the even-numbered gate lines are formed.
  • the data train thus formed corresponding to one horizontal period is divided into the two groups of the odd-numbered gate lines and even-numbered gate lines and, accordingly, in the structure where the video data are written directly in the two memories, i.e., the one for the odd-numbered gate lines and the other for the even-numbered gate lines, data reading operation is effected only from one of the memories in a 1/2 horizontal period, which causes deterioration in the memory access efficiency and makes it necessary to read the video data from the memory for a half of the time required for writing of data (the time corresponding to one horizontal period). Therefore, in order to access the memories efficiently not only in writing of data but also in reading of data, data train conversion is effected before the video signal data are written in the memories.
  • the data trains divided into the two groups of the odd-numbered lines and the even-numbered lines are further distributed as video data corresponding to the odd-numbered source lines and video data corresponding to the even-numbered source lines.
  • the video signals supplied to the source drivers become pixel data trains in which video data for pixels of the odd-numbered source lines and that of the even-numbered source lines appear alternately. Accordingly, if the above mentioned data train conversion is effected, reading of the video data for the even-numbered source lines and reading of the video data for the even-numbered source lines are effected alternately.
  • the two memories, the one for storing the video data for the odd-numbered source lines and the other for storing the video data for the even-numbered source lines are provided. In the case of the construction for the above described conversion of the data trains, data reading operations from those two memories are carried out alternately. Thus, the memory access efficiency is improved and it becomes possible to read the data simultaneously with writing of data.
  • the video data for the odd-numbered gate lines and that for the even-numbered gate lines are written alternately in the corresponding memories. More specifically, in the conversion of the data trains, the data of the odd-numbered gate lines and that of the even-numbered gate lines are written alternately with respect to the odd-numbered source lines for example and, similarly, the video data for the odd-numbered gate lines and that for the even-numbered lines are written alternately with respect to the even-numbered source lines. Accordingly, for each 1/2 horizontal period, the bit Y for switching between the odd-numbered and even-numbered gate lines is reset and set alternately in a repeating manner so that the write address is incremented by one.
  • the area of the memory where the video data for the odd-numbered gate lines is written for a 1/2 horizontal period corresponds to the reset of the switching bit Y and the video data for the even-numbered gate lines is stored in the address where the switching bit Y is set, namely, in the second half area of the memory.
  • the switching bit X for switching between the first and second halves of the respective source lines is reset and set for the first half of the horizontal period and for the second half of the horizontal period.
  • the write position of the memory can be different dependent on the first half of the horizontal period and the second half thereof.
  • the storage space of one pair of memories is divided into eight areas, namely, areas corresponding to the respective two gate lines, areas corresponding to the first and second halves of the odd-numbered source lines, and areas corresponding to the first and second halves of the even-numbered source lines, and the corresponding video data is written in each of those eight areas.
  • the order of arrangement of the read data needs to be coincident with the order of the video signals supplied to the source drivers and, accordingly, the switching bit X for switching of the first and second halves of the source lines are repeatedly reset and set alternately for each 1/2 horizontal period so that the read address is incremented by one.
  • the switching bit Y for switching of the odd-numbered and even-numbered gate lines is reset or set according to the field dependent on the first 1/2 horizontal period and the second 1/2 horizontal period. More specifically, in a certain field, the switching bit Y is reset in the first 1/2 horizontal period and the switching bit Y is set in the second 1/2 horizontal period In another field, the switching bit Y is set in the first 1/2 horizontal period and it is reset in the second 1/2 horizontal period.
  • the video data read from the memories according to the above mentioned read address is a digital signal and, on the other hand, the video signal is applied to the source drivers in the form of an analog signal. Accordingly, the read video data needs to be converted from the digital signal to the analog signal and before this D/A conversion, digital polarity switching is carried out.
  • inversion and non-inversion of the bit value of the data are effected in response to the polarity switching signal and the video signal having passed through the digital polarity switching circuit is converted from the digital data to analog data, whereby the polarity of the video signal is changed.
  • the construction for switching the video signal polarity is that an analog video signal is applied to an inversion amplifier and to a non-inversion amplifier so that the outputs of the respective amplifiers are switched and outputted by using an analog switch in response to the polarity switching signal. Accordingly, in the case of the conventional construction for switching the polarity in the analog form, three devices, namely, the inversion amplifier, the non-inversion amplifier and the analog switch are required, which increases the circuit size.
  • inversion and non-inversion of the bit value of the video data can be effected selectively in response to the switching signal by using an exclusive OR gate (Ex-OR) or the like and only one amplifier is required after the D/A conversion. Accordingly, it is not needed to provide two types of amplifiers such as an inversion amplifier and a non-inversion amplifier, and in the case of the construction of digital processing by A/D conversion of the video signal, such a polarity switching circuit can be realized with a small number of components.
  • Ex-OR exclusive OR gate
  • the video data having passed through the digital polarity switching circuit needs to be subjected to D/A conversion to obtain video signals of the respective colors R, G, B.
  • the latch circuits provided in the preceding stage of the D/A converters are operated according to the color order of the read data train, whereby the data of the respective colors are supplied to the corresponding D/A converters, where the data are converted to respective analog video signals.
  • the analog video signals thus obtained are video signals for the high speed line sequential system and a video signal corresponding to one gate line can be supplied to the source driver in a 1/2 horizontal period.
  • the analog video signals of the three colors R, B, G are converted to video digital data by using the A/D converters provided corresponding to the respective colors and after the video signals of the three colors R, G, B are converted to one data train by adjusting the operation timings of the 3-state buffers provided in the succeeding stage of the respective A/D converters, desired digital processing is applied to the train. After that, by adjusting the operation timings of the latch circuits, the data train is separated as digital video data of the respective colors, which are supplied to the D/A converters provided corresponding to the respective colors R, G, B, so that those digital video data are converted to analog video signals.
  • the digital processing circuit portions between the 3-state buffers and the latch circuits can process the data of the respective colors together without dividing the data, which makes it possible to reduce the number of components.
  • This embodiment is related to a case as shown in Fig. 11, in which the number of pixels of the liquid crystal panel 147 in the horizontal direction is 640 in total for all of the three colors R, G, B, the number of pixels in the vertical direction is 480, and the arrangement of color filters of this liquid crystal panel is a delta arrangement as shown in Fig. 12. Further, four source drivers 143, 144, 145 and 146 are provided to drive the liquid crystal panel 147, corresponding to four groups consisting of a group of odd-numbered source lines, a group of even-numbered source lines, and groups of the first half and second half portions of the respective source lines in the liquid crystal panel.
  • the source driver 143 applies video signals to the odd-numbered source lines of the first half portion, and the source driver 144 applies video signals to the odd-numbered source lines of the second half portion.
  • the source driver 145 applies video signals to the even-numbered source lines of the first half portion, and the source driver 146 applies video signals to the even-numbered source lines of the second half portion.
  • the number of source lines is 640 as described above and the respective source lines are denoted sequentially by the numerals of 1 to 640 in the same manner as in Fig. 4.
  • the characters B, G, R of the liquid crystal panel 147 represent the colors of the pixels and the numerals shown under the respective characters B, G, R represent the numerals assigned to the source lines.
  • the scanning drivers for driving the gate lines are not shown in the figure.
  • the number of source lines of the liquid crystal panel 147 is 640 which is equal to the number of pixels in the horizontal direction
  • the number of gate lines is 480 which is equal to the number of pixels in the vertical direction.
  • the source lines are arranged in a zigzag form in the liquid crystal panel 147 as shown in Fig. 12 since the color filters are arranged in a delta form, and one source line drives liquid crystal pixels of the same color in the respective gate lines.
  • the signal output terminals of the source drivers 143 to 146 are connected with the source lines of the liquid crystal panel 147 so that the connections do not intersect with each other.
  • the arrangement of the pixels 148 of the liquid crystal panel 147 is staggered by 1.5 pixels between the odd-numbered gate lines and the even-numbered gate lines.
  • Each of the source drivers 143 to 146 for driving the respective source lines of the liquid crystal panel 147 has a structure as shown in Fig. 13.
  • the source driver comprises: a shift register 149 activated in response to a start pulse ⁇ 3 for shifting a selection activation signal from the output terminal one by one in response to a clock ⁇ 4; analog switches 150-1 to 150-m for transmitting respective video signals V1 to V3 in response to the selection activation signals from the shift register 149; and an analog sample-and-hold circuit 151 for sampling and holding the video signals applied through the analog switches 150 (150-1 to 150-m) and supplying the held video signals to the corresponding source lines when the signals for all the source lines are held.
  • the analog switches 150 are turned on successively in response to the selection activation signals from the shift register 149 to transmit the corresponding video signals to the analog sample-and-hold circuit 151.
  • the video signals V1 to V3 correspond to the video signals of the respective colors R, G, B and those video signals of the respective colors are transmitted in parallel. Accordingly, in this structure, if the R video signal is transmitted to the analog sample-and-hold circuit 151, the video signals of the remaining colors are not transmitted. Thus, only the video signal of one color, namely, the video signal of one pixel is always transmitted to the analog sample-and-hold circuit 151 through the analog switch 150.
  • the analog sample-and-hold circuit 151 samples and holds the signals transmitted through the analog switches 150 while supplying the signals to the source lines.
  • the line memory circuit 142 comprises: a block 100 for providing video signals for two rows for an odd-numbered gate line and an even-numbered gate line (namely, two gate lines) from the video signals V B , V R , V G for one horizontal period; a data train converting circuit 113 for providing a data train in which the video signals for the two gate lines from the block 100 are arranged selectively as a video signal for the even-numbered source lines and a video signal for the odd-numbered source lines; a memory block 200 for dividing the video signal data for the odd-numbered source lines and the video signal data for the even-numbered source lines from the data train converting circuit 113 into video signal data for the source lines of the first half and video signal data for the source lines of the second half, classifying the data into eight groups in total (groups of the odd-numbered gate line, the even
  • the block 100 which provides video signal data for two gate lines comprises A/D converters 101 to 106 for sampling the respective analog video signals V G , V R , V B at prescribed timings and converting the same to digital signals; and 3-state buffers 107 to 112 for accepting the respective outputs of the A/D converters 101 to 106 with prescribed timing to output the same.
  • the A/D converter 101 to 103 provide video signal data corresponding to one gate line (e.g., an odd-numbered gate line) and the A/D converters 104 to 106 provide video signal data corresponding to other gate line e.g., an even-numbered gate lines).
  • the group of the buffers 107 to 109 and the group of the buffers 110 to 112 have different timings for accepting and outputting the signals and, in those buffers, three trains of video signal data corresponding to the R, G, B signal data) are converted to one train of data.
  • the memory block 200 comprises four line memories 118, 119, 120 and 121 in total, namely, a pair of two memories, the one for storing video signal data to be supplied to odd-numbered source lines and the other for storing video signal data to be supplied to even-numbered source lines, and another pair of similar memories for performing writing operation and reading operation in the memories simultaneously.
  • the memories 118, 119 operate as a pair, and the memories 120, 121 operate as a pair.
  • Video data to be supplied to odd-numbered source lines for example are written in the memories 118, 120, and video signal data to be supplied to even-numbered source lines for example are stored in the memories 119, 121.
  • 3-state buffers 114, 115 for receiving the output data train of the data train converting circuit 113, and a data bus multiplexer 125 for selectively transmitting either of the outputs of the buffers 114, 115 to one of the memories 118, 120 and connecting the output bus of the memory where data is not written to the polarity changing circuit 127.
  • 3-state buffers 116, 117 for transmitting the output of the data train converting circuit 113, and a data bus multiplexer 126 for connecting data writing lines from the buffers 116, 117 to the memories 119, 121, and data reading lines from the memories 119, 121 to the polarity changing circuit 128.
  • the output of the 3-state buffer 114 is transmitted to the memory 118 and the output of the 3-state buffer 115 is transmitted to the memory 120.
  • the output of the 3-state buffer 116 is transmitted to the memory 119 and the output of the 3-state buffer 117 is transmitted to the memory 121.
  • the data bus multiplexer 125 transmits the output of the memory 120 to the polarity changing circuit 127 while data from the buffer 114 is being written in the memory 118.
  • the data bus multiplexer 126 transmits the output of the memory 121 to the polarity changing circuit 128 while the output of the buffer 116 for example is being written in the memory 119.
  • a write address generating circuit 123 for providing a write address
  • a read address generating circuit 124 for providing read addresses of the memories 118 to 121
  • an address bus switching circuit 122 for transmitting selectively the address signals from the write address generating circuit 123 and the read address generating circuit 124 to the memories 118, 119 and to the memories 120, 121 according to the reading operation and the writing operation of the respective memories.
  • the address bus switching circuit 122 transmits the output of the address generating circuit 123 to the memories 118, 119 while the memories 118, 199 carry out writing operation, and, at the same time, it transmits the address from the read address generating circuit 124 to the memories 120, 121.
  • the address bus switching circuit 122 transmits the read address from the read address generating circuit 124 to the memory which carries out reading operation, and transmits the write address from the write address generating circuit 123 to the memory which carries out writing operation.
  • the block 300 comprises latch circuits 129 to 134 formed by D-flip-flops for example, for converting one train of data provided through the polarity changing circuits 127, 128 to three trains of video signals (i.e., the respective video signals of R, G, B), and D/A converters 135 to 140 for converting the respective outputs of the latch circuits 129 to 134 to analog signals with prescribed timing.
  • the group of the latch circuits 129 to 131 and that of the latch circuits 132 to 134 have different latch timings and each group carries out latching operation at prescribed timing for one train of data provided from each of the polarity changing circuits 127, 128, whereby only the video signal data of the corresponding colors are latched. More specifically, the latch circuits 129, 132 latch the B video signal data, the latch circuit 130, 133 latch the R video signal data, and the latch circuits 131, 134 latch the G video signal data.
  • a control circuit 141 which starts operation in response to a line memory start signal ⁇ s1, has its operation timing defined in response to a line memory clock signal ⁇ c1, and provides various control signals with prescribed timing.
  • a control circuit 141 which starts operation in response to a line memory start signal ⁇ s1, has its operation timing defined in response to a line memory clock signal ⁇ c1, and provides various control signals with prescribed timing.
  • Figs. 15 and 16 show a construction for providing video signal data corresponding to one gate line.
  • Fig. 15 shows A/D converters 152-154 which effect A/D conversion in response to a line memory clock ⁇ 2, and 3-state buffers 155 to 157 which accept and provide the data at different timings.
  • the 3-state buffer 155 accepts and outputs the data in response to a control signal (gate) GB
  • the buffer 156 accepts and outputs the data in response to a control signal GR
  • the buffer 157 accepts and outputs the data in response to a control signal GG .
  • the respective analog video signals V B , V R , V G are sampled in the A/D converters 152 to 154 at the rise of the line memory clock ⁇ 2 and those signals are outputted as digital video data in response to the next fall of the clock ⁇ 2.
  • the respective 3-state buffers 155 to 157 output the signals supplied thereto when the respective control signals GB , GR , GG attain L level.
  • the control signals GB , GR , GG form three-phase non-overlapping clocks synchronizing with the clock signal ⁇ 2 as shown in (e), (f), (g) of Fig. 16 and accordingly, the data trains outputted from the buffers 155 to 157 have the same order as the color arrangement of the color filters of the liquid crystal panel.
  • the A/D converters 152 to 154 provided corresponding to the respective colors R, G, B are driven in response to the same clock, the clock phase for the odd-numbered gate lines and that for the even-numbered gate lines are different by 180° for the reasons described below.
  • the video signal data for one pixel in the horizontal direction of the liquid crystal panel is sampled and outputted for one clock of the A/D converters.
  • the arrangement of pixels of the odd-numbered gate lines and that of the even-numbered gate lines are staggered by 1.5 pixels. This staggering of 1.5 pixels causes a lag of 1.5 clock cycles in the clock signal ⁇ 2.
  • the difference of 1.5 clock cycle is equal to a value obtained by adding a clock phase 180° to the lag of 1 clock cycle and the lag of 1 clock cycle is equal to the clock phase of 360°, namely, 0°.
  • the activation timing of the buffers 155 to 157 namely, the buffers 107 to 109 in Fig. 14 and that of the buffers 110 to 112 differ from each other by a half of the line memory clock ⁇ 2.
  • the digital video data trains for the odd-numbered and even-numbered gate lines formed by the buffers 107 to 109 and 110 to 112 are supplied to the data train converting circuit 113 and they are converted to a digital signal data train to be applied to the odd-numbered source lines and a digital signal data train to be applied to the even-numbered source lines.
  • the specified construction and the operation of the data train converting circuit 113 will be described with reference to Figs. 17 and 18.
  • the digital data train converting circuit 113 comprises: a latch circuit 158 formed by a D-flip-flop for example which receives the video signal data train for the odd-numbered gate lines; a latch circuit 159 formed by a D-flip-flop for example which receives the video signal data for the even-numbered gate lines; a digital bus switching circuit 160 which receives the signals from the latch circuits 158, 159 and selects a transmission line in response to a selection signal SEL; and a latch circuit 161 formed by a D-flip-flop for example which latches the signal from the digital bus switching circuit 160.
  • a data train to be applied to the odd-numbered source lines is outputted from the latch circuit 161 and a digital data train to be applied to the even-numbered source lines is outputted from the digital bus switching circuit 160 directly through other data bus.
  • the latch circuits 158, 159 and 161 carry out latch operation in response to the line memory clock ⁇ 2.
  • the selection signal SEL applied to the digital bus switching circuit 160 has a cycle twice as long as that of the line memory clock ⁇ 2. Next, the operation will be described.
  • the output timing of the digital signal data train for the odd-numbered gate line and that for the even-numbered gate line are different from each other by 1.5 clock (see Figs. 18(b) and (c)).
  • the digital signal data train for the odd-numbered gate line and that for the even-numbered gate line having the phases different from each other by 1.5 clock are supplied to the latch circuits 158, 159, respectively and latched by the same line memory clock ⁇ 2. Since the latch circuits 158, 159 are formed by the D-flip-flops, the data trains are outputted from the latch circuits 158, 159 with a delay of 1 clock (as shown in Figs. 18(d), (e)).
  • the data trains having the phases with the delay of 1 clock are switched in the digital bus switching circuit 160 in response to the selection signal SEL. More specifically, by switching of the input/output connection lines in the digital bus switching circuit 160, the digital data train to be applied to the odd-numbered source lines and the digital data train to be applied to the even-numbered source lines are outputted from the digital bus switching circuit 160 as shown in (g), (h) of Fig. 18.
  • the digital data for the even-numbered gate lines and that for the odd-numbered gate lines appear alternately in the respective data trains. Since the output signal from the digital bus switching circuit 160 has the phase delayed by 1 clock as shown in Fig. 18, it is necessary to carry out operation of writing of the digital data directly in the memories with a delay of 1 clock and it is also necessary to generate a write address for the memories with a delay of 1 clock. Accordingly, if the above mentioned construction is adopted, there is disadvantage that the circuit size is increased.
  • the digital data train having the phase advanced by 1 clock out of the output signal data trains from the digital bus switching circuit 160 i.e., the digital signal data train to be applied to the odd-numbered source lines in Figs. 17 and 18
  • the digital bus switching circuit 160 i.e., the digital signal data train to be applied to the odd-numbered source lines in Figs. 17 and 18
  • the transmission thereof is delayed by 1 clock, whereby the timing of the video signal data train to be applied to the even-numbered source lines and the timing of the video signal train to be applied to the odd-numbered source lines can be made coincident.
  • writing operation for the digital data in the memories can be carried out simultaneously and the write addresses for the memories can be generated by one write address generating circuit so as to be assigned to the respective memories, which makes it possible to reduce the number of components.
  • the storage capacity for one memory is 1024 words, which is calculated from 2 (Y+1) .
  • the length of each of those words is defined by the resolutions of the A/D converters and D/A converters.
  • Writing and reading of data are selectively controlled by the 3-state buffers 114 to 117 provided in the preceding stages of the respective memories, and by the data bus multiplexers 125 and 126 provided in the reading lines of the memories 118 to 121 in order to selectively switch between the writing and reading of data for the memories 118 to 121 and to avoid collision between the read data and the write data.
  • the 3-state buffers 114 and 116 provided in the preceding stages of the memories 118 and 119 are enabled and the video signal data train from the data train converting circuit 113 is written in the memories 118 and 119.
  • the 3-state buffers 114 and 116 provided in the respective preceding stages are disabled so that the data read from the memories 118 and 119 may not collide with the data from the data train converting circuit 113.
  • the data bus multiplexers 125, 126 provided in the succeeding stages of the memories always select the data bus connected to the memory where reading is effected, out of the memories 118 to 121 and connect the selected data bus to the polarity changing circuits 127, 128 in the succeeding stages. Accordingly, the switching control signal ⁇ W applied to the data bus multiplexers 125, 126 become a control signal synchronizing with the write/read control signal RW applied to the memories 118 to 121 and the connection lines for the data bus is selectively changed for each horizontal period.
  • the write address for designating a write position in the memory provided from the write address generating circuit 123 is incremented by one according to the output timing of the data from the data train converting circuit 113, as shown in Fig. 19A, while resetting and setting of the odd-numbered gate line/even-numbered gate line switching bit Y are repeated.
  • the source line first half/second half switching bit X is reset in the first 1/2 horizontal period and it is set in the second 1/2 horizontal period. At the time when the switching bit X is switched, the less significant address (the address excluding the switching bits X and Y) is reset.
  • the write addresses in the first 1/2 horizontal period are 0, 2 Y + 0, 1, 2 Y + 1, ..., N/4 -1, 2 Y + N/4 - 1 and those in the second 1/2 horizontal period are 2 X + 0, 2 X + 2 Y + 0, 2 X + 1, 2 X + 2 Y + 1 ..., 2 X + N/4 - 1, 2 X + 2 Y + N/4 - 1.
  • the write addresses generated in the first 1/2 horizontal period are 0, 512, 1, 513, ..., 159, 671 and the write addresses generated in the second 1/2 horizontal period are 256, 768, 257, 769, ..., 415, 927, as shown in Fig.
  • the area A is an area where the video digital signal data for the even-numbered gate lines are stored and the area B is an area where the video digital signal data for the odd-numbered gate lines are stored. Accordingly, each of the memories for the odd-numbered and even-numbered source lines has four divided areas and thus the video signal data are stored in a manner divided in the eight areas in total.
  • the addresses for reading the digital data from the memories 118 to 121 are generated from the read address generating circuit 124 and transmitted through the address bus switching circuit 122 to the memory where reading operation is being carried out.
  • the read address generated from the read address generating circuit 124 is incremented by one while the source line first half/second half switching bit X is reset and set alternately and repeatedly as shown in Fig. 20A. If the odd-numbered gate lines are selected in the first 1/2 horizontal period, the odd-numbered/even-numbered gate line switching bit Y is reset. If the even-numbered gate line are selected in the second 1/2 horizontal period, the odd-numbered/even-numbered gate line switching bit Y is set. Thus, in reading of data, if the odd-numbered gate lines are selected, the switching bit Y is reset and if the even-numbered gate lines are selected, the switching bit Y is set.
  • the data are stored in the memories in this order. Accordingly, the color order of the video signal data read by the above described read addresses is B(0), R(256), R(1), G(257), G(2), B(258), etc. on the odd-numbered source lines and the color order of the data read on the even-numbered source lines is G(0), B(256), B(1), R(257), R(2), G(258), etc. where the numerals in the parentheses represent the addresses. Accordingly, if the video digital signal data train thus read is converted to analog video signals by D/A conversion, signals of the same color are contiguous to each other, no allowance exists for selecting the signals and transmitting the signals selectively to the source drivers for driving the liquid crystal panel.
  • the source line first half/second half switching bit X is set and reset repeatedly oppositely to the case of writing of data, whereby it is incremented by one. More specifically, if the source drivers accept the data starting from the data of the second half of the source lines, the color order of the video digital data on the odd-numbered source lines is R, B, G, R, B, G while that on the even-numbered source lines is B, G, R, B, G, R. This arrangement is the same as the color arrangement of the color filters of the liquid crystal panel, which makes it possible to easily distribute the signals to the source drivers.
  • the read addresses are 2 X + 0, 0, 2 X + 1, 1, ..., 2 X + N/4 - 1, N/4 - 1 and if the digital video data for the even-numbered gate lines are applied in the second 1/2 horizontal period, the read addresses are 2 Y + 2 X + 0, 2 Y + 0, 2 Y + 2 X + 1, 2 Y + 1, ..., 2 Y + 2 X + N/4 -1, 2 Y + N/4 - 1.
  • the read addresses in the first 1/2 horizontal period are 256, 0, 257, 1, ..., 415, 159 and the read addresses in the second 1/2 horizontal period are 768, 512, 769, 513, ..., 927, 671 as shown in Fig. 20A.
  • the even-numbered gate lines are selected, the data are read from the memory for the odd-numbered source lines in the order of the areas A2, A1 alternately. If the odd-numbered gate lines are selected, the data are read alternately in the order of the areas B2, B1.
  • the memory for the even-numbered source lines and the data are read alternately in the order of the area A2′, A1′ or in the order of the areas B2′, B1′ in the manner as shown in Fig. 20B (b).
  • the read addresses and the write addresses for the memories can be made to be common to both of the memory for the odd-numbered source lines and the memory for the even-numbered source lines. Consequently, only by providing one address generating circuit for each of writing and reading, and assigning the addresses from the address generating circuit simply by means of the address bus switching circuit 122, it is possible to write and read video signal data.
  • the digital video signal data read through the data bus multiplexers 125, 126 the respective bit values thereof are inverted in the digital polarity changing circuits 127, 128.
  • An example of specified construction of each of the digital polarity changing circuits 127, 128 is shown in Fig. 21.
  • the digital polarity changing circuit comprises eight Ex-OR gates 162-1 to 162-8.
  • the construction shown in Fig. 21 is the construction in which the video digital signal data has eight bits, that is, the digital data for one pixel has an 8-bit width.
  • a polarity change signal PC is applied from a control circuit 141 to one input of each of the Ex-OR gates 162-1 to 162-8.
  • the Ex-OR gates output a signal of high (H) level if the bit values of both inputs thereof are not coincident, and output a signal of low L) level if the bit values of both inputs are coincident.
  • each of the Ex-OR gates 162-1 to 162-8 permits the input video digital signal data to pass therethrough and if the polarity change signal PC is of H level, each of the gates inverts the bit value of the video digital data supplied thereto and outputs the inverted value.
  • the levels of the polarity change signal PC are changed dependent on the first 1/2 horizontal period and the second 1/2 horizontal period as shown in Fig. 22. In other words, a cycle of the polarity change signal PC is one horizontal period. Accordingly, the polarities of the signals are different by 180° dependent on the first 1/2 horizontal period and the second 1/2 horizontal period.
  • the signal polarities can be inverted for the odd-numbered gate lines and the even-numbered gate lines and signal switching in the high speed line sequential system can be attained.
  • the signal having passed through the polarity changing circuits 127, 128 is one train of digital video data.
  • the digital signal data train is transmitted to the latch circuits 129 to 134 formed by the D-flip-flops, where it is latched with different timings and converted to parallel three trains of digital video signal data corresponding to the respective colors R, G, B.
  • Fig. 23 shows a latch circuit 163 formed by a D-flip-flop for latching the B signal, a latch circuit 164 formed by a D-flip-flop for latching the R signal, and a latch circuit 165 formed by a D-flip-flop for latching the G signal.
  • the latch circuits 163 to 165 include A/D converters 166 to 168, respectively, for converting the outputs therefrom to analog signals.
  • the latch circuit 163 carries out latch operation in response to a latch control signal LB
  • the latch circuit 164 carries out latch operation in response to a latch control signal LR
  • the latch circuit 165 carries out latch operation in response to a latch control signal LG.
  • Those control signals LB, LR, LG form clock signals of three phases different and not overlapping with each other and the cycle of each of the control signals LB, LR, LG has a cycle three times longer than that of the line memory clock ⁇ 2.
  • the composite data train outputted from the data polarity changing circuit is in the order of R, B, G, R ... as shown in Fig. 24 b).
  • the latch circuit 164 carries out latch operation in response to the control signal LR and subsequently the latch circuits 165 and 163 carry out latch operation in this order. Since each of the latch circuits 163 to 165 carries out latch operation for three line memory clocks ⁇ 2, the data maintaining period of each of the latch circuits 163 to 165 is a period of three line memory clocks ⁇ 2.
  • the output signals of the respective D/A converters 135 to 140 (166 to 168) are transmitted to the corresponding source drivers 143 to 146. Among the source drivers 143 to 146 shown in Fig.
  • the source drivers 143 and 145 connected to the source lines of the first half operate in response to the same clock and the source drivers 144 and 146 connected to the source lines of the second half operate in the same clock. Accordingly, as for the odd-numbered source lines, the source drivers for the second half and the source drivers for the first half accept data alternately, and similarly the source drivers 145 and 146 connected to the even-numbered source lines accept data alternately.
  • each of the cycles of the clocks ⁇ 4, ⁇ 4 for the source drivers has a cycle twice larger than that of the line memory clock ⁇ 2 and each of the source drivers can operate with the same operation speed as that in the double speed line sequential system or the interlace system. More specifically, referring to Figs.
  • the source driver for driving the source lines of the second half operates and samples the R signal (R321) and then the source driver for driving the source lines of the first half operates and samples the B signal (B1). subsequently, the signals G323, R3, B325, G5 are sampled successively. This sampling operation is carried out by successively turning on the analog switches 150 (150-1 to 150-m) included in the respective source drivers.
  • the three signal lines are arranged in parallel and connected to the analog switches sequentiallv and, consequently, only the video signal corresponding to one of the three outputs is sampled in the analog sample-and-hold circuit 151.
  • the analog sample-and-hold circuit 151 transmits the data to the corresponding source line after completion of all of the sample-and-holding operations for the signals supplied thereto in connection with one gate line.
  • the manner of division of the areas of the display panel and the number of source drivers are not limited to those in the above described embodiments.
  • the liquid crystal panel can be driven only by one line memory circuit for the three colors and accordingly it is possible to provide an inexpensive liquid crystal drive device having a simplified structure with low consumption of power.
  • At least a pair of memories are used so that video data is written in one of the memories and is read from the other memory, and the read video data is transmitted alternately to the source drivers for driving the first half of the liquid crystal panel and to the source drivers for driving the second half thereof. Accordingly, it is possible to obtain a liquid crystal drive device having excellent linearity, which drives the liquid crystal panel at high speed in an equivalent manner even if it operates with low speed clocks.
  • the memory region is divided into areas for the even-numbered gate lines, the odd-numbered gate lines, the odd-numbered source lines, the even-numbered source lines, the source lines of the first half and the source lines of the second half, and color video data converted to a data train is stored in each of the areas and is read successively according to a prescribed order.
  • the liquid crystal panel in the high speed line sequential system can be driven while the source drivers for driving the liquid crystal panel is operated with the same speed as that in the conventional double speed line sequential system or the conventional interlace system.

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Claims (24)

  1. Verfahren zum Betreiben einer Anzeigevorrichtung (32; 147) mit einer Matrix von Farbpixeln (148), die so angeordnet sind, daß sie über jeweilige Treiberleitungen (S) angesteuert werden, wobei die Treiberleitungen in eine erste und eine zweite Gruppe von Treiberleitungen unterteilt sind, dadurch gekennzeichnet, daß parallele Signale (VB, VR, VG), die jeweilige Farbkomponenten eines anzuzeigenden Bilds repräsentieren, in serielle Daten umgesetzt werden, die Daten in einen Speicher (43, 44; 118, 119, 120, 121) eingespeichert werden, die Daten der Reihe nach aus dem Speicher ausgelesen werden und die aufeinanderfolgend gelesenen Daten abwechselnd an die erste und zweite Treiberleitungsgruppe gegeben werden.
  2. Verfahren nach Anspruch 1, bei dem die Treiberleitungen mehrere Sourceleitungen, von denen jede mit Farbpixeln einer Spalte verbunden ist, aufweist und die Anzeigevorrichtung (32) über mehrere Gateleitungen verfügt, von denen jede mit den Farbpixeln einer Zeile verbunden ist, wobei ein erster (33) und ein zweiter (35) Sourcetreiber zum Ansteuern einer ersten Hälfte bzw. einer zweiten Hälfte ungeradzahliger Sourceleitungen sowie ein dritter (34) und vierter (36) Sourcetreiber zum Ansteuern einer ersten bzw. zweiten Hälfte geradzahliger Sourceleitungen am Umfang der Anzeigetafel (32) vorhanden sind, wobei der Schritt des Umsetzens paralleler Signale in serielle Daten folgendes umfaßt
    - Erzeugen eines ersten digitalen Datensignalzugs für die ungeradzahligen Sourceleitungen sowie eines zweiten digitalen Datensignalzugs (Fig. 7(1)) für die geradzahligen Sourceleitungen, wenn zunächst diese parallelen Farbsignale (VB, VR, VG) empfangen werden, die drei analoge Farbsignale umfassen, wobei der erste digitale Datensignalzug digitale Farbsignale für die drei Farben umfaßt, die in der Farbreihenfolge der ungeradzahligen Sourceleitungen angeordnet sind, und der zweite digitale Datensignalzug digitale Farbsignale der drei Farben umfaßt, die in der Farbreihenfolge der geradzahligen Sourceleitungen angeordnet sind;
    - wobei der Einspeicherschritt folgendes umfaßt,
    - Einschreiben des ersten und des zweiten digitalen Datensignalzugs in ein erstes bzw. zweites Speicherelement des Speichers (43, 44) abhängig von einer Adressenreihenfolge, wobei das erste und das zweite Speicherelement jeweils zu einem Adressenbereich einer ersten Hälfte bzw. einem Adressenbereich einer zweiten Hälfte gehören;
    - wobei zum Leseschritt das abwechselnde Lesen des Bereichs der ersten Hälfte und des Bereichs der zweiten Hälfte aus jeweils den ersten und zweiten Speicherelementen und das Erzeugen eines dritten digitalen Datensignalzugs und eines vierten digitalen Datensignalzugs umfaßt;
    - und der Anlegeschritt das Umsetzen des dritten und vierten digitalen Datensignalzugs in zweite und dritte analoge Farbsignale (VB, VR, VG) der drei Farben auf parallele Weise, das Übertragen der zweiten analogen Farbsignale an den ersten und zweiten Sourcetreiber und das Übertragen der dritten analogen Farbsignale an den dritten und vierten Sourcetreiber umfaßt; und
    - der erste und der zweite Sourcetreiber abwechselnd aktiviert werden, und der dritte und der vierte Sourcetreiber abwechselnd aktiviert werden, um dadurch das zweite Analogsignal im ersten und zweiten Sourcetreiber und das dritte analoge Farbsignal im dritten und vierten Sourcetreiber zu halten.
  3. Verfahren nach Anspruch 1, bei dem die Farbpixel (148) mit einer Dreiecksanordnung angeordnet sind, die Anzeigevorrichtung (147) mehrere Gateleitungen (g) beinhaltet, von denen jede mit den Pixeln einer Zeile verbunden ist und die Treiberleitungen mehrere Sourceleitungen (S) zum Übertragen von Signalen an die mehreren Pixel umfaßt, wobei die Anzeigevorrichtung an ihrem Umfang einen ersten Sourcetreiber (143) zum Ansteuern der Sourceleitungen einer ersten Hälfte der ungeradzahligen Sourceleitungen, einen zweiten Sourcetreiber (144) zum Ansteuern der Sourceleitungen einer zweiten Hälfte der ungeradzahligen Sourceleitungen, einen dritten Sourcetreiber (145) zum Ansteuern der Sourceleitungen einer zweiten Hälfte der geradzahligen Sourceleitungen sowie einen vierten Sourcetreiber (146) zum Ansteuern der Sourceleitungen einer zweiten Hälfte der geradzahligen Sourceleitungen beinhaltet, wobei die Pixel derselben Farbe mit einer Sourceleitung verbunden sind, und wobei der Umsetzungsschritt folgendes umfaßt:
    - Umsetzen der ersten parallelen Farbsignale, die drei analoge Farbsignale (VB, VR, VG) umfassen, zum Erstellen eines ersten digitalen Datensignalzugs (Fig. 18(b)) von Farbsignalen, die an die Pixel einer ersten Gateleitung zu übertragen sind, und eines zweiten digitalen Datensignalzugs (Fig. 18(c)) von Farbsignalen, die an die Pixel einer zweiten Gateleitung zu übertragen sind, die mit der ersten Gateleitung ein Paar bildet, wobei der erste digitale Datensignalzug und der zweite digitale Datensignalzug verschiedene Phasen entsprechend 1,5 Pixeln aufweisen und wobei der erste und der zweite digitale Datensignalzug digitale Farbsignale der drei Farben umfassen, die in derselben Reihenfolge angeordnet sind, wie es der Farbreihenfolge der Pixel entlang einer Gateleitung entspricht; und
    - die Differenz der Phasen zwischen dem ersten und dem zweiten digitalen Datensignalzug so korrigiert wird, daß die Differenz einem Pixel entspricht;
    - wobei ein dritter digitaler Datensignalzug (Fig. 18(g)), der an die ungeradzahligen Sourceleitungen zu übertragen ist, erzeugt wird, und ein vierter digitaler Datensignalzug (Fig. 18(h)) von Farbsignalen, die an die geradzahligen Sourceleitungen unter den ersten und zweiten digitalen Datensignalzügen mit den korrigieren Phasen erzeugt werden, wobei der dritte und vierte digitale Datensignalzug solche Datensignalzüge umfassen, in denen die Daten für die erste Gateleitung und die Daten für die zweite Gateleitung abwechselnd angeordnet sind, wobei der dritte digitale Datensignalzug einen digitalen Farbsignalzug umfaßt, der mit einer Reihenfolge angeordnet ist, die der Farbreihenfolge der ungeradzahligen Sourceleitungen folgt, und der vierte digitale Datensignalzug einen digitalen Farbsignalzug umfaßt, der in einer Reihenfolge angeordnet ist, die der Farbreihenfolge der geradzahligen Sourceleitungen folgt; und
    - wobei die Phase des dritten digitalen Datensignalzugs und diejenige des vierten digitalen Signalszugs miteinander übereinfallen; wobei der Einspeicherungsschritt folgendes umfaßt:
    - Einschreiben des dritten digitalen Datensignalzugs in ein erstes Speicherelement (118, 120) und des vierten digitalen Datensignalzugs in ein zweites Speicherelement (119, 121) des Speichers, wobei das erste und das zweite Speicherelement einen ersten (A₁), einen zweiten (A₂), einen dritten (A₃) und einen vierten (A₄) Speicherbereich gemäß einer Adressenreihenfolge aufweisen, wobei der Einschreibschritt die Schritte des Einschreibens der zugeführten digitalen Daten auf abwechselnde Weise in den ersten und dritten Speicherbereich des ersten und zweiten Speicherelements in einer ersten Halbperiode einer Horizontalabrasterperiode (Fig. 19(a)) und das Einschreiben der zugeführten Daten auf abwechselnde Weise in den zweiten und vierten Speicherbereich in der zweiten Halbperiode der einen Horizontalabrasterperiode (Fig. 19B(b)) umfaßt;
    - wobei der Leseschritt das Lesen der Daten aus dem ersten Speicherelement zum Erzeugen eines fünften digitalen Datenzugs (Fig. 20A(c)) und gleichzeitiges Lesen der Daten aus dem zweiten Speicherelement zum Erzeugen eines sechsten digitalen Datensignalzugs (Fig. 20A(d)) umfaßt, wobei der Leseschritt die Schritte des Lesens der Daten auf abwechselnde Weise aus dem ersten und zweiten Speicherbereich des ersten und zweiten Speicherelements in der ersten Halbperiode der einen Horizontalabrasterperiode (Fig. 20B(a)) und des Lesens der Daten auf abwechselnde Weise aus dem dritten und vierten Speicherbereich derselben in der zweite Halbperiode der einen horizontalen Abrasterperiode (Fig. 20B(b)) umfaßt, wobei der fünfte digitale Datensignalzug einen digitalen Farbsignalzug der drei Farben umfaßt, die in einer Reihenfolge angeordnet sind, die der Farbreihenfolge der ungeradzahligen Sourceleitungen folgen, und der sechste digitale Datensignalzug einen digitalen Farbsignalzug der drei Farben beinhaltet, die mit einer Reihenfolge angeordnet sind, die der Farbreihenfolge der geradzahligen Sourceleitungen folgt; und der Anlegeschritt folgendes umfaßt:
    - Erstellen eines zweiten analogen Farbsignals mit drei Farbsignalen (VB, VR, VG) in paralleler Weise aus dem sechsten digitalen Datensignalzug und Übertragen desselben an den dritten und vierten Sourcetreiber, wobei der Schritt zum Erstellen des zweiten analogen Farbsignals einen Schritt des sukzessiven und perioden Aktivierens dreier Latcheinrichtungen (163, 164, 165) beinhaltet, die parallel angeordnet sind, um gleichzeitig den fünften digitalen Datensignalzug aufzunehmen, und wobei der Schritt zum Erstellen des dritten analogen Farbsignals einen Schritt des sukzessiven periodischen Aktivierens weiterer drei parallel angeordneter Latcheinrichtungen (163, 164, 165) umfaßt, um den sechsten digitalen Datensignalzug gleichzeitig aufzunehmen; und
    - der erste und der zweite Sourcetreiber abwechselnd aktiviert werden, um das zweite analoge Farbsignal aufrechtzuerhalten, und der dritte und der vierte Sourcetreiber abwechselnd aktiviert werden, um das dritte analoge Farbsignal aufrechtzuerhalten, wobei zwei benachbarte Gateleitungen innerhalb einer Horizontalabrasterperiode aktiviert werden.
  4. Verfahren nach Anspruch 3, ferner mit dem Schritt des Invertierens der Polaritäten des ersten und sechsten digitalen Datensignalzugs (Fig. 20A(c), (d)) in solcher Weise, daß die Polaritäten der Daten in der ersten Halbperiode und der zweiten Halbperiode der einen horizontalen Abrasterperiode in umgekehrter Beziehung stehen (Fig. 22).
  5. Verfahren nach einem der vorstehenden Ansprüche, bei dem die Anzeigevorrichtung (32; 147) eine Flüssigkristall-Farbanzeigevorrichtung ist.
  6. Vorrichtung zum Betreiben einer Anzeigevorrichtung (32; 147) mit einer Matrix von Farbpixeln (148), die so angeordnet sind, daß sie durch jeweilige Treiberleitungen (S) angesteuert werden, wobei die Treiberleitungen in eine erste und eine zweite Treiberleitungsgruppe unterteilt sind, gekennzeichnet durch:
    - eine Einrichtung (39, 40; 101 bis 116, 107 bis 112, 113) zum Umsetzen paralleler Signale (VB, VR, VG), die jeweilige Farbkomponenten eines anzuzeigenden Bilds repräsentieren, in serielle Daten;
    - eine Einrichtung (43, 44, 49, 50; 118 bis 121, 122, 123) zum Einspeichern der seriellen Daten;
    - eine Einrichtung (45, 49, 51, 52; 122; 124, 125, 126) zum Lesen der Daten der Reihe nach aus der Speichereinrichtung; und
    - eine Einrichtung (46, 47, 33 bis 36, 129 bis 134, 135 bis 140, 143 bis 146) zum abwechselnden Zuführen der gelesenen Daten an die erste und die zweite Treiberleitungsgruppe.
  7. Vorrichtung nach Anspruch 6, bei der die Farbpixel in der Matrix von Zeilen und Spalten gemäß einer vorgegebenen Farbreihenfolge angeordnet sind und die Treiberleitungen mehrere Sourceleitungen umfassen, von denen jede mit einer Spalte von Farbpixeln derselben Farbe verbunden ist, wobei die mehreren Sourceleitungen in mindestens eine erste und eine zweite Gruppe unterteilt sind, wobei die erste und die zweite Gruppe jeweils in eine erste und eine zweite Untergruppe weiter unterteilt ist, wobei die Einrichtung zum Anlegen des Lesesignals an die Treiberleitungen folgendes umfaßt:
    - eine Einrichtung zum Übertragen eines Signals an jede der mehreren Sourceleitungen, wobei die Signalübertragungseinrichtung eine erste Sourcetreibereinrichtung (33, 35) und eine zweite Sourcetreibereinrichtung (34, 36) umfaßt, die so vorhanden sind, daß sie der ersten bzw. zweiten Gruppe von Sourceleitungen entsprechen, und wobei die erste und die zweite Sourcetreibereinrichtung jeweils einen ersten Treiber (33, 34) entsprechend der ersten Untergruppe sowie einen zweiten Treiber (35, 36) entsprechend der zweiten Untergruppe beinhalten, wobei der erste Treiber und der zweite Treiber abwechselnd aktiviert werden, um ein ihnen jeweils zugeführtes Farbsignal einzuspeichern;
    - wobei die Vorrichtung eine erste Signalzuführeinrichtung (37) und eine zweite Signalzuführeinrichtung (38) zum Zuführen von Farbsignalen zu den entsprechenden Sourcetreibereinrichtungen aufweist;
    - wobei die erste und die zweite Signalzuführeinrichtung jeweils folgendes beinhaltet
    - zunächst die Umsetzeinrichtung (39b, 39r, 39g, 40b, 40r, 40g, 41, 42) zum Empfangen der parallelen Farbsignale, die Analogsignale sind, und zum Umsetzen derselben in einen digitalen Datensignalzug mit einer Farbreihenfolge, die der Farbreihenfolge entspricht, wie sie durch die Sourceleitungen der entsprechenden Gruppe festgelegt ist;
    - die Speichereinrichtung (43, 44, 49, 50) zum aufeinanderfolgenden Einspeichern des Ausgangssignals der Umsetzeinrichtung gemäß einer Adresse, wobei die Speichereinrichtung einen ersten Bereich zum Einspeichern von an die erste Untergruppe zu übertragenden Daten sowie einen zweiten Speicherbereich zum Einspeichern von an die zweite Untergruppe zu übertragenden Daten beinhaltet;
    - die Einrichtung (49, 51) zum aufeinanderfolgenden Lesen der abgespeicherten Daten aus der Speichereinrichtung, wobei die Leseeinrichtung eine Leseeinrichtung für abwechselndes Lesen beinhaltet, um die Daten abwechselnd aus dem ersten Bereich und dem zweiten Bereich auszulesen; und
    - eine Analogumsetzeinrichtung (46b, 46r, 46g, 47b, 47r, 47g, l1b, l1r, l1g) zum Umsetzen eines von der Leseeinrichtung gelesenen Datensignalzugs in analoge Signale und zum Übertragen derselben an die zugehörige Sourcetreibereinrichtung, wobei diese Analogumsetzeinrichtung eine zweite Umsetzeinrichtung (46b, 46r, 46g, 47b, 47r, 47g, l1b, l1r, l1g) zum Umsetzen des gelesenen Datensignalzugs in parallele, analoge Farbsignale und zum Ausgeben derselben beinhaltet.
  8. Vorrichtung nach Anspruch 7, bei der die mehreren Sourceleitungen ungeradzahlige Sourceleitungen, die die erste Gruppe bilden, und geradzahlige Sourceleitungen, die die zweite Gruppe bilden, umfassen und sie Sourceleitungen einer ersten Hälfte, die jede der ersten Untergruppen bilden, und Sourceleitungen einer zweiten Hälfte, die jede der zweiten Untergruppen bilden, umfassen,
    - wobei die Leseeinrichtung für abwechselndes Lesen eine Einrichtung (51, 49) zum abwechselnden Lesen von Daten aus dem zweiten Bereich und dem ersten Bereich der Speichereinrichtung beinhaltet.
  9. Vorrichtung nach einem der Ansprüche 7 oder 8, bei der die Speichereinrichtung mindestens einen ersten (43) und einen zweiten (44) Speicher umfaßt, von denen jeder eine Kapazität aufweist, die dazu ausreicht, die an eine Pixelzeile zu übertragenden Daten einzuspeichern, wobei die Vorrichtung ferner folgendes aufweist,
    - eine Einrichtung (45, 52) zum Steuern des Betriebs der Speichereinrichtung zum Auslesen von Daten aus dem ersten oder zweiten Speicher, während Daten in den anderen Speicher eingeschrieben werden.
  10. Vorrichtung nach einem der Ansprüche 7 bis 9, bei der die erste Umsetzeinrichtung folgendes beinhaltet:
    - mehrere A/D-Umsetzeinrichtungen (39b, 39r, 39g) entsprechend den mehreren Arten analoger Farbsignale, wie sie jeweils parallel geliefert werden, um die entsprechenden analogen Farbsignale in digitale Signale umzusetzen;
    - mehrere Puffereinrichtungen (40b, 40r, 40g) zum Aufnehmen der Ausgangssignale der entsprechenden A/D-Umsetzeinrichtungen mit vorgegebener zeitlicher Lage, und zum Ausgeben derselben, wobei die mehreren Puffereinrichtungen sequentiell und periodisch abhängig von einer Reihenfolge aktiviert werden, die der Farbreihenfolge der Sourceleitungen der entsprechenden Gruppen folgen; und
    - eine Einrichtung (41, 42) zum Empfangen der Ausgangssignale der mehreren Puffereinrichtungen, zum Umsetzen derselben in einen digitalen Datensignalzug und zum Liefern des Datensignalzugs an die Speichereinrichtung.
  11. Vorrichtung nach einem der Ansprüche 7 bis 10, bei der die zweite Speichereinrichtung folgendes beinhaltet
    - mehrere Latcheinrichtungen (46b, 46r, 46g), die parallel vorhanden sind, um die von der Leseeinrichtung gelesenen digitalen Daten mit verschiedenen zeitlichen Lagen einzuspeichern, wobei die mehreren Latcheinrichtungen Einrichtungen zum Ausgeben der mehreren Arten von Farbsignalen auf parallele Weise sind, und sie sukzessiv und periodisch gemäß der Reihenfolge der Aufnahme der Farbsignale durch die zugehörige Sourcetreibereinrichtung aktiviert werden, um die zugeführten Daten einzuspeichern und auszugeben;
    - D/A-Umsetzeinrichtungen (47b, 47r, 47g) zum Umsetzen der Ausgangssignale der entsprechenden Latcheinrichtung in Analogsignale; und
    - Einrichtungen (l1b, l1r, l1g) zum Übertragen der Ausgangssignale der zugehörigen D/A-Umsetzereinrichtung auf parallele Weise an eine zugeordnete Sourcetreibereinrichtung.
  12. Vorrichtung nach Anspruch 6, bei der die Farbpixel gemäß einer vorgegebenen Farbreihenfolge anordnet sind und die Treiberleitungen mehrere Sourceleitungen (S) zum Übertragen von Signalpotentialen an die mehreren Pixel umfassen, wobei die Vorrichtung folgendes beinhaltet: mehrere Gateleitungen (g), die in einer die mehreren Sourceleitungen schneidenden Richtung vorhanden sind, zum Übertragen eines Signals, das eine Zeile der mehreren Pixel aktiviert, wobei an eine Sourceleitung Pixel derselben Farbe angeschlossen sind und wobei den mehreren Sourceleitungen Zahlen zugeordnet sind, die fortlaufend ansteigen, so daß die mehreren Sourceleitungen in eine Gruppe ungeradzahliger Sourceleitungen, eine Gruppe geradzahliger Sourceleitungen, eine Gruppe von Sourceleitungen einer ersten Hälfte und eine Gruppe von Sourceleitungen einer zweiten Hälfte unterteilt sind, wobei die Einrichtung zum Anlegen von Lesedaten an die Treiberleitungen, folgendes umfaßt:
    - eine erste und eine zweite Sourcetreibereinrichtung (143, 144, 145, 146) entsprechend der Gruppe ungeradzahliger Sourceleitungen bzw. der Gruppe geradzahliger Sourceleitungen, wobei die erste und die zweite Sourcetreibereinrichtung jeweils einen ersten Sourcetreiber (143, 145) zum Übertragen eines Signals an die Sourceleitungen der ersten Hälfte sowie einen zweiten Sourcetreiber (144, 146) zum Übertragen eines Signals an die Sourceleitungen der zweiten Hälfte beinhaltet, die abwechselnd aktiviert werden, und wobei die erste und die zweite Sourcetreibereinrichtung jeweils eine Einrichtung (149, 150, 151) zum Zwischenspeichern von ihnen zugeführten Signalen mit einer Reihenfolge, die der Reihenfolge der Farbanordnung der entsprechenden Sourceleitungsgruppen entspricht, und zum Übertragen der eingespeicherten Signale an die Sourceleitungen der entsprechenden Gruppen mit vorgegebener zeitlicher Lage umfaßt, wobei die Umsetzeinrichtung folgendes beinhaltet
    - eine Einrichtung (101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113) zum Empfangen eines analogen Videosignals, das einer Zeile der mehreren Pixel entspricht, und zum Erzeugen eines digitalen Datensignalzugs, der in den Pixeln darzustellen ist, die mit der ersten Zeile und einer zweiten Zeile, die mit der ersten Zeile ein Paar bildet, verbunden sind, wobei die Erzeugung ausgehend von dem für eine Zeile empfangenen Videosignal erfolgt, das die parallelen Videosignale (VB, VR, VG) der drei Farben beinhaltet, wobei die Speicherungeinrichtung folgendes umfaßt
    - eine Einrichtung (114, 115, 116, 117, 118, 120, 121, 123, 141) zum Empfangen des Ausgangssignals der Erzeugung, die den Datensignalzug erzeugt, und zum Abspeichern der empfangenen Videosignaldaten durch Unterteilen derselben in Gruppen von Signaldaten, die an die erste Zeile, die zweite Zeile, die Gruppe ungeradzahliger Sourceleitungen, die Gruppe geradzahliger Sourceleitungen, die Gruppe von Sourceleitungen der ersten Hälfte und die Gruppe der Sourceleitungen der zweiten Hälfte zu übertragen sind;
    - wobei die Leseeinrichtung eine Einrichtung (124, 141) zum seriellen Lesen der an die Pixel der ersten Zeile unter den in der Speichereinrichtung abgespeicherten Daten mit vorgegebener Reihenfolge, mit anschließendem seriellem Lesen der an die Pixel der zweiten Zeile mit der vorgegebenen Reihenfolge zu übertragenden Daten aufweist; und
    - die Vorrichtung ferner eine Einrichtung (129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140) zum Zwischenspeichern des von der Leseeinrichtung gelieferten Datensignalzugs mit vorgegebener zeitlicher Lage, zum Umsetzen derselben in parallele, analoge Farbsignale und zum Übertragen dieser Farbsignale an die erste und die zweite Sourcetreibereinrichtung aufweist, wobei die Übertragungseinrichtung eine erste Latchumsetzeinrichtung zum Zwischenspeichern der an die ungeradzahligen Sourceleitungen zu übertragenden Daten innerhalb des gelesenen Datensignalzugs und zum Umsetzen derselben sowie eine zweite Latchumsetzeinrichtung zum Zwischenspeichern der an die geradzahligen Sourceleitungen zu übertragenden Daten und zum Umsetzen derselben beinhaltet.
  13. Vorrichtung nach Anspruch 12, bei der die Anzeigevorrichtung Farbfilter mit Dreiecksanordnung umfaßt, wobei die Pixel der jeweilig benachbarten Gateleitungen um 1,5 Pixel versetzt sind, wobei die Einrichtung zum Erzeugen des digitalen Datensignalzugs folgendes aufweist:
    - eine erste Erzeugungseinrichtung (101, 102, 103, 107, 108, 109) zum Empfangen der drei verschiedenen Farbsignale auf parallele Weise und zum Erzeugen der an die Pixel der ersten Gateleitung in Form des digitalen Signalzugs zu übertragenden Farbsignale, wobei diese erste Erzeugungseinrichtung eine Einrichtung (107, 108, 109) zum Erzeugen serieller digitaler Daten, die den drei verschiedenen Farbsignalen entsprechen, mit einer Reihenfolge, die der Farbreihenfolge der an die erste Gateleitung angeschlossenen Pixel entsprechen, beinhaltet, und
    - eine zweite Erzeugungseinrichtung (104, 105, 106, 110, 111, 112) beinhaltet, die mit einer zeitlichen Lage komplementär zur Aktivierung der ersten Erzeugungseinrichtung aktiviert wird, um einen digitalen Datensignalzug zu erzeugen, der eine Anordnung der drei Farbsignale mit derselben Reihenfolge hat, wie es die Farbreihenfolge der an die zweite Gateleitung angeschlossenen Pixel entspricht.
  14. Vorrichtung nach Anspruch 13, bei der die Einrichtung zum Erzeugen des digitalen Datensignalzugs ferner folgendes aufweist:
    - eine erste Datensignalzug-Umsetzeinrichtung (158, 160, 161) zum Empfangen der Ausgangssignale der ersten und der zweiten Erzeugungseinrichtung und zum Erzeugen eines ersten Datensignalzugs, der aus digitalen Daten besteht, wie sie an die ungeradzahligen Sourceleitungen zu übertragen sind, und eine zweite Datensignalzug-Umsetzeinrichtung (159, 160) zum Erzeugen eines zweiten Datensignalzugs aus digitalen Daten, wie sie an die geradzahligen Sourceleitungen zu übertragen sind;
    - wobei der erste und der zweite Datensignalzug jeweils einen Datensignalzug beinhaltet, in dem die an die Pixel der ersten Gateleitung zu übertragenden Daten und die an die Pixel der zweiten Gateleitung zu übertragenden Daten abwechselnd angeordnet sind.
  15. Vorrichtung nach einem der Ansprüche 13 oder 14, bei der die erste Erzeugungseinrichtung folgendes aufweist:
    - eine erste, zweite und dritte A/D-Umsetzeinrichtung (101, 102, 103; 152, 153, 154), die entsprechend den parallelen, analogen Farbsignalen für die drei Farben vorhanden sind, um die entsprechenden Farbsignale auf Taktsignale hin in digitale Signale umzusetzen;
    - eine erste bis dritte Puffereinrichtung (107, 108, 109), jeweils entsprechend der ersten bis dritten A/D-Umsetzeinrichtung, um die Ausgangssignale der zugeordneten A/D-Umsetzeinrichtung selektiv hindurchzulassen, wobei die erste bis dritte Puffereinrichtung sukzessive und periodisch aktiviert werden, um dadurch einen digitalen Datensignalzug zu erzeugen, der mit einer Reihenfolge angeordnet ist, die der Farbreihenfolge der Pixel dieser ersten Zeile folgt;
    - eine vierte, fünfte und sechste A/D-Umsetzeinrichtung (104, 105, 106), die jeweils den parallelen, analogen Farbsignalen der drei Farben entsprechen, um die entsprechenden Farbsignale auf invertierte Signale der Taktsignale hin in digitale Signale umzusetzen; und
    - eine vierte, fünfte und sechste Puffereinrichtung (110, 111, 112), jeweils entsprechend der vierten bis sechsten A/D-Umsetzeinrichtung, um die Ausgangssignale der entsprechenden A/D-Umsetzeinrichtung selektiv hindurchzulassen, wobei die vierte bis sechste Puffereinrichtung sukzessive und periodisch aktiviert werden, um dadurch einen digitalen Farb-Datensignalzug zu erzeugen, der mit einer Reihenfolge angeordnet ist, die der Farbreihenfolge der Pixel der zweiten Gateleitung folgt; und wobei der digitale Datensignalzug von der ersten bis dritten Puffereinrichtung mit einer zeitlichen Lage erzeugt wird, die sich um 1,5 Pixelperioden gegenüber der des digitalen Datensignalzugs von der vierten bis sechsten Puffereinrichtung unterscheidet.
  16. Vorrichtung nach Anspruch 13, bei der der digitale Datensignalzug von der ersten Erzeugungseinrichtung eine Phase aufweist, die um 1,5 Pixel gegenüber der des digitalen Datensignalzugs von der zweiten Erzeugungseinrichtung voreilt, wobei die Einrichtung zum Erzeugen des digitalen Datensignalzugs ferner folgendes aufweist:
    - eine erste Latcheinrichtung (158) zum Einspeichern und Ausgeben des digitalen Signalzugs von der ersten Erzeugungseinrichtung auf ein Taktsignal hin;
    - eine zweite Latcheinrichtung (159) zum Einspeichern und Ausgeben des digitalen Datensignalzugs von der zweiten Erzeugungseinrichtung auf das Taktsignal hin;
    - eine Signalzug-Umsetzeinrichtung (160), die die Ausgangssignale der ersten und der zweiten Erzeugungseinrichtung erhält, die jeweiligen Ausgangssignale der ersten und der zweiten Erzeugungseinrichtung auf ein Auswahlsignal hin austauscht und einen Datensignalzug erzeugt, der aus Daten besteht, wie sie an die ungeradzahligen Sourceleitungen zu übertragen sind, und einen Datensignalzug, der an die geradzahligen Sourceleitungen zu übertragen ist; und
    - eine dritte Latcheinrichtung (161) zum Einspeichern und Ausgeben des digitalen Datensignalzugs für die ungeradzahligen Sourceleitungen von der Signalzug-Umsetzeinrichtung auf das Taktsignal hin.
  17. Vorrichtung nach Anspruch 14, bei der die Speichereinrichtung folgendes aufweist:
    - eine erste Speichereinrichtung (118, 120) zum Einspeichern digitaler Daten für die ungeradzahligen Sourceleitungen, wobei diese erste Speichereinrichtung einen Speicherbereich für eine erste Hälfte und einen Speicherbereich für eine zweite Hälfte aufweist;
    - eine zweite Speichereinrichtung (119, 121) zum Einspeichern digitaler Daten für die geradzahligen Sourceleitungen, wobei die zweite Speichereinrichtung einen zweiten Speicherbereich für eine erste Hälfte und einen Speicherbereich für eine zweite Hälfte aufweist;
    - eine erste Schreibeinrichtung (122, 123, 144) zum abwechselnden Einschreiben des Ausgangssignals der ersten Datensignalzug-Umsetzeinrichtung in den Speicherbereich der ersten Hälfte (A) und den Speicherbereich der zweiten Hälfte (B) der ersten Speichereinrichtung; und
    - eine zweite Schreibeinrichtung (122, 123, 141) zum abwechselnden Einschreiben des Ausgangssignals der zweiten Datensignalzug-Umsetzeinrichtung in den Speicherbereich der ersten Hälfte und den Speicherbereich der zweiten Hälfte der der zweiten Speichereinrichtung;
    - wobei die erste und die zweite Schreibeinrichtung gemeinsam eine Einrichtung (123) zum Erzeugen einer Adresse aufweisen, die das Ziel für in die entsprechende Speichereinrichtung einzuschreibende Daten spezifiziert, und zum Einschreiben der Daten in die entsprechende Speichereinrichtung gemäß derselben Adresse, wie sie gleichzeitig von der Schreibadressen-Erzeugungseinrichtung geliefert wird.
  18. Vorrichtung nach Anspruch 17, bei der jeder der Speicherbereiche der ersten Hälfte (A) und der zweiten Hälfte (B) jeder der ersten und zweiten Speichereinrichtungen weiter in einen ersten (A₁, B₁) und einen zweiten (A₂, B₂) Unterspeicherbereich unterteilt ist und
       - die Schreibadressen-Erzeugungseinrichtung (123) Adressen so erzeugt, daß Daten abwechselnd in den ersten Unterspeicherbereich (A₁) des Speicherbereichs der ersten Hälfte und in den ersten Unterspeicherbereich (B₁) des Speicherbereichs der zweiten Hälfte eingeschrieben werden, und zwar innerhalb einer Periode der ersten Hälfte einer Horiontalabrasterperiode, in der eine Gateleitung aktiviert ist, und sie die Adresse so erzeugt, daß die Daten abwechselnd in den zweiten Unterspeicherbereich (A₂) des Speicherbereichs der ersten Hälfte und den zweiten Unterspeicherbereich (B₂) des Speicherbereichs der zweiten Hälfte eingeschrieben werden, was in einer Periode der zweiten Hälfte der einen horizontalen Abrasterperiode erfolgt.
  19. Vorrichtung nach einem der Ansprüche 13 bis 16, bei der die Leseeinrichtung folgendes aufweist:
    - eine erste Leseeinrichtung (118, 120, 124, 141) zum abwechselnden Lesen von an die Sourceleitungen der ersten Hälfte der ungeradzahligen Sourceleitungsgruppe der ersten Zeile zu übertragenden Daten und der an die Sourceleitungen der zweiten Hälfte der ungeradzahligen Sourceleitungsgruppe der ersten Zeile zu übertragenden Daten aus der Speichereinrichtung, und zum abwechselnden Lesen, nach dem Lesen der Daten für die erste Zeile, der an die Sourceleitungen der ersten Hälfte der ungeradzahligen Sourceleitungsgruppe der zweiten Zeile zu übertragenden Daten und der an die Sourceleitungen der zweiten Hälfte der ungeradzahligen Sourceleigungsgruppe der zweiten Zeile zu übertragenden Daten; und
    - eine zweite Leseeinrichtung (119, 121, 124, 141) zum abwechselnden Lesen von an die Sourceleitungen der ersten Hälfte der geradzahligen Sourceleitungsgruppe der ersten Zeile zu übertragenden Daten und der an die Sourceleitungen der zweiten Hälfte der geradzahligen Sourceleitungsgruppe der ersten Zeile zu übertragenden Daten aus der Speichereinrichtung, und zum abwechselnden Lesen, nach dem Lesen der Daten für die erste Zeile, der an die Sourceleitungen der ersten Hälfte der geradzahligen Sourceleitungsgruppe der zweiten Zeile zu übertragenden Daten und der an die Sourceleitungen der zweiten Hälfte der geradzahligen Sourceleitungsgruppe der zweiten Zeile zu übertragenden Daten,
    - wobei die von der ersten und zweiten Leseeinrichtung gelesenen Datensignalzüge dieselbe Farbreihenfolge aufweisen, wie es der Farbreihenfolge der Pixel der entsprechenden Gateleitungen entspricht.
  20. Vorrichtung nach Anspruch 18, bei der die Leseeinrichtung folgendes aufweist:
    - eine erste Leseeinrichtung (124, 141) zum Lesen von Daten aus der ersten Speichereinrichtung (118, 120), wobei diese erste Leseeinrichtung abwechselnd Daten des ersten Unterbereichs (A₁) des Speicherbereichs der ersten Hälfte der ersten Speichereinrichtung und Daten des zweiten Unterbereichs (A₂) derselben in der ersten Halbperiode der einen Horizontalperiode liest, und sie abwechselnd Daten des ersten Unterbereichs (B₁) des Bereichs der zweiten Hälfte der ersten Speichereinrichtung sowie Daten des zweiten Unterbereichs (B₂) derselben in der zweiten Halbperiode der einen Horizontalperiode liest; und
    - eine zweite Leseeinrichtung (124, 141) zum aufeinanderfolgenden Lesen von Daten aus der ersten Speichereinrichtung (119, 121), wobei die zweite Leseeinrichtung abwechselnd Daten des ersten (A₁′) und des zweiten (A₂′) Unterspeicherbereichs des Speicherbereichs der ersten Hälfte der zweiten Speichereinrichtung in der ersten Halbperiode der einen Horizontalperiode liest, und sie abwechselnd Daten des ersten (B₁′) und des zweiten (B₂′) Unterspeicherbereichs des Speicherbereichs der zweiten Hälfte der zweiten Speichereinrichtung in der zweiten Halbperiode der einen Horizontalperiode liest;
    - wobei die erste und die zweite Leseeinrichtung eine Leseadressen-Erzeugungseinrichtung (124) gemeinsam haben und
    - die erste und die zweite Leseeinrichtung die Daten mit derselben zeitlichen Lage entsprechend derselben Adresse von der Leseadressen-Erzeugungseinrichtung lesen.
  21. Vorrichtung nach einem der Ansprüche 12 bis 20, ferner mit einer Einrichtung (127, 128) zum Aufnehmen des Datensignalzugs von der Leseeinrichtung und zum Umkehren der Polarität der Daten jedesmal dann, wenn sie Pixeldaten für eine Gateleitung aufgenommen hat.
  22. Vorrichtung nach Anspruch 21, bei der die Umkehrungseinrichtung Einrichtungen (161-1 bis 161-8) zum Invertieren jedes Bitwerts der empfangenen Daten aufweist.
  23. Vorrichtung nach Anspruch 20, bei der die Einrichtung zum Übertragen des Signals an die Sourcetreibereinrichtung folgendes aufweist:
    - eine erste, zweite und dritte Latcheinrichtung (129, 130, 131), die parallel zueinander geschaltet sind, um das Ausgangssignal der ersten Leseeinrichtung (118, 120) mit unterschiedlichen zeitlichen Lagen einzuspeichern und auszugeben, wobei die erste bis dritte Latcheinrichtung sukzessive und periodisch aktiviert werden, um das zugeführte Signal abhängig von der Farbreihenfolge der Sourceleitungen einzuspeichern, die von der ersten Sourcetreibereinrichtung (143, 144) angesteuert werden;
    - eine erste, zweite und dritte D/A-Umsetzeinrichtung (135, 136, 137) zum Umsetzen der Ausgangssignale der entsprechenden Latcheinrichtung in analoge Signale und zum Übertragen derselben auf parallele Weise an die erste Sourcetreibereinrichtung;
    - eine vierte, fünfte und sechste Latcheinrichtung (132, 133, 134), die parallel zueinander vorhanden sind, um das Ausgangssignal der zweiten Datenleseeinrichtung (119, 121) mit verschiedenen zeitlichen Lagen einzuspeichern und auszugeben, wobei die vierte bis sechste Latcheinrichtung sukzessive und periodisch aktiviert werden, um die zugeführten Daten gemäß der Farbreihenfolge der geradzahligen Sourceleitungen einzuspeichern; und
    - eine vierte, fünfte und sechste D/A-Umsetzeinrichtung (138, 139, 140) zum Umsetzen der Ausgangssignale der entsprechenden Latcheinrichtung in analoge Signale und zum Übertragen derselben auf parallele Weise an die zweite sourcetreibereinrichtung (145, 146).
  24. Vorrichtung nach einem der Ansprüche 12 bis 16, bei der die Speichereinrichtung folgendes aufweist:
    - ein erstes Paar Speicherelemente (118, 119) zum Einspeichern von Daten für die Gruppe der ungeradzahligen Sourceleitungen und Daten für die Gruppe der geradzahligen Sourceleitungen, und
    - ein zweites Paar Speicherelemente (120, 121), in denen ein Datenlesevorgang ausgeführt wird, wenn im ersten Paar Speicherelemente ein Datenschreibvorgang ausgeführt wird, wobei der Datenschreibvorgang dann ausgeführt wird, wenn im ersten Paar Speicherelemente ein Datenlesevorgang ausgeführt wird.
EP89311397A 1988-11-05 1989-11-03 Steuereinrichtung und -verfahren für eine Flüssigkristallanzeigetafel Expired - Lifetime EP0368572B1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP63280029A JPH02126285A (ja) 1988-11-05 1988-11-05 液晶駆動回路
JP280029/88 1988-11-05
JP326472/88 1988-12-23
JP63326472A JPH02170784A (ja) 1988-12-23 1988-12-23 液晶パネルを駆動するためのラインメモリ回路

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EP0368572A2 EP0368572A2 (de) 1990-05-16
EP0368572A3 EP0368572A3 (de) 1991-08-14
EP0368572B1 true EP0368572B1 (de) 1995-08-02

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KR900008434A (ko) 1990-06-04
DE68923683T2 (de) 1996-02-15
DE68923683D1 (de) 1995-09-07
EP0368572A2 (de) 1990-05-16
KR920009029B1 (ko) 1992-10-12

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