EP0315422A3 - Dispositif semi-conducteur de mémoire comprenant un contact chimique entre une métallisation en alliage aluminium-silicium et un substrat en silicium - Google Patents

Dispositif semi-conducteur de mémoire comprenant un contact chimique entre une métallisation en alliage aluminium-silicium et un substrat en silicium Download PDF

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Publication number
EP0315422A3
EP0315422A3 EP19880310285 EP88310285A EP0315422A3 EP 0315422 A3 EP0315422 A3 EP 0315422A3 EP 19880310285 EP19880310285 EP 19880310285 EP 88310285 A EP88310285 A EP 88310285A EP 0315422 A3 EP0315422 A3 EP 0315422A3
Authority
EP
European Patent Office
Prior art keywords
aluminum
film
silicon substrate
memory device
semiconductor memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19880310285
Other languages
German (de)
English (en)
Other versions
EP0315422A2 (fr
Inventor
Taiji Ema
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of EP0315422A2 publication Critical patent/EP0315422A2/fr
Publication of EP0315422A3 publication Critical patent/EP0315422A3/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Electrodes Of Semiconductors (AREA)
EP19880310285 1987-11-05 1988-11-02 Dispositif semi-conducteur de mémoire comprenant un contact chimique entre une métallisation en alliage aluminium-silicium et un substrat en silicium Withdrawn EP0315422A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP278286/87 1987-11-05
JP62278286A JP2548957B2 (ja) 1987-11-05 1987-11-05 半導体記憶装置の製造方法

Publications (2)

Publication Number Publication Date
EP0315422A2 EP0315422A2 (fr) 1989-05-10
EP0315422A3 true EP0315422A3 (fr) 1990-11-14

Family

ID=17595230

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19880310285 Withdrawn EP0315422A3 (fr) 1987-11-05 1988-11-02 Dispositif semi-conducteur de mémoire comprenant un contact chimique entre une métallisation en alliage aluminium-silicium et un substrat en silicium

Country Status (4)

Country Link
US (1) US4931845A (fr)
EP (1) EP0315422A3 (fr)
JP (1) JP2548957B2 (fr)
KR (1) KR920007447B1 (fr)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5247197A (en) * 1987-11-05 1993-09-21 Fujitsu Limited Dynamic random access memory device having improved contact hole structures
KR920010695B1 (ko) * 1989-05-19 1992-12-12 삼성전자 주식회사 디램셀 및 그 제조방법
JP2623019B2 (ja) * 1990-03-13 1997-06-25 三菱電機株式会社 半導体装置
US5281838A (en) * 1990-03-13 1994-01-25 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having contact between wiring layer and impurity region
DE4143506C2 (de) * 1990-04-27 1997-01-23 Mitsubishi Electric Corp Dram
US5276344A (en) * 1990-04-27 1994-01-04 Mitsubishi Denki Kabushiki Kaisha Field effect transistor having impurity regions of different depths and manufacturing method thereof
DE4143389C2 (de) * 1990-04-27 1994-11-24 Mitsubishi Electric Corp Verfahren zum Herstellen eines DRAM
JP2524862B2 (ja) * 1990-05-01 1996-08-14 三菱電機株式会社 半導体記憶装置およびその製造方法
JPH0449654A (ja) * 1990-06-19 1992-02-19 Nec Corp 半導体メモリ
GB2252667A (en) * 1990-10-08 1992-08-12 Gold Star Electronics Contact in DRAM device
NL9100039A (nl) * 1991-01-11 1992-08-03 Philips Nv Halfgeleiderinrichting en werkwijze voor het vervaardigen van de halfgeleiderinrichting.
JPH0575061A (ja) * 1991-09-13 1993-03-26 Oki Electric Ind Co Ltd 半導体記憶装置の配線構造
JPH05110005A (ja) * 1991-10-16 1993-04-30 N M B Semiconductor:Kk Ｍｏｓ型トランジスタ半導体装置およびその製造方法
KR960005248B1 (ko) * 1991-10-24 1996-04-23 마쯔시다덴기산교 가부시기가이샤 반도체기억장치 및 그 제조방법
JP2748070B2 (ja) * 1992-05-20 1998-05-06 三菱電機株式会社 半導体装置およびその製造方法
JP3413876B2 (ja) * 1992-07-08 2003-06-09 セイコーエプソン株式会社 半導体装置
JP3013624B2 (ja) * 1992-09-01 2000-02-28 日本電気株式会社 半導体集積回路装置
KR960006693B1 (ko) * 1992-11-24 1996-05-22 현대전자산업주식회사 고집적 반도체 접속장치 및 그 제조방법
US5545926A (en) * 1993-10-12 1996-08-13 Kabushiki Kaisha Toshiba Integrated mosfet device with low resistance peripheral diffusion region contacts and low PN-junction failure memory diffusion contacts
US6057604A (en) * 1993-12-17 2000-05-02 Stmicroelectronics, Inc. Integrated circuit contact structure having gate electrode protection for self-aligned contacts with zero enclosure
JP3326267B2 (ja) * 1994-03-01 2002-09-17 三菱電機株式会社 半導体装置およびその製造方法
US6025264A (en) * 1998-02-09 2000-02-15 United Microelectronics Corp. Fabricating method of a barrier layer
KR100553682B1 (ko) * 2003-03-07 2006-02-24 삼성전자주식회사 게이트 전극을 갖는 반도체 소자 및 그 형성방법
US7205665B1 (en) * 2005-10-03 2007-04-17 Neah Power Systems, Inc. Porous silicon undercut etching deterrent masks and related methods

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4042953A (en) * 1973-08-01 1977-08-16 Micro Power Systems, Inc. High temperature refractory metal contact assembly and multiple layer interconnect structure
JPS5893347A (ja) * 1981-11-30 1983-06-03 Toshiba Corp Ｍｏｓ型半導体装置及びその製造方法
US4569122A (en) * 1983-03-09 1986-02-11 Advanced Micro Devices, Inc. Method of forming a low resistance quasi-buried contact
JPS6066465A (ja) * 1983-09-21 1985-04-16 Seiko Epson Corp 半導体装置
JPS6079746A (ja) * 1983-10-07 1985-05-07 Hitachi Ltd 半導体装置及びその機能変更方法
JPH0763060B2 (ja) * 1984-03-15 1995-07-05 松下電器産業株式会社 半導体装置の製造方法
JPH0789569B2 (ja) * 1986-03-26 1995-09-27 株式会社日立製作所 半導体集積回路装置及びその製造方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. SC-19, no. 5, October 1984, pages 596-602, IEEE, New York, US; D. KANTZ et al.: "A 256K DRAM with descrambled redundancy test capability" *
THIN SOLID FILMS, vol. 120, no. 4, October 1984, pges 257-266, Elsevier Sequoia, Lausanne, CH; F. NEPPL et al.: "A TaSix barrier for low resistivity and high reliability of contacts to shallow diffusion regions in silicon" *

Also Published As

Publication number Publication date
JPH01120863A (ja) 1989-05-12
US4931845A (en) 1990-06-05
KR890008947A (ko) 1989-07-13
JP2548957B2 (ja) 1996-10-30
EP0315422A2 (fr) 1989-05-10
KR920007447B1 (en) 1992-09-01

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