EP0236767B1 - Dispositif de commande - Google Patents

Dispositif de commande Download PDF

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Publication number
EP0236767B1
EP0236767B1 EP87101880A EP87101880A EP0236767B1 EP 0236767 B1 EP0236767 B1 EP 0236767B1 EP 87101880 A EP87101880 A EP 87101880A EP 87101880 A EP87101880 A EP 87101880A EP 0236767 B1 EP0236767 B1 EP 0236767B1
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EP
European Patent Office
Prior art keywords
signal
switching
circuit
electrodes
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
EP87101880A
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German (de)
English (en)
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EP0236767A2 (fr
EP0236767A3 (en
Inventor
Hiroshi Inoue
Yoshiyuki Osada
Yutaka Inaba
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Canon Inc
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Canon Inc
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Priority claimed from JP2815186A external-priority patent/JPS62186229A/ja
Priority claimed from JP3473086A external-priority patent/JPS62191832A/ja
Application filed by Canon Inc filed Critical Canon Inc
Publication of EP0236767A2 publication Critical patent/EP0236767A2/fr
Publication of EP0236767A3 publication Critical patent/EP0236767A3/en
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Publication of EP0236767B1 publication Critical patent/EP0236767B1/fr
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
    • G09G3/3629—Control of matrices with row and column drivers using a passive matrix using liquid crystals having memory effects, e.g. ferroelectric liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3692—Details of drivers for data electrodes suitable for passive matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display

Definitions

  • the present invention relates to a driving apparatus for driving an optical modulation device wherein the contrast is discriminated depending on an applied electric field, particularly a ferroelectric liquid crystal device.
  • liquid crystal device having bistability In order to overcome the drawbacks of the prior art liquid crystal devices, the use of a liquid crystal device having bistability has been proposed. Since ferroelectric liquid crystals having chiral smectic C-phase (SmC*) or H-phase (SmH*) have bistability, these liquid crystals are generally used. In detail these liquid crystals have bistable states of first and second stable states with respect to an electric field applied thereto. In contrast to optical modulation devices in which the above-mentioned TN-type liquid crystals are used, the bistable liquid crystal molecules are oriented to first and second optically stable states with respect to the electric field vectors of the electric field applied thereto.
  • SmC* chiral smectic C-phase
  • SmH* H-phase
  • liquid crystals of this type are such that they are oriented to one of two stable states at an extremely high speed and that the states are maintained if no electric field is supplied thereto.
  • these liquid crystals having chiral smectic phase can essentially improve a large number of problems involved in the prior art devices as described above.
  • switching may be effected by selectively applying a voltage signal of a positive polarity or a voltage signal of a negative polarity to individual pixels as disclosed in British Patent Specification GB-A2141279.
  • a driving apparatus which is adapted for driving an optical modulation device to which a writing scheme using different polarity driving voltage signals inclusive of a positive polarity signal and a negative polarity signal is applied comprising a scanning driver circuit connected to scanning electrodes and a signal driver circuit connected to signal electrodes. That is, writing signals applied to signal electrodes include both a positive polarity signal and a negative polarity signal in a single scanning phase.
  • a driving circuit for a ferroelectric liquid crystal device generally requires a complicated circuit structure when compared with a driving circuit for a conventional TN (twisted nematic) type liquid crystal device, so that it requires a large number of driver ICs (integrated circuits) and also a large number of connecting points between the ICs and the ferroelectric liquid crystal device.
  • driver ICs integrated circuits
  • connecting points between the ICs and the ferroelectric liquid crystal device is liable to be expensive.
  • An object of the present invention is to provide a driving apparatus having solved the above mentioned problems, particularly a driving apparatus with a simple circuit structure adapted for a ferroelectric liquid crystal device.
  • a driving apparatus adapted for driving an optical modulation device having scanning electrodes and signal electrodes and to which a writing scheme using different polarity driving voltage signals inclusive of a positive polarity signal and a negative polarity signal is applied, the driving apparatus comprising: a scanning driver circuit having outputs connectable to said scanning electrodes and a signal driver circuit having outputs connectable to said signal electrodes; characterized in that said signal driver circuit comprises: a drive signal generating unit which includes a first and a second signal generating circuit for generating a first and a second voltage signal, respectively, of waveforms of the same shape and of mutually opposite polarity; a switching circuit unit for selectively supplying said first or second voltage signal to each of said signal electrodes; and a switching signal generating unit for supplying a switching control signal to said switching circuit unit in dependence of an image signal.
  • An optical modulation material used in an optical modulation device to which the present invention may be suitably applied may be a material capable of providing a discriminatable contrast by showing at least a first optically stable state (assumed to provide, e.g., a "bright” state) and a second optically stable state (assumed to provide, e.g., a "dark” state) depending on an electric field applied thereto, preferably a material showing bistability in response to an applied electric field, and particularly a liquid crystal showing such properties.
  • Preferable liquid crystals having bistability which can be used in a driving apparatus according to the present invention are smectic, particularly chiral smectic, liquid crystals having ferroelectricity.
  • chiral smectic C (SmC*)-, H (SmH*)-, I (SmI*)-, F (SmF*)- or G (SmC*)-phase liquid crystals are suitable therefor.
  • ferroelectric liquid crystal compound used in the apparatus according to the present invention are decyloxybenzylidene-p'-amino-2-methylbutyl-cinnamate (DOBAMBC), hexyloxybenzylidene-p'-amino-2-chloropropylcinnamate (HOBACPC), 4-o-(2-methyl)-butylresorcylidene-4'-octylaniline (MBRA8), etc.
  • DOBAMBC decyloxybenzylidene-p'-amino-2-methylbutyl-cinnamate
  • HOBACPC hexyloxybenzylidene-p'-amino-2-chloropropylcinnamate
  • MBRA8 4-o-(2-methyl)-butylresorcylidene-4'-octylaniline
  • the device When a device is constituted by using these materials, the device may be supported with a block of copper, etc., in which a heater is embedded in order to realize a temperature condition where the liquid crystal compounds assume an SmC*-, SmH*-, SmI*-, SmF*- or SmG*-phase.
  • FIG. 13 there is schematically shown an example, of a ferroelectric liquid crystal cell.
  • the reference numerals 131a and 131b denote substrates (glass plates) on which a transparent electrode of, e.g., In2O3, SnO2, ITO (Indium Tin Oxide), etc., is disposed, respectively.
  • a liquid crystal of an SmC*-phase in which liquid crystal molecular layers 132 are oriented perpendicular to the surfaces of the glass plates is hermetically disposed therebetween.
  • a full line 133 shows liquid crystal molecules.
  • Each liquid crystal molecule 133 has a dipole moment (P ⁇ ) 132 in a direction perpendicular to the axis thereof.
  • P ⁇ dipole moment
  • each of the liquid crystal molecules 133 has an elongated shape and shows refractive anisotropy between the long axis and the short axis thereof.
  • the liquid crystal cell when, for instance, polarizers arranged in a cross nicol relationship, i.e., with their polarizing directions being crossing each other are disposed on the upper and the lower surfaces of the glass plates, the liquid crystal cell thus arranged functions as a liquid crystal optical modulation device of which optical characteristics vary depending upon the polarity of an applied voltage.
  • the thickness of the liquid crystal cell is sufficiently thin (e.g., 1 micron)
  • the helical structure of the liquid crystal molecules is unwound without application of an electric field whereby the dipole moment assumes either of the two states, i.e., Pa in an upper direction 144a or Pb in a lower direction 144b as shown in Figure 14.
  • the dipole moment is directed either in the upper direction 144a or in the lower direction 144b depending on the vector of the electric field Ea or Eb.
  • the liquid crystal molecules are oriented in either of a first stable state 143a (bright state) and a second stable state 143b (dark state).
  • the response speed is quite fast.
  • the orientation of the liquid crystal shows bistability.
  • the second advantage will be further explained, e.g., with reference to Figure 14.
  • the electric field Ea is applied to the liquid crystal molecules, they are oriented to the first stable state 143a. This state is stably retained even if the electric field Ea is removed.
  • the electric field Eb having a direction opposite to the direction of the electric field Ea is applied thereto, the liquid crystal molecules are oriented to the second stable state 143b, whereby the directions of molecules are changed. Likewise, the latter state is stably retained even if the electric field Eb is removed.
  • the liquid crystal molecules are placed in the respective orientation states.
  • the thickness of the cell is as thin as possible and generally 0.5 to 20 microns, particularly 1 to 5 microns.
  • FIG 1 is a block diagram of a driving apparatus for a ferroelectric liquid crystal device (hereinafter, the term “ferroelectric liquid crystal” is sometimes abbreviated as "FLC"). More specifically, a driving unit for an FLC panel 11 comprises a scanning driver circuit 12 and a signal driver circuit 13. The scanning driver circuit 12 supplies scanning signals S1, S2, ..., and the signal driver circuit 13 supplies data signals D1, D2, ..., respectively as shown in Figure 3. The addresses of the scanning driver circuit 12 and the signal driver circuit 13 are respectively determined by an address decoder 14. Further, column data 16 are governed by a CPU 15 and supplied to the signal driver circuit 13.
  • FLC ferroelectric liquid crystal
  • Figure 2 is a schematic plan view of a panel 21 having a matrix electrode comprising a number ( m ) of scanning electrodes 22 (S1, ... Sm) and a number ( n ) of signal electrodes 33 (D1, ... Dn) with a ferroelectric liquid crystal (not shown) as an optical modulation material sandwiched therebetween.
  • the scanning electrodes 22 are sequentially selected in the order of S1, S2, S3, ..., Sm. Further, when a scanning electrode is selected, the signal electrodes 23 (D1, ..., Dn) are respectively supplied with signals corresponding to image data.
  • Figure 3 shows an example of signals applied to electrodes S1, S2, D1 and D2 for providing a display state as shown in Figure 2 wherein a pixel at an S1-D1 is displayed in "black” (denoted by “B” in the figure) based on the second stable state of the ferroelectric liquid crystal, a pixel at an S1-D2 intersection is displayed in "white” (denoted by "W” in the figure) based on the first stable state of the ferroelectric liquid crystal, and a pixels at S2-D1 and S2-D2 intersections are both displayed in "black”.
  • a black signal B and a white signal W are selectively applied to pixels on a selected scanning line S1 at phase 2 to write in the pixels on the scanning line S1.
  • a voltage of 3V exceeding the first threshold voltage V th1 is applied to all the pixels on the scanning line S1, whereby all the pixels are written in "white” based on the first stable state of the FLC.
  • a pixel supplied with a black signal B is supplied with a voltage of -3V exceeding the second threshold voltage V th2 to be inverted into "black” based on the second stable state of the FLC, while a pixel supplied with a white signal W is supplied with a voltage of -V not exceeding the second threshold voltage V th2 to retain the "white" display state resultant in the phase 1 as it is.
  • the signals of ⁇ V applied at phase 3 are signals which do not change the display states of the pixels written at the phase 2 and are used to prevent a crosstalk phenomenon which is caused by a data signal continuously applied to one pixel, e.g., in a case where a white signal W is continuously applied to one pixel through a signal electrode.
  • the signal applied at phase 3 is preferably one of a polarity which is opposite to the polarity of the signal applied at phase 2 with respect to a reference potential.
  • the written states of one line of pixels are determined at the above mentioned phase 2, and by sequentially repeating the operation of phases 1-2-3 including the phase 2 row by row, writing of one whole picture is effected.
  • the voltage value V is set to satisfy the following relations with the first threshold voltage V th1 for providing the first stable state (white) of the FLC and the second threshold voltage V th2 for providing the second stable state (black) of the FLC, i.e., 3V>V th1 >V and -3V ⁇ V th2 ⁇ -V.
  • the "white” signal W (-V) and the “black” signal B (+V) with polarities different from each other are selectively applied to the signal electrodes 23 in a single scanning signal phase, i.e., phase 2.
  • the signal of +V and the signal of -V applied selectively to the signal electrodes at phase 2 are respectively referred to as a "black” signal and a "white” signal.
  • FIG. 4 is a block diagram of a driving apparatus for generating the above mentioned data signals D1, D2, ...
  • the driving apparatus is provided with a drive signal generating unit 41 for generating a "white” signal W and a “black” signal B, a switching signal generating unit 42 for generating a timing signal for selecting either one of the white signal and the black signal depending on given data, and a switching circuit unit 43 for selecting a signal on a "white” bus 414 or a "black” bus 413 as a data signal.
  • the drive signal generating unit 41 includes a "black” signal generating unit 411 for generating a "black” signal waveform (A) shown at (A) in Figure 7 and a “white” signal generating unit 412 for generating a “white” signal waveform (F) shown at (F) in Figure 7, which units are connected to the "black” bus 413 and the “white” bus 414, respectively.
  • the two buses 413 and 414 are respectively connected to the switching circuit unit 43.
  • Figure 5 shows more detailed arrangements of the "black” signal generating circuit 411 and the "white” signal generating circuit 412.
  • Basic clock signals from a clock 40 are supplied to a shift register 52 (LS 164) through a frequency demultiplier 51.
  • Figure 6 shows a timing chart for the circuit.
  • the switching (control) signal generating circuit 42 supplied image signals are subjected to serial ⁇ parallel conversion by means of a serial-parallel converter circuit such as a shift register 421 to provide data signals (D) for one scan line as shown at (D) in Figure 7, which signals are sent to a buffer circuit such as a transfer gate 422.
  • a serial-parallel converter circuit such as a shift register 421
  • signals are sent to a buffer circuit such as a transfer gate 422.
  • latch pulses (C) as shown at (C) in Figure 7 are applied to respective transistors Tr1 ⁇ 1, Tr1 ⁇ 2, ..., whereby the data signals (D) from the shift register 421 are stored in data holding capacitors C1, C2, ... to be uniformized with respect to time.
  • Signals (E) from the transfer gate 422 as shown in Figure 7 are respectively supplied to inverters In1, In2, ...
  • Figure 7 shows a timing chart for the above mentioned “black” signal waveform (A), "white” signal waveform (F), latch pulses (C), signals (D) from the shift register 421, signals (E) from the transfer gate 422, output signal D1 to the signal line D1, scanning signals S1, S2, ..., and basic clock signals.
  • Figure 8A shows an equivalent circuit of a signal inverter 81 functioning as one of the inverters In1, In2, ...;
  • Figure 8B is a plan view showing the layout thereof; and
  • Figure 8C illustrates the relationships between the input and output of the circuit.
  • V SS denotes 0 volt (ground state)
  • V DD denotes a power supply voltage.
  • an output signal (E) from the transfer gate 422 may be controlled by a load transistor 81 and a drive transistor 82 to provide a switching timing signal V out .
  • the load transistor 81 has a gate 811 and a source 812 which are short-circuited through a contact hole 813, and also a drain 814 which is connected to a source 82 of the drive transistor 82 through a contact hole 821.
  • the drive transistor 82 has a gate 822 to which a signal (E) is supplied, and a drain 823 connected to V SS .
  • the hatched portions in Figure 8B comprise thin film semiconductors such as amorphous silicon, polysilicon, CdSe or ZnSe.
  • Figure 9 illustrates a preferred embodiment of the shift register 421 and shows a circuit of a dynamic shift register incorporating inverters.
  • An image signal is for example supplied as an input signal.
  • Figure 10 shows a timing chart for the input signal, a clock signal ⁇ 1, a clock signal ⁇ 2, a signal at point I, a signal at point II (first stage output, corresponding to one denoted by "1st bit out"), a signal at point III, and a signal at point IV.
  • Figure 10 shows that the input pulse is shifted to a subsequent stage for each cycle of the clock signal ⁇ .
  • the clock signal ⁇ 1 corresponds to one supplied from the clock 40, and the clock signal ⁇ 2 is one obtained by inverting it.
  • a load transistor 92 and drive transistors 93, 94 and 95 in each block may comprise a thin film semiconductor such as amorphous silicon, polysilicon, CdSe, or ZnSe as a semiconductor.
  • the transistors Tr1, Tr2, ... used in the above mentioned switching circuit unit 43, the inverters In1, In2, ... used in the switching control signal generating unit 42, and the transistors in the transfer gate 422 or the shift register 421 may be composed of MOS or MIS-FET transistors, and these transistors may be formed as thin film transistors on one glass substrate by using a semiconductor material such as amorphous silicon, polysilicon, CdSe or ZnSe.
  • a display apparatus having fewer parts and fewer connections may be prepared by forming the switching circuit unit 43, the switching signal generating unit 42, the "black” bus 413 and the “white” bus 414 on a single glass substrate constituting an FLC panel 21 and combining them with the "black” signal generating circuit 411, the "white” signal generating circuit 412 and the clock 40 as external circuits.
  • the operating frequency of the shift register 421 is definitely determined by the scanning frequency (frame frequency) of the panel 21 and the number of pixels, so that a dynamic shift register having less elements and adapted for a high speed operation is preferably used than a static shift register having many elements.
  • a driving apparatus of a simple circuit structure for a device to which a writing scheme using different polarities of voltage signals such as a positive polarity signal and a negative polarity signal is applied particularly a ferroelectric liquid crystal device.
  • the number of ICs used for the driving apparatus may be decreased, and the production cost of a display apparatus may be decreased.
  • FIG 11 shows another embodiment of the driving apparatus according to the present invention.
  • the driving apparatus in Figure 11 is particularly characterized by the switching control signal generating circuit 112.
  • the switching control signal generating circuit comprises (a) a serial-parallel converter circuit and (b) a matrix circuit comprising a plurality of switching elements divided into a plurality of blocks, the switching elements in each block being commonly connected to a control line, the output signals from the serial-parallel converter circuit being distributed to the respective blocks.
  • Figure 11 is a block diagram of a driving apparatus for generating the above mentioned data signals D1, D2, ...
  • the driving apparatus comprises a drive signal generating unit 41 for generating a "white” signal W and a "black” signal B, which is substantially the same as the corresponding one in Figure 4; a switching control signal generating unit 112; and a switching circuit unit 43 for selecting as a data signal either one of signals from a "black” bus 413 and a "white” bus 414, which is substantially the same as the corresponding one in Figure 4.
  • the switching control signal generating unit 112 comprises a serial-parallel conversion circuit such as a shift register 1121 whereby input image signals are subjected to serial ⁇ parallel conversion to provide data signals (D) for one scan line as shown at (D) in Figure 7; a matrix circuit 1122 for processing the data signals in a time-sharing manner; a buffer circuit such as a transfer gate circuit for making up or putting in the output signals from the matrix circuit 1122; and inverter circuits In1, In2, ...
  • the shift register 1121 may be a dynamic shift register as explained with reference to Figure 9.
  • the clock 40 in Figure 11 is substantially the same as the clock 40 in Figure 9.
  • the matrix circuit 1122 will now be explained with reference to Figure 11, and Figure 12 showing a timing chart therefor.
  • the number of total bits on the signal side (the number of signal lines) n is 16 including D1, D2, ..., D16 and the number of divisions (number of blocks) is 4.
  • 16 bits are divided into 4 blocks (BLOCKs 1, 2, 3 and 4) each comprising 4 bits, and switching elements 1125 (1125a1-1125a4, 1125b1-1125b4, 1125c1-1125c4, and 1125d1-1125d4) are disposed corresponding to the respective bits so that they are connected in common for each block to one of control lines 1124 (1124a, 1124b, 1124c and 1124d).
  • the above mentioned switching elemens 1125 may be composed of MOS or MIS-field effect transistors, particularly thin film transistors, so that each of the control lines 1124 is commonly connected to the gates of related thin film transistors.
  • the sources of the switching transistor elements in each block are respectively connected to the output stages of the shift register 1121 so as to provide a matrix.
  • the first stage output line of the shift register 1121 is commonly connected to the transistor 1125a1 in Block 1, the transistor 1125b1 in Block 2, the transistor 1125c1 in Block 3 and the transistor 1125d1 in Block 4.
  • the second, third and fourth output lines of the shift register 1121 are connected commonly to the transistors (1125a2, 1125b2, 1125c2 and 1125d2), (1125a3, 1125b3, 1125c3 and 1125d3) and (1125a4, 1125b4, 1125c4 and 1125d4), respectively, in the respective blocks.
  • the gates of the transistors in each block are commonly connected to one of the control lines 1124a-1124d, to which gate-on pulses as shown at G1, G2, G3 and G4 in Figure 12 are sequentially applied from the terminals G1, G2, G3 and G4, respectively.
  • the drains of the switching transistors 1125 are respectively connected to the transfer gate circuit for each bit.
  • Figure 12 is a timing chart for the respective signals, based on the clock signals 40, including the outputs of the shift register 1121, the gate-on pulses G1, G2, G3 and G4 to the control lines, a latch pulse, and the logical levels of an i-1-th and i-th scanning lines.
  • "L" (low level) and "H” (high level) indicate the logical levels accompanying the switching operation during the period of selection of the i-1-th scanning line.
  • a period from the selection of the scanning line S i-1 to the selection of the subsequent scanning line Si is referred to as one horizontal scanning period (1H), and during the 1H-period, image signals for one scanning line are subjected to serial ⁇ parallel conversion and latched.
  • the outputs of the shift register 1121 are allotted as shown in Figure 12.
  • one control line G1 is turned on in order to transfer a set of parallel signals (the 1st - 4th stage output signals in the figure) into a block (Block 1 in Figure 11).
  • the subsequent control line G2 is turned on so as to transfer parallel signals from the shift register 1121 into a subsequent block.
  • the above operation is repeated until the last block (Block 4 in the figure), and thereafter a latch pulse (C) is applied to the transfer gate circuit 1123.
  • a timing signal (E) as shown at (E) supplied from the transfer gate 1123 is supplied to inverters In1, In2, ... each functioning as a control circuit for generating a switching signal. More specifically, when the signal (E) from the transfer gate 1123 is "H" (high level; indicating "1"), transistors Tr1, Tr3, ...
  • Tr 2n-1 (n: number of signal lines) in the switching circuit unit 43 are selected to supply the "white” signal waveform (F) to signal electrodes, and when the signal (E) from the transfer gate 1123 is "L" (low level; inicating "0"), transistors Tr2, Tr4, ..., Tr 2n in the switching circuit unit 43 are selected to supply a "black” signal waveform (A) to signal electrodes.
  • the time-serial waveform applied to the signal line D1 at this time is shown at D1 in Figure 7.
  • Figure 7 also shows a timing chart for the above mentioned "black” signal waveform (A), "white” signal waveform (F), latch pulses (C), signals (D) from the shift register 1121, signals (E) from the transfer gate 1123, output signal D1 to the signal line D1, scanning signals S1, S2, ..., and basic clock signals.
  • the structures and function of the inverters In1, In2, ... are substantially the same as explained with reference to Figures 8A - 8F.
  • an output signal (E) from the transfer gate 1123 may be controlled by a load transistor 81 and a drive transistor 82 as shown in Figure 8 to provide a switching timing signal V out .
  • the load transistor 81 has a gate 811 and a source 812 which are short-circuited through a contact hole 813, and also a drain 814 which is connected to a source 82 of the drive transistor 82 through a contact hole 821.
  • the drive transistor 82 has a gate 822 to which a signal (E) is supplied, and a drain 823 connected to V SS .
  • the transistors Tr1, Tr2, ... used in the above mentioned switching circuit unit 43, the switching elements 1125 used in the matrix circuit 1122, the inverters In1, In2, ... used in the switching control signal generating unit 112, and the transistors in the transfer gate 1123 or the shift register 1121 may be composed of MOS or MIS-FET transistors, and these transistors may be formed as thin film transistors on one glass substrate by using a semiconductor material such as amorphous silicon, polysilicon, CdSe or ZnSe.
  • a display apparatus having fewer parts and fewer connections may be produced by forming the switching circuit unit 43, the switching signal generating unit 112, the "black” bus 413 and the “white” bus 414 on a single glass substrate constituting an FLC panel 21 and combining them with the "black” signal generating circuit 411, the "white” signal generating circuit 412 and the clock 40 as external circuits.
  • the switching circuit 43 and the switching control signal generating unit 112 are formed on a single glass substrate and to connect them to a ferroelectric liquid crystal device by wire bonding or by using an anisotropic conductive adhesive.
  • the signal line driver circuit may be constituted by 6n x (1+1/k) switching transistors.
  • a driving apparatus of a simple circuit construction adapted for a device to which a writing scheme using different polarity voltage signals inclusive of a positive polarity signal and a negative polarity signal is applied, particularly a ferroelectric liquid crystal device.
  • the number of ICs used in the driving apparatus may be decreased, and the production cost of a display apparatus may be decreased.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Electronic Switches (AREA)

Claims (18)

  1. Appareil de commande conçu pour commander un dispositif de modulation optique ayant des électrodes de balayage et des électrodes de signaux et auquel est appliqué un arrangement d'écriture utilisant des signaux de tension de commande de polarités différentes incluant un signal de polarité positive et un signal de polarité négative, l'appareil de commande comportant
       un circuit d'attaque de balayage (12) ayant des sorties pouvant être connectées auxdites électrodes de balayage (22) et
       un circuit d'attaque de signaux (13) ayant des sorties pouvant être connectées auxdites électrodes de signaux (23) ;
       caractérisé en ce que
       ledit circuit (13) d'attaque de signaux comprend :
       une unité (41) de génération de signaux de commande qui comprend des premier (411) et second (412) circuits de génération de signaux destinés à générer des premier (A) et second (F) signaux de tension, respectivement, de formes d'ondes du même profil et de polarités mutuellement opposées :
       une unité (43) à circuit de commutation destinée à appliquer sélectivement ledit premier (A) ou second (F) signal de tension à chacune desdites électrodes (23) de signaux ; et
       une unité (42) de génération de signal de commutation destinée à fournir un signal de commande de commutation à ladite unité (43) à circuit de commutation en dépendance d'un signal d'image.
  2. Appareil selon la revendication 1, caractérisé en ce que ladite unité (42) de génération de signal de commutation comprend un circuit de conversion série-parallèle (421, 1121).
  3. Appareil selon la revendication 2, caractérisé en ce que ledit circuit de conversion série-parallèle est un registre à décalage dynamique (421).
  4. Appareil selon la revendication 2 ou 3, caractérisé en ce que ladite unité (42) de génération de signal de commutation comporte en outre un circuit (1122) à matrice qui comprend plusieurs éléments de commutation agencés en plusieurs blocs, lesdits éléments de commutation dans chaque bloc étant connectés en commun à une ligne de contrôle respective (G1, G4), les signaux de sortie dudit circuit de conversion série-parallèle (1121) étant distribués aux blocs respectifs ; et ladite unité (43) à circuit de commutation fournissant sélectivement ledit premier (A) ou second (F) signal de tension à chacune desdites électrodes de signaux (23) suivant le signal de commande de commutation fourni à partir des sorties desdits éléments de commutation de ladite unité (42) de génération de signal de commande de commutation.
  5. Appareil selon l'une des revendications 2 à 4, caractérisé en ce que ladite unité (42) de génération de signal de commutation comprend en outre un circuit tampon (422).
  6. Appareil selon la revendication 5, caractérisé en ce que ladite unité (42) de génération de signal de commutation comprend en outre un circuit d'inversion (In1, In2).
  7. Appareil selon l'une des revendications précédentes, caractérisé en ce qu'au moins l'un de ladite unité (43) à circuit de commutation, de ladite unité (42) de génération de signal de commutation, dudit registre à décalage dynamique (421) et/ou desdits éléments de commutation comprend un transistor (Tr1 - Tr4).
  8. Appareil selon la revendication 7, caractérisé en ce que ledit transistor (Tr1 - Tr4) est un transistor à effet de champ.
  9. Appareil selon la revendication 8, caractérisé en ce que ledit transistor à effet de champ est un transistor à films minces.
  10. Appareil selon la revendication 9, caractérisé en ce que ledit transistor à films minces comprend un film semiconducteur de silicium amorphe, de polysilicium, de CdSe ou de ZnSe.
  11. Appareil selon l'une des revendications précédentes, caractérisé en ce que lesdits premier (A) et second (F) signaux de tension sont fournis à leurs bus exclusifs (413, 414), respectivement, à partir de ladite unité (41) de génération de signaux de commande, les bus étant connectés à ladite unité à circuits de commutation.
  12. Appareil selon l'une des revendications 1 à 10, caractérisé en ce que ledit dispositif de modulation optique est un panneau d'affichage du type comportant des électrodes en matrice formées par lesdites électrodes de balayage (22) et lesdites électrodes de signaux (23) agencées de façon à intersecter lesdites électrodes de balayage (22), un contraste à chaque intersection desdites électrodes de balayage (22) et desdites électrodes de signaux (23) étant discriminé suivant la direction d'un champ électrique appliqué à ladite intersection.
  13. Appareil selon la revendication 12, caractérisé en ce qu'il comporte en outre un moyen de synchronisation destiné à synchroniser lesdits premier (A) et second (F) signaux de tension fournis par ledit circuit d'attaque de signaux (13) auxdites électrodes de signaux (23) avec un signal de sélection de balayage fourni par ledit circuit d'attaque de balayage (12) à une électrode de balayage (22).
  14. Appareil selon la revendication 12 ou 13, caractérisé en ce que chacun desdits premier (A) et second (F) signaux de tension comprend une tension d'une polarité positive, une tension d'une polarité négative et une tension du même niveau, respectivement, par rapport à un potentiel de référence.
  15. Appareil selon la revendication 14, caractérisé en ce que ladite tension de polarité positive et ladite tension de polarité négative ont la même amplitude.
  16. Appareil selon l'une quelconque des revendications précédentes 12 à 15, caractérisé en ce que le dispositif de modulation optique comprend un cristal liquide ferro-électrique disposé auxdites intersections desdites électrodes de balayage (22) et desdites électrodes de signaux (23).
  17. Appareil selon la revendication 16, caractérisé en ce que ledit cristal liquide ferro-électrique est un cristal liquide smectique chiral.
  18. Appareil selon la revendication 17, caractérisé en ce que ledit cristal liquide smectique chiral est disposé en une couche assez mince pour libérer la structure hélicoïdale propre audit cristal liquide smectique chiral en l'absence d'un champ électrique.
EP87101880A 1986-02-12 1987-02-11 Dispositif de commande Expired - Lifetime EP0236767B1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP28151/86 1986-02-12
JP2815186A JPS62186229A (ja) 1986-02-12 1986-02-12 駆動装置
JP34730/86 1986-02-18
JP3473086A JPS62191832A (ja) 1986-02-18 1986-02-18 駆動装置

Publications (3)

Publication Number Publication Date
EP0236767A2 EP0236767A2 (fr) 1987-09-16
EP0236767A3 EP0236767A3 (en) 1989-05-24
EP0236767B1 true EP0236767B1 (fr) 1993-05-05

Family

ID=26366197

Family Applications (1)

Application Number Title Priority Date Filing Date
EP87101880A Expired - Lifetime EP0236767B1 (fr) 1986-02-12 1987-02-11 Dispositif de commande

Country Status (4)

Country Link
US (1) US4830467A (fr)
EP (1) EP0236767B1 (fr)
DE (1) DE3785687T2 (fr)
ES (1) ES2041650T3 (fr)

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KR20140000075A (ko) * 2012-06-22 2014-01-02 삼성디스플레이 주식회사 파워 유닛 및 이를 구비하는 유기 발광 표시 장치
JP6519378B2 (ja) * 2015-07-23 2019-05-29 セイコーエプソン株式会社 データ転送回路、撮像回路装置及び電子機器
CN110246468B (zh) * 2019-06-21 2022-12-02 昆山龙腾光电股份有限公司 一种摆幅调整驱动装置
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CN102708827B (zh) * 2012-06-01 2014-08-20 矽创电子股份有限公司 扫描驱动电路

Also Published As

Publication number Publication date
DE3785687T2 (de) 1993-09-02
ES2041650T3 (es) 1993-12-01
EP0236767A2 (fr) 1987-09-16
DE3785687D1 (de) 1993-06-09
EP0236767A3 (en) 1989-05-24
US4830467A (en) 1989-05-16

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