EP0235303A1 - Systeme d'ajustement de la phase horloge - Google Patents

Systeme d'ajustement de la phase horloge Download PDF

Info

Publication number
EP0235303A1
EP0235303A1 EP86905405A EP86905405A EP0235303A1 EP 0235303 A1 EP0235303 A1 EP 0235303A1 EP 86905405 A EP86905405 A EP 86905405A EP 86905405 A EP86905405 A EP 86905405A EP 0235303 A1 EP0235303 A1 EP 0235303A1
Authority
EP
European Patent Office
Prior art keywords
scan
delay
delay means
signal
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP86905405A
Other languages
German (de)
English (en)
Other versions
EP0235303B1 (fr
EP0235303A4 (fr
Inventor
Tatsuro Yoshimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of EP0235303A1 publication Critical patent/EP0235303A1/fr
Publication of EP0235303A4 publication Critical patent/EP0235303A4/fr
Application granted granted Critical
Publication of EP0235303B1 publication Critical patent/EP0235303B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew

Definitions

  • the present invention relates to a clock phase adjusting system, especially, it relates to a system for adjusting a clock signal in an information processing system.
  • a main function of an information .processing system such as operational processing, information holding, etc., in a central processing unit (hereinafter called CPU) can be achieved by a logic circuit formed by semiconductor elements.
  • CPU central processing unit
  • This logic circuit is realized by combining many combination circuits, such as OR/NOR gates, and sequential circuits formed by registers, latches, flip-flops (hereinafter called FF) etc., by a plurality of combination circuits.
  • combination circuits such as OR/NOR gates
  • FF flip-flops
  • the above-mentinoed combination circuits can obtain an output signal only by an operation delay time in each constitution element, but in the sequence circuit, the output signal can be obtained when the input data is set by another clock signal after the input data is applied.
  • LSI large scale integration circuit
  • the large scale integration circuit provides a high integration with a low cost, and further the above-mentioned logic circuit can be realized with a uniform operational characteristic and high reliability.
  • the high speed and large scale system is, however, formed by the above-mentioned combination circuit using a large number of semiconductor elements. Therefore, because many semiconductor elements are integrated in the logic circuit, and these elements inevitably have varying operational characteristics, especially the operation time, there is an inevitable slight affect on a margin of a timing of a clock signal in the CPU, etc.
  • the clock signal of the logic circuit is obtained by distributing a plurality of clock signal having a predetermined delay time via a so-called phase adjusting circuit.
  • LSI large scale integration circuit
  • the number of gates included therein is restricted, and further, the number of external draw out terminals in a printed circuit board is also restricted.
  • the number n of the terminals of above-mentioned phase adjusting circuit is restricted, and therefore, the problem arises of a conflict in the coexistence of such a circuit in the LSI.
  • an object of the invention provides a phase adjusting system including a well known scan in/out means for easily locating a fault position in a logic circuit such as a usual LSI, etc., so that the number of the external draw out terminals for the phase adjusting is restricted to a minimum, and carrying out the work for selecting the terminals for adjusting the phase.
  • the present invention is commonly used as a scan in/out means in the logic circuit for scanning the selected data for phase adjusting, it is not especially necessary to provide a terminal for applying the select data for the phase adjusting, and thus the phase adjusting circuit can coexist with the logic circuit in the LSI.
  • a clock phase adjusting system having a high reliability can be included in the high density package without a wiring change.
  • Figures 1A and lB are diagrams showing examples of a conventional phase adjusting system.
  • Figure lA is an example of a phase adjusting circuit using an inductive line (L) and a capacitance (C), and Fig. 1B is an example of a phase adjusting circuit using OR/NOR gates.
  • phase adjusting circuits lOa - 10h shown in Fig. lA cascade delay times between each unit section of L and C are based on a constant, or a distributed constant is selected by adjusting terminals 11a ⁇ llan, ..., 111a ⁇ llhn, and CLKa ⁇ CLKh having respectively a predetermined delay time are output as the standard clock signal * CLKO to be input.
  • CLKO CLKa.
  • phase adjusting circuit 20a ⁇ 20h shown in Fig. lB cascade delay times using a plurality of OR/NOR gates are selected by adjusting terminals 21aa ⁇ 2lhn.
  • phase adjusting circuits 20a ⁇ 20h which can be easily realized are frequently used.
  • FIGS. 2A and 2B are block diagrams of the embodiments of the present invention.
  • an input means of a selected data for setting the delay time given to a basic input clock signal * CLKO is realized by a scan-in due to an address system (parallel system)
  • Figure 2B shows a system in which the input means of the selected data is realized by a scan-in due to a shift register system (series system). Note, throughout the drawings, the same symbols designate the same elements.
  • Figs. 2A and 2B show an information processing device, or an intermediate package body of the narrower function block of the information processing device, such as an assembly of a printed circuit board or the afore-mentioned LSI (hereinafter called the device).
  • the device an information processing device, or an intermediate package body of the narrower function block of the information processing device, such as an assembly of a printed circuit board or the afore-mentioned LSI (hereinafter called the device).
  • Figures 3A, 3B, and 3C are diagrams of examples of constructions of a first delay portion in Figs. 2A and 2B and of a.second delay portion connected to the first delay portion.
  • FIGs. 4A and 4B are block diagrams of other embodiments of the present invention.
  • a clock signal which is input to the * CLKO terminal of the first delay portion 1 is input to cascade m-1 OR/NOR gates 11, and each input and output signal is applied to m OR gates 12, wherein 8 OR gates.
  • the second delay portion 2 the NOR gate 14 commonly used, and the NOR gate 15 of the second delay portion 2 function to output externally, as it is, any clock signal (*CLR0 ⁇ * CLK7) delayed to eight steps of * CLKO selected by the above-mentioned PSO ⁇ . PS2, because the phase adjusting signal of the other p bits applied to the second delay portion 2, here PS10, by one bit is maintained at °0".
  • the delay means formed by inserting a capacitor Co, for example, several pF, to an emitter follower output terminal which is connected parallel to a base of the output transistor forming an emitter follower of an internal connecting element in the NOR gate 14 and 15 outputting the above-mentioned *CLR0 ⁇ * CLK7, for example, an emitter coupled logic circuit (ECL), via the NOR gate, a further delay time, for example, 0.5 step, can be inserted to the step delay signals *CLR0 ⁇ * CLK7 from the first delay portion 1.
  • a capacitor Co for example, several pF
  • the phase adjusting due to the first delay portion 1 and the second delay portion can obtain, when the delay time per one NOR gate 11 of the first delay portion 1 is set as ts, a selection clock signal (CLK1) set at every 1/2 P step in the range from a minimum 0 to a maximum (m - l/2 P ), by 4 bits of PS0 ⁇ PS2, and PS10.
  • CLK1 selection clock signal
  • a selection signal PS11 and a NOR gate 17 corresponding to the selection signal PS11 are added, one output is added for the NOR gates 14, 15, and further, the capacitance CO',.which is commonly connected to the output of the NOR gate 17, is added.
  • This capacitance CO' has a similar function to that of the.afore-mentioned capacitance C0, but the value of the capacitance is varied so that the variable step width is 0.25 step.
  • 0 ⁇ 0.75 steps can be set at a 0.25 step interval.
  • circuit such as shown in Fig. 3C can be used as the circuit of the second delay portion 2.
  • C1 ⁇ C4 are stray capacitances formed by wiring patterns, etc., in the LSI.
  • the value of these capacitance (concretely the length of the wiring pattern) is set at different values, and a signal transmission delay time (from the input of the NOR gate 18 to the input of the NOR gate 19) of the NOR gate 18 is made different by 0.25 steps, the function equivalent to the circuit shown in Fig. 3B can be obtained.
  • the selection signal for the phase adjust is set as follows. First, all latches including the address type scan in/out latch circuits 3a ⁇ 3d in the apparatus 0 are cleared to a set state (for example "1") by the set signal (SET). Next, the scan address signal (SAD) is applied to the decoder 4 and the scan in data (SI) is input to sequentially select the natural scan address (Sada m Sadd) for the latches for which the content is to be inverted (“1" ⁇ "0”), amuont the latches 3a ⁇ 3d.
  • SAD scan address signal
  • SI scan in data
  • the content of the desired latch can be inverted from “1” to "0”, and finally, any selection signal can be set in the latches 3a ⁇ 3d.
  • the above-mentioned set signal may be made a reset signal (which clears the content of the latch to zero) when using each scan in/out latch.
  • the scan in circuit is formed such that the content of the latch is inverted from “0" to "1".
  • the scan out signal (SO) carries out the input of the scan addresses Sada ⁇ Sadr of a sequential decoder 4 from all latch circuits 3a 3r to the corresponding terminals, and gathers the signals from the scan out outputs Soa ⁇ Sor by dot OR manner, to be output.
  • the latch circuits 3a m 3r cannot operate in the dot OR manner as a TTL circuit, the above-mentioned SO is output via an OR gate.
  • the controlling portion of the apparatus 0 not shown in the drawing is operated as follows.
  • the set signal (SET) is applied to all latch circuits 3a ⁇ 3r, then the scan in signal (SI) is sequentially input together with the scan address signal (SAD), so that the selection data is set in the latch circuits 3a ⁇ 3r.
  • the delay time corresponding to the selection data is selected by the first delay portion 1 and the second delay portion 2, and in the range of 0 ⁇ (m - 1/2 P ) for * CLKO, a CLK1 having a delay time of 1/2 step is sent via the OR gate 5 of the buffer function to the input terminals *CLKe ⁇ * CLKr of the other latch circuits 3e ⁇ 3r of the apparatus 0.
  • the above-mentioned SET, SI, SAD for selecting and setting the above-mentioned CLK1 can directly use the conventional scan in/out function, and thus the increase of the input/output terminals in the apparatus, 0, if the conventional SAD is more than 3 bits, corresponds to the increase of the four scan address Sada ⁇ Sadd, so that the increase of the SAD is only one bit at maximum. Then, the number of input/output terminals in the apparatus or LSI level is not largely increased, and thus apparatus can be easily combined with the LSI, and the delay time for the clock signal * CLKO can be set by the external selection signal. Therefore, a clock phase adjusting circuit having good operational characteristics can be realized.
  • the latches circuits 3a m 3d which hold the selection signal applied to the first delay portion 1 and the second delay portion 2 can be also realized by selecting from and holding the other portion, for example, the control portion.
  • phase adjusting circuit in a modified embodiment realized by the series type scan corresponding to the parallel type scan-in, by referring to Fig. 2B.
  • a scan in signal (SIa) and a scan out signal (SOa) shown in Fig. 2B are connected in series and in a ring manner with shift type scan in/out latch circuits 3aa ⁇ 3ar, together with the other shift registers included in an external control portion or controlled in the external control portion, to form a scan chain, and the above-mentioned shift registers also apply the scan clock signal (SCK) output from the scan clock generating portion under the control of another control portion to the above-mentioned scan in/out latch circuit 3aa ⁇ 3ar similarly.
  • SIa scan in signal
  • SOa scan out signal
  • the above-mentioned SIa data is incremented by one step at every one clock of the SCK, so that the above-mentioned SIa data is circulated in the scan chain by the scan clock SCK of the sum (r+s) of r number of scan in/out latch circuits 3aa ⁇ 3ar and the number of stages of the above-mentioned shift register, for example, s.
  • the data set on the shift register by the control portion is shifted by the application and the control of the scan clock (SCK), and can be set in any of the scan in/out latch circuits 3aa ⁇ 3ar on the scan chain or in the above-mentioned shift register.
  • SCK scan clock
  • the above-mentioned external control portion sets the signals corresponding to PSO ⁇ PS2, PS10, as in the afore-mentioned embodiment, in the first delay portion 1 and the second delay portion 2 and sets the above-mentioned SIa in the scan in/out latches circuits 3aa m 3ad, to input the selection data for the phase adjusting.
  • the delay time corresponding to the selection data is selected in the first delay portion 1 and the second delay portion 2, and as in the above-mentioned parallel system, in the range of 0 ⁇ (m - 1/2 P ) for * CLKO, CLK1 having any delay time of 1/2 P step is sent via the OR gate 5 of the buffer function to input terminals *CLKal ⁇ *CLKar of the other latch out circuits 3al m 3ar in the apparatus Oa.
  • system clock CLK1 used for the logic operation is not necessary, and during the logic operation using CLKl, .the scan in/out operation is not carried out, so that the phase adjust condition of the CLK1 does not vary.
  • the selection data for CKL1 must be set at a constant value each time by the scan in operation.
  • the selection data which is input as the scan in signal (SI or SIa) is processed as an image of a firmware data which is held in one portion of the control portion stored together with the control program in the memory portion belonging, for example, to an external controlling portion.
  • the selection data for the clock phase adjust special to each apparatus is stored in the apparatus, here another memory portion (hereinafter called MEM 6b, c) provided in the apparatus Ob, Oc, and, for example, at the initial set time for each apparatus, the external control portion at once sends the predetermined selection data set in MEM 6b, c in each apparatus Ob, Ob as the scan out data (SO or SOa), regardless of the selection data in each apparatus, and thereafter, the scan out data (SO, SOa) are used as the scan in data (SI, SIa), only by a predetermined process, so that the clock phase adjusting system which carries out the operation similar to the former embodiment as explained in Figs. 2A and 2B can be provided.
  • MEM 6b, c another memory portion
  • the parallel system shown in Fig. 4A is different in that the MEM 6b is added to the construction of the apparatus 0 corresponding to Fig. 2A.
  • CS chip select
  • an address signal exclusive to the MEM 6b may be used.
  • the selected data in the first delay portion 1 and the second delay portion 2 set to the latch circuits 3a N 3d in Fig. 2A are accessed to the MEM 6b to be output from the data output terminal (DO) and to be read out to an external control portion not shown in the drawing as the scan out signal (SO).
  • the data which the external controlling portion reads out by the above-mentioned SO is input as the above-mentioned SI, and the delay time according to the selected data due to above-mentioned SI is selected in * CLKO applied to the first delay portion 1 and the second delay portion 2 to output CLKl.
  • the selected data to be stored in the memory MEM 6b is stored the signal which is necessary for the write enable (We) for the MEM 6b, the data input (Di), and addresses (A0 ⁇ An) and which is output and supplied by the above-mentioned control portion.
  • the series system of Fig. 4B is different in that the MEM 6c is added to the construction of the apparatus 0 in the corresponding Fig. 2b.
  • a latch circuit 3ae in the scan chain formed as in Fig. 2B is allocated to a data input (Di), the latch circuits 3af m 3aj are allocated to the addresses (A0 ⁇ An), and the latch circuit 3ak is allocated to the data output (Do).
  • the above-mentioned external control portion not shown in the drawings executes the scan in by applying the scan clock (SCK) using the selection data as the scan in data (SIa), applies the scan in via a latch circuit 3ae to the data input (Di) of the MEM 6c and via the latch circuits 3af ⁇ 3aj to the address (A0 ⁇ An) of the MEM 6c, and the selected data is stored in the MEM 6c by applying the write enable (We).
  • the selection data stored in the MEM 6c is shifted by the above-mentioned control portion applying the scan clock (SCK) sequentially to the MEM 6c using the above-mentioned write enable as a disenable (that is read out mode), then the selection data due to the read out signal (Do) according to the address (A0 ⁇ An) supplied via the latch circuits 3af ⁇ 3aj is set in the latch circuit 3ak to be read out as the scan out signal (SOa).
  • the CLK1 signal is necessary for taking in the read out signal (Do) of the MEM 6c to the latch 3ak, however, the phase of the CLK1 signal at this time need not be adjusted.
  • a clock phase delay system can be obtained which sends out a CLK1 with a delay which is applied to the * CLKO in accordance with the predetermined selection data stored in the MEM 6c.
  • the following function may be allowed, that is, the latch circuits 3aa m 3ad and 3ae ⁇ 3ak are made valid only when operating the scan in/out for the selection data, the selection data is read out from the MEM 6c and withdrawn from the scan chain, except for setting in the first delay portion 1 and the second delay portion 2, so that the selection data in the latch circuits 3aa m 3ad is made fixed and held.
  • the characteristic feature of the clock phase adjusting system is as shown below.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Pulse Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

Un circuit logique comprenant un dispositif de balayage E/S est pourvu de n+p circuits bascules spécifiques de balayage E/S. Un premier dispositif de temporisation qui génère sélectivement des cadence d'entrée en tant que signaux de temporisation ayant m = 2n pas au maximum en fonction de signaux de sélection ayant n bits est connecté en cascade à un deuxième dispositif de temporisation qui génère sélectivement des signaux de cadence d'entrée en tant que signaux de temporisation ayant un pas minimum à 1/2p de la longueur d'un pas minimum des signaux de cadence générés par le premier dispositif de temporisation, en fonction de signaux de sélection ayant p bits. En ajustant les données de sélection par raport auxdits n+p circuits bascules de balayage E/S, on peut obtenir n'importe quel signal de temporisation retardé d'un pas donné à 1/2p par rapport au signal de cadence d'entrée.
EP86905405A 1985-09-04 1986-09-04 Systeme d'ajustement de la phase horloge Expired - Lifetime EP0235303B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP60195171A JPS6270922A (ja) 1985-09-04 1985-09-04 クロツク位相調整方式
JP195171/85 1985-09-04

Publications (3)

Publication Number Publication Date
EP0235303A1 true EP0235303A1 (fr) 1987-09-09
EP0235303A4 EP0235303A4 (fr) 1988-05-31
EP0235303B1 EP0235303B1 (fr) 1993-05-19

Family

ID=16336619

Family Applications (1)

Application Number Title Priority Date Filing Date
EP86905405A Expired - Lifetime EP0235303B1 (fr) 1985-09-04 1986-09-04 Systeme d'ajustement de la phase horloge

Country Status (8)

Country Link
US (1) US4859954A (fr)
EP (1) EP0235303B1 (fr)
JP (1) JPS6270922A (fr)
KR (1) KR900002947B1 (fr)
AU (1) AU578546B2 (fr)
BR (1) BR8606853A (fr)
DE (1) DE3688462T2 (fr)
WO (1) WO1987001479A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0535165A1 (fr) * 1990-06-08 1993-04-07 Cray Research, Inc. Procedes et appareils de repartition d'impulsions d'horloge
DE4326062C1 (de) * 1993-08-03 1994-08-18 Siemens Ag Phasenregelanordnung

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU605562B2 (en) * 1987-04-10 1991-01-17 Computervision Corporation Clock skew avoidance technique for pipeline processors
US5065041A (en) * 1989-01-05 1991-11-12 Bull Hn Information Systems Inc. Timing generator module
JPH04157379A (ja) * 1990-10-20 1992-05-29 Fujitsu Ltd 遅延測定方式
US5111086A (en) * 1990-11-19 1992-05-05 Wang Laboratories, Inc. Adjusting delay circuitry
US5382850A (en) * 1992-09-23 1995-01-17 Amdahl Corporation Selectable timing delay system
SE500929C2 (sv) * 1993-02-24 1994-10-03 Ellemtel Utvecklings Ab Signalbehandlingskrets och förfarande för fördröjning av en binär periodisk insignal
SE501190C2 (sv) * 1993-04-28 1994-12-05 Ellemtel Utvecklings Ab Digitalt styrd kristalloscillator
JP3553639B2 (ja) * 1994-05-12 2004-08-11 アジレント・テクノロジーズ・インク タイミング調整回路
US6081147A (en) * 1994-09-29 2000-06-27 Fujitsu Limited Timing controller and controlled delay circuit for controlling timing or delay time of a signal by changing phase thereof
US5981046A (en) * 1995-03-13 1999-11-09 Sumitomo Chemical Company, Limited Sound absorbing component
KR100548225B1 (ko) * 2003-12-24 2006-02-02 삼성전자주식회사 피딩 시간간격 조절 기능을 갖는 화상형성장치 및 그 방법
CN106959934B (zh) * 2017-02-21 2021-03-30 深圳市紫光同创电子有限公司 低电压差分信号接收接口及低电压差分信号接收方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2010552A (en) * 1977-12-19 1979-06-27 Ibm Clock pulse circuits
GB2050644A (en) * 1979-05-04 1981-01-07 Nissan Motor Digital control system for internal combustion engine
EP0117735A1 (fr) * 1983-02-28 1984-09-05 Deere & Company Système de commande d'ordinateur

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB201055A (en) * 1922-08-14 1923-07-26 Leich Electric Co Improvements in and relating to rotary electric ignition current distributors or timers
JPS5390834A (en) * 1977-01-21 1978-08-10 Hitachi Ltd Lsi logic circuit containig timing pulse switching circuit
US4290022A (en) * 1979-04-16 1981-09-15 General Electric Company Digitally programmable phase shifter
JPS5696526A (en) * 1979-12-28 1981-08-04 Fujitsu Ltd Timing signal generating system
JPS58218229A (ja) * 1982-06-11 1983-12-19 Fujitsu Ltd 遅延時間選定回路
JPS59158208A (ja) 1983-02-28 1984-09-07 松下電工株式会社 繊維セメント板の製法
US4580137A (en) * 1983-08-29 1986-04-01 International Business Machines Corporation LSSD-testable D-type edge-trigger-operable latch with overriding set/reset asynchronous control
US4546269A (en) * 1983-12-01 1985-10-08 Control Data Corporation Method and apparatus for optimally tuning clock signals for digital computers
US4580066A (en) * 1984-03-22 1986-04-01 Sperry Corporation Fast scan/set testable latch using two levels of series gating with two current sources
JPS60219675A (ja) * 1984-04-13 1985-11-02 Sony Corp 時間軸変換回路
US4700347A (en) * 1985-02-13 1987-10-13 Bolt Beranek And Newman Inc. Digital phase adjustment
JPH0669722A (ja) * 1992-08-18 1994-03-11 Nippon Antenna Kk マルチビームアンテナ

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2010552A (en) * 1977-12-19 1979-06-27 Ibm Clock pulse circuits
GB2050644A (en) * 1979-05-04 1981-01-07 Nissan Motor Digital control system for internal combustion engine
EP0117735A1 (fr) * 1983-02-28 1984-09-05 Deere & Company Système de commande d'ordinateur

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO8701479A1 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0535165A1 (fr) * 1990-06-08 1993-04-07 Cray Research, Inc. Procedes et appareils de repartition d'impulsions d'horloge
EP0535165A4 (en) * 1990-06-08 1994-12-07 Supercomputer Systems Ltd Clock distribution apparatus and processes
DE4326062C1 (de) * 1993-08-03 1994-08-18 Siemens Ag Phasenregelanordnung
US5471512A (en) * 1993-08-03 1995-11-28 Siemens Aktiengesellschaft Phase-locked loop configuration

Also Published As

Publication number Publication date
DE3688462D1 (de) 1993-06-24
BR8606853A (pt) 1987-11-03
DE3688462T2 (de) 1993-08-26
JPS6270922A (ja) 1987-04-01
AU578546B2 (en) 1988-10-27
EP0235303B1 (fr) 1993-05-19
KR900002947B1 (ko) 1990-05-03
US4859954A (en) 1989-08-22
KR880700351A (ko) 1988-02-22
EP0235303A4 (fr) 1988-05-31
AU6287986A (en) 1987-03-24
WO1987001479A1 (fr) 1987-03-12

Similar Documents

Publication Publication Date Title
EP0235303A1 (fr) Systeme d'ajustement de la phase horloge
KR100322721B1 (ko) 버스 내의 스큐를 경감시키는 시스템 및 방법
KR100434833B1 (ko) 직렬/병렬 변환 회로, 데이터 전송 제어 장치 및 전자 기기
USRE46754E1 (en) Integrated circuit for clock generation for memory devices
KR100416208B1 (ko) 코어 주파수의 기분수를 포함하는 주파수에서의 소스 동기전송을 위한 방법 및 장치
US6061293A (en) Synchronous interface to a self-timed memory array
KR100498473B1 (ko) 제어신호 발생회로 및 상기 제어신호 발생회로를 구비하는데이터 전송회로
KR20050061123A (ko) Ｄｄｒ ｓｄｒａｍ 콘트롤러의 데이터 제어회로
US6732305B2 (en) Test interface for verification of high speed embedded synchronous dynamic random access memory (SDRAM) circuitry
US20120249204A1 (en) Flip-flop circuit, scan test circuit, and method of controlling scan test circuit
US6351170B1 (en) Low power consumption type digital logic circuit
KR100408406B1 (ko) 복수개의 제어 신호들에 동기되어 입력된 데이터를출력하는 데이터 래치 회로를 갖는 동기식 디램 반도체 장치
US7221126B1 (en) Apparatus and method to align clocks for repeatable system testing
US4270116A (en) High speed data logical comparison device
JPH10133768A (ja) クロックシステム、半導体装置、半導体装置のテスト方法、及びｃａｄ装置
US6418176B1 (en) Forwarded clock recovery with variable latency
KR100426761B1 (ko) 반도체 집적 회로 장치
KR100318264B1 (ko) 패킷명령어 구동형 메모리소자의 로드신호 발생회로
JPH02137189A (ja) メモリ回路およびディジタル装置
US7620838B2 (en) Semiconductor integrated circuit and image processing system using the same
KR100244430B1 (ko) 반도체 칩의 테스트 회로
US6222893B1 (en) Synchronizing circuit
JPH05315900A (ja) フリップ・フロップ回路
KR20030046132A (ko) 기입 시간 손실을 감소시키는 데이터 입력버퍼 및 그 방법
US20020184468A1 (en) High speed address sequencer

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19870512

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB IT NL

A4 Supplementary search report drawn up and despatched

Effective date: 19880531

17Q First examination report despatched

Effective date: 19900904

ITF It: translation for a ep patent filed

Owner name: INTERPATENT ST.TECN. BREV.

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB IT NL

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Effective date: 19930519

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 19930528

Year of fee payment: 8

REF Corresponds to:

Ref document number: 3688462

Country of ref document: DE

Date of ref document: 19930624

ET Fr: translation filed
NLV1 Nl: lapsed or annulled due to failure to fulfill the requirements of art. 29p and 29m of the patents act
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Effective date: 19940601

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Effective date: 19950531

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 19981001

Year of fee payment: 13

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19990904

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 19990904

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED.

Effective date: 20050904