EP0229164A1 - Poste de travail a graphique en mode point. - Google Patents

Poste de travail a graphique en mode point.

Info

Publication number
EP0229164A1
EP0229164A1 EP86904601A EP86904601A EP0229164A1 EP 0229164 A1 EP0229164 A1 EP 0229164A1 EP 86904601 A EP86904601 A EP 86904601A EP 86904601 A EP86904601 A EP 86904601A EP 0229164 A1 EP0229164 A1 EP 0229164A1
Authority
EP
European Patent Office
Prior art keywords
window
screen
storing
bitmap
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP86904601A
Other languages
German (de)
English (en)
Other versions
EP0229164B1 (fr
Inventor
Rajan Netralal Kapur
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Publication of EP0229164A1 publication Critical patent/EP0229164A1/fr
Application granted granted Critical
Publication of EP0229164B1 publication Critical patent/EP0229164B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/14—Display of multiple viewports

Definitions

  • the invention relates to the generation of window borders on the displays of bitmapped graphics workstations and the like.
  • Windowing is a feature that has recently gained much popularity in the fields of * graphics workstations, personal computers, etc.
  • the screen of a display device such as a workstation monitor, is partitioned into separate rectangular areas (windows) , each of which may be assigned to view and/or control the activities of the same or different processes being carried out by an associated processor.
  • windows rectangular areas
  • a user might initiate an output printing process in one window and then activate the second window for on- 1 ine text processing while the background printing is* progressing.
  • Performance has been a problem with prior art windowing techniques as applied in the field of bitmapped graphics. Suffice it to say that the primary reason for performance problems has been the need for massive data shuffling as window data is updated. This is caused by the manner in which data is stored fcr - display in prior art techniques.
  • the prior art provides one bitmapped display memory. The states of consecutive bits of the memory reflect the on/off states of consecutive pixels of the display screen. The bit states are sequentially obtained from the memory and sent to the display device as the screen of the device is raster scanned. Thus, as scrolling is performed in one window, for example, large portions of the memory, corresponding to the position of the window on the display screen, must be continually updated.
  • border generation for windows in the prior art bitmapped techniques is relatively simple
  • the one memory contains display data for the entire display screen, all that need be done to generate visual window borders is to set the appropriate bits in the memory to an appropriate state.
  • the border data remains static in the memory as long as the position of the window on the screen is not changed.
  • the invention is window border generating circuitry in a bitmapped graphics workstation in which the workstation includes a host processor, a raster scanned ' graphics display device and means for controlling the display of data in one or more windows on the screen of the display device.
  • An individual bitmap is provided for each window.
  • Other memory is provided for storing parameters defining the screen boundaries of each window Circuitry continually identifies which, if any window is presently being refreshed on the screen.
  • display data is retrieved from one of the bitmaps associated with a window presently being refreshed. The location in the bitmaps from which the display data is obtained is determined by the window boundary definitions and by the position of the raster on the screen.
  • Circuitry for detecting when the screen raster is located at a position at which a border of a window is to be displayed. Other circuitry responds to this condition by substituting for the display data from the bitmaps predefined signals for generating the screen borders.
  • a depth indication i.e., an indication of how the windows are visually stacked with respect to each other, is stored for each window.
  • Means are provided for using the depth indications in conjunction, with raster positi.on data to determine a "winning" window if any, at each position of the screen. This determines the bitmap from which display data is obtained for each such position.
  • Access means is provided to allow the host processor to write display data into the bitmaps.
  • windows are defined by storing addresses identifying relative horizontal screen positions of the vertical boundaries of the windows and raster line numbers identifying the horizontal boundaries of the windows.
  • the individual bitmaps are illustratively contained fn a. single display memory.
  • Display memory address generating means are provided which generates an address in-, .an appropriate bitmap at any given time.
  • Border detection circuits associated with the individual windows generate border detection signals when a border area of a window with which an individual detection circuit is associated is being refreshed on the screen.
  • a left vertical border detection signal is generated as a window is entered from the left.
  • a right vertical border detection signal is generated as a window is exited on the right.
  • Horizontal border detection signals are generated as appropriate.
  • the border detection signals and bitmap data obtained for display are delayed to allow for border generation.
  • bitmap data and the horizontal and right vertical border detection signals are delayed by a first predefined time interval.
  • Left vertical border detection signals are delayed by a second time interval which is less than the first interval by at least the raster scan time required to scan the horizontal width of a vertical border on the screen.
  • Output circuits respond to the delayed border detection signals to substitute border generation data signals into the delayed bitmap data. The difference in delays of the left and right vertical border detection signals allow the output circuits to generate properly and insert into the delayed bitmap the vertical border generation signals.
  • FIG. 1 is an illustration of a display screen with two windows as they might appear in the prior art and with this invention
  • FIG. 2 is an illustration of how display data is stored in a single bitmap in the prior art
  • FIG. 3 illustrates how display data is stored in individual window bitmaps in the preferred embodiment of the present invention
  • FIG. 4 shows an illustrative individual bitmap in the present invention with the data corresponding to individual raster lines vertically stacked so as to visually resemble a display screen;
  • FIG. 5 is an illustrative block diagram of the overall graphics workstation including a window manager circuit
  • FIG. 6 is an illustrative block diagram o the window manager, including individual per window circuits and common circuits
  • FIG 7 is a simplified view of a window backlaid with illustrative bitmap data that illustrates the effect of scrolling the window and the corresponding effects on bitmap address generation
  • FIG. 8 illustrates a per window circuit that stores data defining the boundaries of a window, bitmap data for generating bitmap addresses and window depth and stipple data;
  • FIG. 9 illustrates a per window circuit for detecting when the associated window is being refreshed on the display device and related circuitry in a common interface circuit to a host precursor
  • FIG. 10 illustrates common and per window circuitry for determining which, if any, window is being refreshed on the display device
  • FIG. 11 shows an illustrative per window bitmap address generator
  • FIG. 12 shows an illustrative output control circuit as part of the common circuitry and a window border detector that identifies when a window border is being refreshed on the display device;
  • FIG. 13 illustrates an exemplary circuit for generating window background (stipple) patterns
  • FIG. 14 illustrates an exemplary output shift register circuit that generates vertical window border data and transmits this data and etched display data to the display device.
  • FIG. 1 illustrates the face of a display screen as it might appear in an implementation of the present invention.
  • the screen comprises 1024 scan lines in the vertical direction with each line made up of 80 horizontal cells.
  • each cell is the atomic unit of horizontal display in this illustrative embodiment and is composed of 16 horizontal pixels.
  • the upper left corner of the screen is assumed to have an address of line 0 and pixel
  • Processes associated with some windows may be idle, for example, while none, one or more processes associated with other windows are active.
  • a user might, for example, activate an output printing process for data associated with one window and then change to another window for interactive editing while the printing is proceeding.
  • the screen in FIG. 1 is assumed to be partitioned into two overlapping work windows Wl and W2.
  • Wl the projection of its upper-left corner onto the top scan line 0 gives a left cell coordinate COORD.L for Wl.
  • COORD.R the projection of the upper-right corner onto line 0 gives a right cell coordinate address COORD.R for Wl.
  • Parameters LINE.T and LINE.B define the respective upper and lower line addresses of the window Equivalent parameters are associated with each defined window.
  • FIG. 2 illustrates the manner in which window data is stored for the screen of FIG. 1 by the prior art.
  • Individual bits of a contiguous display memory correspond one-for-one with the sequential pixels of the screen as each line is raster scanned.
  • one contiguous segment of the memory contains -the display data for a line X (shown in FIG. 1) of the screen. Part of the data in this segment corresponds to Wl.
  • a next contiguous segment contains data for line X+l, part of which corresponds' to Wl, and so on. It is easy to see how this leads to complexities, for example, when at 200 of FIG. 2, Wl and W2 begin to overlap.
  • a scrolling of W2 has to take into account the overlapping of the windows and provide for moving "hidden" data in W2 (data that is under Wl) into and out of the display memory as scrolling proceeds.
  • FIG. 3 illustrates the manner that display data is handled in this invention.
  • a display memory is partitioned into a plurality of contiguous segments, each of which pertain to a potential window.
  • the entire memory as the display memory and the individual contiguous segments for each window as a bitmap.
  • the data in each bitmap is arranged in a fashion similar to that of FIG. 2.
  • the bitmap corresponding to Wl for example, the data to be displayed in successive lines of the window at a given time are shown in bold in FIG. 2.
  • the arrangement of FIG. 3 reduces many of the problems of data shuffling inherent in the arrangement of FIG. 2. For example, "hidden" data is maintained in the window bitmap memory and need not be relocated as scrolling proceeds.
  • each bitmap is larger than that required for the full display screen. This allows any window to be any size up to the size of the screen, or to be located anywhere on the screen and also to be scrolled horizontally and vertically .
  • ADDR.TOP The parameters ADDR.TOP, ADDR.JMP. ADDR.BASE, ADDR BTM, W. IDTH and B.WIDTH refer to addresses, actually relative addresses, in the individual bitmaps, rather than to screen addresses.
  • FIG. 4 is the bitmap for Wl in which the contiguous sections pertaining to the raster lines of a screen are stacked to give the physical appearance of a screen. This presentation of the bitmap makes it easier to envision the significance of the above parameters.
  • ADDR.BASE is the bitmap address at the beginning of the window.
  • ADDR BTM is the last address before the end of the bitmap containing data to be displayed at any given time.
  • ADDR.TOP is the bitmap address containing the next set of line data for the window after that at
  • ADDR.BTM. W. IDTH is the width of the window in cells. Each cell corresponds to 16 screen pixels.
  • B. IDTH is the width of the display screen in cells.
  • windows may or may not contain borders, as desired by a user. If a border is defined for a window the outside edges of the vertical and horizontal borders correspond to the edges of the window in this illustrative embodiment. In other words, a border is contained within its associated window
  • FIG. 7 shows a simplified 2 cell by 2 cell window backlaid with characters to illustrate how scrolling is effected in the invention.
  • the view shows characters F, G, J and K present in the windows.
  • the host processor 502 modifies the contents of ADDR.BASE by adding to it the number of raster lines assigned to one cell. This causes the window to next display the characters J, K, N and 0.
  • the window is scrolled right one cell, ADDR.BASE, ADDR TOP and ADDR.BTM must be changed. Specifically, the number of pixels in a cell is added to each of these registers.
  • FIG. 5 shows a block diagram of the overall system.
  • a window manager 500 interconnects a host processor or microprocessor 502, a display memory 504, a display screen 506 and a number of output circuits.
  • Processor 502 writes display data into the display memory 504 via address and data busses P.ADDR and P.DATA. Signals on lead INTR from window manager 500 to processor 502 tell the processor when it is okay to write.
  • processor 502 writes data into internal registers of window manager 500 to control from where display data is retrieved for each window during raster scanning of display 506.
  • Data is outputted from memory 504 on bus 508 in 64 bit words.
  • the slash in 508 indicates a multilead bus, and the number beside the slash indicates the number of leads in the bus. This notation is used throughout the disclosure.
  • An input read, address bus A.OUT extending from the window manager 500 to display memory 504, however, is only 9 bits wide, whereas 18 address bits are required to address 256K 64-bit words. Therefore, two operations are required to specify the required 18 address bits.
  • a signal on lead RAS row address signal
  • a signal on lead CAS columnumn address signal
  • a 64-bit word from display memory 504 illustratively comprises data for four 16-bit contiguous cells on the display screen.
  • the entire word is inputted into a latch 510 and the data for the individual cells metered out at appropriate times under control of a multiplexer select circuit 512.
  • Circuit 512 is, in turn, controlled by signals on an address enable lead AEN and two address select leads A0 and Al, which identify- the particular 16-bit word to, be selected from the 64-bit word.
  • circuit 522 adds vertical window border signals to the data, as required, in accordance with the state of left and right vertical bonded signals on leads L.BORD and R.BORD. From circuit 522, display data is sent serially to the display device 506 on lead.DATA3.
  • FIG. 6 A more detailed block diagram of .the window manager 500 is shown in FIG. 6. It comprises a common section 600 which interacts with a plurality (up to sixteen in the exemplary embodiment) of per window sections 602-1 through 602-n.
  • a host interface circuit 614 provides the connection to a host processor 502. Each per window section may be associated with an individual window defined at any given time. Sin ⁇ e the per window sections are identical, only the details of 602-1 are shown.
  • a descriptor registers circuit 604--1 contains a number of registers defining the scre n boundaries, border, stipple and depth of the associated window. These registers are loaded by the host processor via a host interface circuit 614 in the common section.
  • An address generator 608-1 in the per window section uses the register data from circuit 604-1 to generate bitmap addresses for fetching screen data for the associated window. This address data is only used, however, when the respective window is actively being scanned on the screen.
  • a depth priority encoder 618 in the common section continuously interacts with window winner circuits such as 612-1 in each of the per window sections to determine a window with the highest depth at the point on the screen presently being scanned.
  • the "in window" circuit 606-1 in each per window section determines from window definition data and screen position data if the associated window is presently being scanned on the screen.
  • the individual window winner circuits obtain respective depth information from the respective descriptor circuits, such as 604-1 and broadcasts this information to the depth priority encoder 618.
  • Circuit 618 determines the highest depth window at any given time and returns this information to each of the window winner circuits in the per window sections.
  • Outputs from the window winner circuits 612 and the "in window" detectors 606 are examined by the respective address generators 608. If the window area being scanned on the screen is also identified as the present winner, the appropriate address generator 608 is enabled and generates and passes appropriate bitmap addresses to the display memory control circuit 616 for fetching the screen update information.
  • a border detector 610 in each of the per window circuits detects when border areas of windows are being replaced, if borders are defined, and controls the generation of special signals to create the borders on the screen. Thus, data for creating the window borders is not .stored in the bitmaps. The reason for this will become apparent below.
  • a descriptor registers circuit 604 is shown in FIG. 8. When a window is first defined, the defining data arrives on the P.DATA bus 800 from the host processor 502 and is loaded into the registers 802, 804, 806 and 808. These registers are respectively identified as LINE.T, LINE.B, COORD.L, and COORD.R and contain the screen parameters of the window as shown in FIG. 1.
  • the host processor When a window is first defined, the host processor also determines the bitmap addresses for the parameters ADDR.TOP, ADDR.BTM, ADDR.BASE and ADDR.JMP, shown in FIGS. 3 and 4, and loads these into the respective registers 810, 812, 814 and 816.
  • Two remaining registers CNTL.DEPTH and CNTL.STIP are loaded with numbers that define the depth of a window and a background texture (stipple) for the window as displayed on the screen. These are user preferences and may be changed by a user at any time by entering appropriate commands to the host processor.
  • a register address is transmitted on address bus P.ADDR with each set of register data from the host interface.
  • the cell count is outputted on bus PX to two comparators 906 and 908. Respective secondary inputs to these comparators come from the registers COORD.L and COORD.R in the descriptor registers circuit in FIG. 8.
  • comparator 906 sets a flip-flop 910. This flip-flop is reset by comparator 908 as the window is exited on the right.
  • flip-flop 910 produces a signal on its output lead XF whenever the screen raster is within the horizontal bounds of the window. This signal is delayed by one cell time by delay flip-flop 911 to generate a dela'yed signal on output lead XF.P.
  • comparators 910, 912 and flip-flop 914 generate a signal on output lead YEF whenever the screen raster is within the vertical bounds of the window.
  • a signal on lead YLF is an image of that of YEF, but precedes YEF by four raster lines due to the reset states of PIXEL.YL and PIXEL.YE and to the action of comparators 916, 918 and flip-flop 920.
  • Address generator 608, shown in FIG. 11, in each per window circuit uses the "in window” signals from FIG. 9 and the WTNNER signal from FIG. 10 to generate bitmap addresses.
  • Present bitmap address is maintained in a register ADDR.CUR 1100.
  • the cell clock signal appearing on lead 1102 loads an address into register 1100 from one of the sources in the upper part of FIG. 11 at the beginning of each cell time.
  • An output driver 1104 gates the address in register 1100 to the bitmap address leads A19 1 through A00' at the proper times and thence to the common portion of the window manager.
  • Enable signals appearing on lead 1106 to driver 1104 determine when addresses are gated to these address leads.
  • the vertical sync signal V.SYNC enables a driver 1108, which gates the base address of this window into register 1100. This prepares the starting bitmap memory address when the raster first enters the window.
  • the contents of ADDR.CUR are returned on lead 1110 to one input of a fast adding circuit 1112 at the upper right corner of FIG. 11.
  • a second input of adder 1112 is attached to a positive voltage at 1114. This causes adder 1112 to increment the address from ADDR.CUR by one. This incremented address is returned and loaded into register 1100 at the beginning of each cell time while driver 1116 is enabled.
  • the signals appearing on enabling lead 1118 follow the boolean expression
  • Slow adder 1120 adds the contents of register ADDR.JMP (see FIGS. 3 and 4) to the current address. At the beginning of the next screen line, assuming that this line is still within the window, driver 1122 is enabled by the signal on lead
  • driver 1124 (H.SYNC) ( (YEF) (YLF) + (YEF+YLF) ) , and gates the new address into ADDR.CUR.
  • driver 1126 gates the beginning bitmap address into ADDR.CUR when it becomes necessary to loop from the bottom of the bitmap (ADDR.BOTM in
  • FIGS. 3 and 4 to the beginning of the bitmap
  • comparator 1128 compares the contents of register ADDR.BOT in the descriptor registers circuit with ADDR.CUR and enables driver 1126 when a match occurs.
  • multiplexer 1200 and address select 1202 The purpose of multiplexer 1200 and address select 1202 is to partition the address on leads A19' through A02' into two parts and to multiplex the two parts onto a nine lead address bus A.OUT. As shown in FIG. 5, A.OUT extends to the display memory 504. Address select 1202 merely toggles signals on RAS and CAS at proper times based on the word clock to accomplish this purpose. Border detector 610, shown on the right of
  • FIG. 12 generates signals whenever the raster coincides with a border area of a winning window. These signals cause the automatic generation of raster border signals which are modulated into the display signal stream instead of signals from display memory 504.
  • L.BORD 1 and H.BORD' are inputted to the first of three cascaded latch stages 1204, 1206 and 1208 in the display memory control.
  • R.BORD' is inputted to the second latch stage 1206.
  • the least significant address leads A01' and A00' from address generator 608 are inputted to the first latch stage 1204 via a circuit 1210.
  • Circuit 1210 decodes the A00 ' and A01 1 signals to generate the address enable signal AEN, which is also inputted to the first delay stage 1204.
  • the corresponding output signals from the third stage 1208, A00, A01, AEN, L.BORD, H.BORD and R.BORD are the signals actually used for controlling the screen image.
  • a given cell clock signal at latch 1204 gates in the states of its inputs. Two cell clock signals later, these states appear at the output of latch 1208. The one cell difference in delay between
  • R.BORD and L.BORD created by latches 1206 and 1204 is used by the output current 522 to create right edge window borders, as will be seen.
  • An AND gate 1219 in the per window circuitry is enabled when the associated window is the winning window. This causes stipple pattern select signals from the descriptor registers to also be gated to the input of first latch 1204. The corresponding delayed output signals appear at the output STIPPLE of latch 1208 in, synchronizing with the above-described signals for controlling the actual display of data.
  • the signal on lead 1306 is injected into the display data stream on DATA0 by an EXCLUSIVE OR gate 1310.
  • the output of gate 1310 extends to a NAND gate 1310.
  • the output of gate 1310 extends to a NAND gate 1312 which outputs the stream to bus DATAl.
  • Bus DATAl extends to FIFO 520 where the data signals are temporarily stored. Signals for creating a horizontal border on the display device are injected at gate 1312 whenever a H.BORD signal appears on lead 1314.
  • the output control 522 in FIG. 14 performs the final operations to generate the vertical window borders. Cell data from FIFO 520 appears on incoming bus 1400 in sixteen bit parallel format.
  • L.BORD activates gate 1418, which, in turn, activates tick circuit 1420.
  • tick circuit 1420 activates tick circuit 1426, which pulses gates 1412 and 1414 to shift out another cell of data from SRs 1402 and 1404.
  • circuit 1426 pulses OR gate 1416 to generate SO.
  • Gate 1428 is activated when a right-edge border is detected.
  • tick circuit 1430 generates 12 tick pulses. The first eight of these cause eight data bits to be outputted from the least significant SR 1404. Simultaneously, twelve border signals are shifted into SR 1404 by the tick signals applied to OR gate 1432. The first four of these border signals will eventually be outputted from

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Generation (AREA)
  • Digital Computer Display Output (AREA)

Abstract

Un poste de travail à graphique en mode point comprend un ordinateur central (502), des circuits de gestion (500) des fenêtres, une mémoire d'affichage (504), un dispositif d'affichage visuel (506) et des circuits multiplexeurs (510, 520, 522) qui connectent la mémoire d'affichage au dispositif d 'affichage. Les circuits de gestion des fenêtres permettent de diviser la mémoire d'affichage en une pluralité de modes points individuels contigus qui correspondent chacun à une fenêtre affichée différente. Les circuits (500) de gestion des fenêtres sont divisés en une section commune de commande (600) et en sections individuelles de fenêtre (602-N) qui correspondent à chaque fenêtre susceptible d'être définie. L'ordinateur central (502) inscrit des données décrivant les paramètres de chaque fenêtre définie dans les circuits individuels de gestion des fenêtres. Il enregistre également des données à afficher dans les fenêtres (y compris des données cachées) dans des adresses appropriées de chaque mode point. A mesure que l'image affichée par le dispositif (506) est régénérée, les circuits communs et les circuits générateurs chaque fenêtre faisant partie du module de gestion coopèrent pour sélectioner des fenêtres prioritaires, c'est-à-dire, la fenêtre au premier plan sur chaque élément d'image de l'écran. Le contenu approprié du mode point correspodant à la fenêtre prioritaire à n'importe quel moment donné est lu sous la commande du circuit de la fenêtre prioritaire et transmis au dispositif d'affichage (506) via les circuits multiplexeurs.
EP86904601A 1985-07-09 1986-06-27 Poste de travail a graphique en mode point Expired - Lifetime EP0229164B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/753,271 US4700320A (en) 1985-07-09 1985-07-09 Bitmapped graphics workstation
US753271 1985-07-09

Publications (2)

Publication Number Publication Date
EP0229164A1 true EP0229164A1 (fr) 1987-07-22
EP0229164B1 EP0229164B1 (fr) 1991-06-05

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US (1) US4700320A (fr)
EP (1) EP0229164B1 (fr)
JP (1) JPH083784B2 (fr)
KR (1) KR940008546B1 (fr)
DE (1) DE3679651D1 (fr)
ES (1) ES2000653A6 (fr)
WO (1) WO1987000321A1 (fr)

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EP0229164B1 (fr) 1991-06-05
US4700320A (en) 1987-10-13
WO1987000321A1 (fr) 1987-01-15
JPS63500273A (ja) 1988-01-28
KR880700358A (ko) 1988-02-22
DE3679651D1 (de) 1991-07-11
JPH083784B2 (ja) 1996-01-17
ES2000653A6 (es) 1988-03-16
KR940008546B1 (ko) 1994-09-24

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